JP2008166621A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP2008166621A
JP2008166621A JP2006356733A JP2006356733A JP2008166621A JP 2008166621 A JP2008166621 A JP 2008166621A JP 2006356733 A JP2006356733 A JP 2006356733A JP 2006356733 A JP2006356733 A JP 2006356733A JP 2008166621 A JP2008166621 A JP 2008166621A
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Japan
Prior art keywords
semiconductor element
conductive member
bonding pad
semiconductor device
wire
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JP2006356733A
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Japanese (ja)
Inventor
Takayoshi Nishi
貴義 西
Atsushi Mashita
敦 真下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
System Solutions Co Ltd
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Sanyo Electric Co Ltd
Sanyo Semiconductor Co Ltd
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Application filed by Sanyo Electric Co Ltd, Sanyo Semiconductor Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2006356733A priority Critical patent/JP2008166621A/en
Publication of JP2008166621A publication Critical patent/JP2008166621A/en
Pending legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device where the layout of metal small-gauge wires arranged densely has been thought out. <P>SOLUTION: The semiconductor device 10 roughly comprises: an island 14 integral with a lead 16; a semiconductor element 18 adhered to the upper surface of the island 14; the lead 16 where one end approaches the island 14 and the other end is exposed to the outside; a metal small-gauge wire 20 connecting a bonding pad and the lead 16 provided on the upper surface of the semiconductor element 18; and a sealing resin 12 that covers the components and supports them integrally. The bonding pad 24 on the upper surface of the semiconductor element 18 is connected to a connection region 30 of the lead via a plurality of metal small-gauge wires 20, and the long metal small-gauge wires 20 are withdrawn at an angle close to a right angle to the side of the semiconductor element 18 as compared with other metal small-gauge wires. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置およびその製造方法に関し、特に、内蔵される半導体素子に設けた１つのボンディングパッドに多数の金属細線が接続する半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a large number of fine metal wires are connected to one bonding pad provided in a built-in semiconductor element and a manufacturing method thereof.

一般に半導体装置は、金属細線により、中に封止された半導体チップとリードとの間を電気的に接続する。金属細線は、フリップチップ等で応用されるバンプ電極等と異なり、技術の歴史的変遷が長く、その信頼性故に現在も使われている。   In general, a semiconductor device electrically connects a semiconductor chip sealed therein and a lead by a thin metal wire. Unlike bump electrodes, which are applied to flip chips and the like, metal fine wires have a long history of technological change and are still used because of their reliability.

例えば図９に示す半導体装置１００がその一例である。図９（Ａ）は半導体装置１００を上方から見た平面図であり、図９（Ｂ）はその断面図である。矩形で示す符号１０３が半導体チップであり、ここではトランジスタデバイスで説明してある。半導体チップ１０３としては例えば、バイポーラトランジスタ、ＭＯＳトランジスタ等が採用される。   For example, the semiconductor device 100 shown in FIG. 9 is an example. FIG. 9A is a plan view of the semiconductor device 100 as viewed from above, and FIG. 9B is a cross-sectional view thereof. Reference numeral 103 indicated by a rectangle is a semiconductor chip, which is described here as a transistor device. As the semiconductor chip 103, for example, a bipolar transistor, a MOS transistor, or the like is employed.

半導体装置１００の内部には、上記した半導体チップ１０３と電気的に接続される３つのリードが内蔵される。上記した半導体チップ１０３の裏面と電気的に接続して固着されるアイランド状のリード１０２Ａが左端に位置し、右端には、二つのリード１０２Ｂ、１０２Ｃがある。例えば、リード１０２Ａはコレクタリードとなり、一方のリード１０２Ｂ、１０２Ｃがエミッタリード、ベースリードとなる。そして半導体チップ１０３の２つのボンディングパッドは、各々が金属細線１０５を経由して、リード１０２Ｃおよびリード１０２Ｂに接続される。   The semiconductor device 100 includes three leads that are electrically connected to the semiconductor chip 103 described above. An island-shaped lead 102A that is electrically connected and fixed to the back surface of the semiconductor chip 103 is located at the left end, and two leads 102B and 102C are located at the right end. For example, the lead 102A becomes a collector lead, and one of the leads 102B and 102C becomes an emitter lead and a base lead. The two bonding pads of the semiconductor chip 103 are connected to the lead 102C and the lead 102B via the fine metal wire 105, respectively.

そして、リード１０２Ａ、１０２Ｂ、１０２Ｃ、半導体チップ１０３、金属細線１０５は、封止樹脂１０１により一体的に封止されている。また、リード１０２Ａ、１０２Ｂ、１０２Ｃに関しては、その一部が封止樹脂１０１から外部に露出している。   The leads 102A, 102B, and 102C, the semiconductor chip 103, and the fine metal wire 105 are integrally sealed with a sealing resin 101. Further, some of the leads 102A, 102B, and 102C are exposed from the sealing resin 101 to the outside.

金属細線１０５は、半導体チップ１０３のボンディングパッドでボールボンドし、上昇させ、その後でインナーリード（リード１０２Ｂ、１０２Ｃ）まで下降させてスティッチボンドすることにより形成される。   The fine metal wire 105 is formed by ball bonding with a bonding pad of the semiconductor chip 103 and raising it, and then lowering to inner leads (leads 102B and 102C) and stitch bonding.

下記特許文献１の図１および図２では、インナーリードがアイランドの両側に配置されたパッケージが示されている。
特開平９−２９８２５６号公報 FIG. 1 and FIG. 2 of Patent Document 1 below show a package in which inner leads are arranged on both sides of an island.
JP-A-9-298256

しかしながら、例えば、半導体チップ１０３が大電流のスイッチングを行う半導体素子である場合、金属細線１０５のトータルな電気抵抗を引き下げるために、半導体チップ１０３の上面に設けた１つのボンディングパッドに、複数の金属細線１０５が接続される。このような場合では、１つのボンディングパッドに多数の金属細線が密に接続されるので、金属細線同士の接触や交差を排除して、金属細線を効率的にレイアウトすることが困難であった。   However, for example, when the semiconductor chip 103 is a semiconductor element that performs switching of a large current, in order to reduce the total electrical resistance of the thin metal wire 105, a plurality of metals are attached to one bonding pad provided on the upper surface of the semiconductor chip 103. A thin wire 105 is connected. In such a case, since a large number of fine metal wires are closely connected to one bonding pad, it has been difficult to efficiently lay out the fine metal wires by eliminating contact and intersection between the fine metal wires.

更に、製法上に於いては、図９（Ｂ）を参照して、金属細線１０５が半導体チップ１０３の肩部に接触してショートしてしまう問題があった。この理由は、金属細線１０５をリード１０２Ｃの上面に接着させる際に、金属細線１０５に超音波エネルギーを加えると、このエネルギーによる振動で金属細線１０５が垂れ下がるからである。特に、半導体チップ１０３の中央部付近に金属細線１０５が接続されると、金属細線１０５の線長が例えば２．０ｍｍ以上に長くなり、上記した垂れ下がりによるショートの問題が顕著となる。   Further, in the manufacturing method, with reference to FIG. 9B, there is a problem that the thin metal wire 105 contacts the shoulder portion of the semiconductor chip 103 and is short-circuited. This is because, when the fine metal wire 105 is bonded to the upper surface of the lead 102C, if the ultrasonic energy is applied to the fine metal wire 105, the fine metal wire 105 hangs down due to vibration caused by this energy. In particular, when the fine metal wire 105 is connected near the center of the semiconductor chip 103, the wire length of the fine metal wire 105 becomes, for example, 2.0 mm or more, and the above-described short-circuit problem due to drooping becomes significant.

本発明はこのような問題を鑑みて成されたものであり、本発明の主な目的は、密集して配置される金属細線のレイアウトが工夫された半導体装置を提供することにある。更に、本発明の他の目的は、金属細線の垂れ下がりに起因したショートの発生を防ぐ半導体装置の製造方法を提供することにある。   The present invention has been made in view of such problems, and a main object of the present invention is to provide a semiconductor device in which the layout of densely arranged metal wires is devised. Furthermore, another object of the present invention is to provide a method of manufacturing a semiconductor device that prevents occurrence of a short circuit due to sagging of a fine metal wire.

本発明の半導体装置は、上面にボンディングパッドが設けられた半導体素子と、金属細線を経由して前記半導体素子の前記ボンディングパッドと接続される導電部材とを具備し、前記半導体素子の前記ボンディングパッドと前記導電部材とは、複数の前記金属細線を経由して接続され、各々の前記金属細線は、前記ボンディングパッドと接続される第１接続部と、前記導電部材と接続される第２接続部とを含み、前記第１接続部が前記半導体素子の中央寄りに位置する前記金属細線は、前記第１接続部が前記半導体素子の周辺寄り位置する前記金属細線よりも、前記半導体素子の側辺に対して直角に近い角度で引き出されることを特徴とする。   The semiconductor device of the present invention includes a semiconductor element having a bonding pad provided on an upper surface, and a conductive member connected to the bonding pad of the semiconductor element via a thin metal wire, and the bonding pad of the semiconductor element And the conductive member are connected via a plurality of the fine metal wires, and each fine metal wire has a first connection portion connected to the bonding pad and a second connection portion connected to the conductive member. The thin metal wire in which the first connection portion is located closer to the center of the semiconductor element is located on the side of the semiconductor element than the thin metal wire in which the first connection portion is located near the periphery of the semiconductor element. It is drawn out at an angle close to a right angle.

本発明の半導体装置の製造方法は、上面にボンディングパッドが設けられた半導体素子を、アイランド形状の第１導電部材の上面に載置する第１工程と、前記半導体素子の前記ボンディングパッドと、外部端子となる第２導電部材とを金属細線により接続する第２工程と、押圧手段により前記金属細線を下方から上方に押圧して、前記金属細線の中間部を前記半導体素子から離間させる第３工程と、を具備することを特徴とする。   According to another aspect of the present invention, there is provided a semiconductor device manufacturing method including: a first step of placing a semiconductor element having a bonding pad on an upper surface thereof on an upper surface of an island-shaped first conductive member; the bonding pad of the semiconductor element; A second step of connecting the second conductive member to be a terminal with a fine metal wire, and a third step of pressing the fine metal wire upward from below by a pressing means to separate an intermediate portion of the fine metal wire from the semiconductor element It is characterized by comprising.

本発明の半導体装置によれば、金属細線の線長を短くすることでその断線や変形を抑止することができる。具体的には、本発明では、半導体素子の中央寄りに接続する金属細線を、半導体装置の側辺寄りに接続する金属細線よりも、半導体素子の側辺に対して直角に外側に引き出している。このことにより、半導体素子の中央寄りに接続する金属細線の線長が短くなり、金属細線の垂れ下がりや横方向への変形が抑制される。   According to the semiconductor device of the present invention, it is possible to suppress disconnection and deformation by shortening the wire length of the fine metal wire. Specifically, in the present invention, the fine metal wire connected closer to the center of the semiconductor element is drawn outward at a right angle to the side of the semiconductor element than the fine metal wire connected near the side of the semiconductor device. . As a result, the wire length of the fine metal wire connected closer to the center of the semiconductor element is shortened, and the metal fine wire is prevented from sagging and deformed in the lateral direction.

更に、本発明の半導体装置の製造方法によれば、ワイヤボンディング時に金属細線に与えられた超音波エネルギーにより、金属細線が下方に垂れ下がっても、押圧手段により金属細線を上方に押圧する。従って、金属細線の中間部が半導体チップから離間され、両者のショートが防止される。   Furthermore, according to the method for manufacturing a semiconductor device of the present invention, even if the metal thin wire hangs downward due to ultrasonic energy applied to the metal thin wire during wire bonding, the metal thin wire is pressed upward by the pressing means. Therefore, the middle part of the fine metal wires is separated from the semiconductor chip, and short-circuit between them is prevented.

＜第１の実施の形態＞
本実施の形態では、図１および図２を参照して、本実施の形態の半導体装置１０の構成を説明する。図１（Ａ）は半導体装置１０の斜視図であり、図１（Ｂ）は半導体装置１０を上方から見た平面図であり、図１（Ｃ）は半導体装置１０の代表的な断面図である。 <First Embodiment>
In the present embodiment, the configuration of the semiconductor device 10 of the present embodiment will be described with reference to FIGS. 1 and 2. 1A is a perspective view of the semiconductor device 10, FIG. 1B is a plan view of the semiconductor device 10 viewed from above, and FIG. 1C is a typical cross-sectional view of the semiconductor device 10. is there.

図１（Ａ）を参照して、半導体装置１０は、１つの半導体素子が樹脂封止されたリードフレーム型のパッケージであり、対向する側辺から複数のリード１６が外部に露出する構成となっている。具体的には、半導体装置１０は、リード１６と一体で設けられたアイランド１４（導電部材）と、アイランド１４の上面に固着された半導体素子１８と、アイランド１４に一端が接近して他端が外部に露出するリード１６と、半導体素子１８の上面に設けられたボンディングパッドとリード１６とを接続する金属細線２０と、これらの構成要素を被覆して一体的に支持する封止樹脂１２とを主に具備する構成となっている。   Referring to FIG. 1A, a semiconductor device 10 is a lead frame type package in which one semiconductor element is sealed with resin, and a plurality of leads 16 are exposed to the outside from opposite sides. ing. Specifically, the semiconductor device 10 includes an island 14 (conductive member) provided integrally with the lead 16, a semiconductor element 18 fixed to the upper surface of the island 14, one end approaching the island 14, and the other end A lead 16 exposed to the outside, a fine metal wire 20 that connects the bonding pad provided on the upper surface of the semiconductor element 18 and the lead 16, and a sealing resin 12 that covers and integrally supports these components It is mainly configured.

図１（Ｂ）を参照して、アイランド１４およびリード１６の構成を説明する。アイランド１４は正方形形状または矩形形状であり、その平面的な大きさは上面に載置される半導体素子１８よりも若干大きい程度である。アイランド１４の大きさは、例えば、縦×横＝２．０ｍｍ×３．０ｍｍ程度である。アイランド１４の左側側辺からは一体的に複数のリード１６が封止樹脂１２から外側に延在している。ここでは、リード１６Ａ、１６Ｂ、１６Ｃ、１６Ｄの４本のリードが、アイランド１４から連続して一体的に外部に露出している。これらのリード１６Ａ等は、アイランド１４に載置される半導体素子１８の裏面電極（例えばコレクタ電極）に共通に接続されている。これらのリード１６Ａ〜１６Ｄは、互いに等間隔に離間されている。   The configuration of the island 14 and the lead 16 will be described with reference to FIG. The island 14 has a square shape or a rectangular shape, and its planar size is slightly larger than the semiconductor element 18 placed on the upper surface. The size of the island 14 is, for example, about vertical × horizontal = 2.0 mm × 3.0 mm. A plurality of leads 16 integrally extend from the sealing resin 12 to the outside from the left side of the island 14. Here, the four leads 16A, 16B, 16C, and 16D are continuously exposed from the island 14 and integrally exposed to the outside. These leads 16A and the like are commonly connected to the back surface electrode (for example, collector electrode) of the semiconductor element 18 mounted on the island 14. These leads 16A to 16D are spaced apart from each other at equal intervals.

アイランド１４の右側には、一端（左側の端部）がアイランド１４に接近して、他端（右側の端部）が封止樹脂１２から外部に露出する複数のリード１６Ｅ〜１６Ｈが設けられている。具体的には、４つのリード１６Ｅ、１６Ｆ、１６Ｇ、１６Ｈが設けられる。リード１６Ｅは、半導体素子１８の上面に設けられたボンディングパッド２２（例えばゲート電極）と金属細線２０を経由して接続されている。また、リード１６Ｆ、１６Ｇ、１６Ｈは、封止樹脂１２の内部に位置する接続領域３０により一体に連結されている。そして、接続領域３０は、複数の金属細線２０を経由して、半導体素子１８の上面に設けられたボンディングパッド２４と接続されている。ここで、ボンディングパッド２４は、例えばエミッタ電極（ＩＧＢＴの場合）であり、上述したボンディングパッド２２よりも面積が大きく形成される。ここでは、６本の金属細線２０を経由して、ボンディングパッド２４と接続領域３０（リード１６Ｆ等）が接続されており、このことで金属細線２０のトータルな電気抵抗が引き下げられる。   On the right side of the island 14, a plurality of leads 16 </ b> E to 16 </ b> H are provided such that one end (left end) approaches the island 14 and the other end (right end) is exposed to the outside from the sealing resin 12. Yes. Specifically, four leads 16E, 16F, 16G, and 16H are provided. The lead 16E is connected to a bonding pad 22 (for example, a gate electrode) provided on the upper surface of the semiconductor element 18 via a thin metal wire 20. Further, the leads 16F, 16G, and 16H are integrally connected by a connection region 30 located inside the sealing resin 12. The connection region 30 is connected to the bonding pad 24 provided on the upper surface of the semiconductor element 18 via the plurality of fine metal wires 20. Here, the bonding pad 24 is, for example, an emitter electrode (in the case of IGBT), and has a larger area than the bonding pad 22 described above. Here, the bonding pad 24 and the connection region 30 (the lead 16F and the like) are connected via the six fine metal wires 20, whereby the total electric resistance of the fine metal wire 20 is lowered.

なお、上記したアイランド１４およびリード１６は、例えば銅（Ｃｕ）を主材料とする厚みが２００μｍ〜５００μｍ程度の金属箔を、プレス加工またはエッチング加工することにより形成される。   Note that the islands 14 and the leads 16 described above are formed by pressing or etching a metal foil having a thickness of about 200 μm to 500 μm whose main material is copper (Cu), for example.

半導体素子１８は、アイランド１４の上面に固着されており、下面の電極がアイランド１４と接続され、上面に設けたボンディングパッド２２等が金属細線２０を経由してリード１６Ｅ等と接続されている。ここで、半導体素子１８としては、ＭＯＳトランジスタやＩＧＢＴ等の絶縁ゲート型トランジスタが採用される。そして、半導体素子１８がＭＯＳトランジスタの場合は、下面の電極がドレイン電極となり、上面に設けたボンディングパッド２２がゲート電極となり、ボンディングパッド２４がソース電極（主電極）となる。また、半導体素子１８がＩＧＢＴの場合は、下面の電極がコレクタ電極となり、上面のボンディングパッド２２がゲート電極であり、ボンディングパッド２４がエミッタ電極（主電極）となる。また、半導体素子１８としてバイポーラ型トランジスタが採用されてもよく、この場合は、半導体素子１８の裏面、ボンディングパッド２２およびボンディングパッド２４のそれぞれが、コレクタ電極、ベース電極およびエミッタ電極となる。   The semiconductor element 18 is fixed to the upper surface of the island 14, the electrode on the lower surface is connected to the island 14, and the bonding pads 22 and the like provided on the upper surface are connected to the leads 16 </ b> E and the like via the fine metal wires 20. Here, as the semiconductor element 18, an insulated gate transistor such as a MOS transistor or an IGBT is employed. When the semiconductor element 18 is a MOS transistor, the lower electrode serves as a drain electrode, the bonding pad 22 provided on the upper surface serves as a gate electrode, and the bonding pad 24 serves as a source electrode (main electrode). When the semiconductor element 18 is an IGBT, the lower electrode is a collector electrode, the upper bonding pad 22 is a gate electrode, and the bonding pad 24 is an emitter electrode (main electrode). In addition, a bipolar transistor may be employed as the semiconductor element 18. In this case, the back surface of the semiconductor element 18, the bonding pad 22, and the bonding pad 24 serve as a collector electrode, a base electrode, and an emitter electrode, respectively.

本実施の形態では、半導体素子１８のボンディングパッド２２、２４と接続される金属細線２０の全てが半導体素子１８の右側の側辺の上方を通過するように引き出されてリード１６Ｅ等と接続されている。このことにより、図１（Ｂ）を参照して、金属細線２０を経由して接続されるリード１６Ｅ等の全てを、アイランド１４の右側に配置させることが可能となり、半導体装置の構成を簡素化できる。   In the present embodiment, all of the fine metal wires 20 connected to the bonding pads 22 and 24 of the semiconductor element 18 are drawn out so as to pass over the right side of the semiconductor element 18 and connected to the leads 16E and the like. Yes. As a result, referring to FIG. 1B, all of the leads 16E and the like connected via the fine metal wires 20 can be arranged on the right side of the island 14, and the configuration of the semiconductor device is simplified. it can.

図１（Ｃ）を参照して、外部に導出されるリード１６は、所謂ガルウイング形状に曲折されており、外部に露出するリード１６の端部付近は、封止樹脂１２の下面と同一平面上に平坦に延在している。また、アイランド１４は、封止樹脂１２の厚み方向の中央部よりも下方に位置している。このことにより、アイランド１４の上面に固着される半導体素子１８を封止樹脂１２の厚み方向の中央部付近に位置させることが可能となり、半導体装置１０を取り巻く外部雰囲気に温度変化が生じても、半導体素子１８に作用する熱応力を小さくすることができる。   Referring to FIG. 1C, the lead 16 led out to the outside is bent in a so-called gull wing shape, and the vicinity of the end of the lead 16 exposed to the outside is flush with the lower surface of the sealing resin 12. It extends flat. Further, the island 14 is located below the central portion in the thickness direction of the sealing resin 12. As a result, the semiconductor element 18 fixed to the upper surface of the island 14 can be positioned near the center in the thickness direction of the sealing resin 12, and even if a temperature change occurs in the external atmosphere surrounding the semiconductor device 10, The thermal stress acting on the semiconductor element 18 can be reduced.

図２を参照して、次に、金属細線２０の配置を説明する。ここで、図２は、半導体素子１８およびその周辺部を上方から見た平面拡大図である。   Next, the arrangement of the thin metal wires 20 will be described with reference to FIG. Here, FIG. 2 is an enlarged plan view of the semiconductor element 18 and its periphery viewed from above.

この図を参照して、半導体素子１８の上面に設けられたボンディングパッド２２は１つの金属細線２０Ａを経由してリード１６Ｅと接続され、ボンディングパッド２４は複数の金属細線２０Ｂ等を経由して接続領域３０と接続されている。ボンディングパッド２４が複数の金属細線２０Ｂ等を経由して接続領域３０と接続される理由は、例えば数アンペア程度の大電流をボンディングパッド２４が通過するため、金属細線２０Ｂ等のトータルな電気抵抗を引き下げる必要があるからである。   Referring to this figure, bonding pad 22 provided on the upper surface of semiconductor element 18 is connected to lead 16E via one thin metal wire 20A, and bonding pad 24 is connected via a plurality of fine metal wires 20B. It is connected to the area 30. The reason why the bonding pad 24 is connected to the connection region 30 via a plurality of fine metal wires 20B and the like is that, for example, a large current of about several amperes passes through the bonding pad 24, so that the total electrical resistance of the fine metal wires 20B and the like is reduced. This is because it needs to be lowered.

ここで、接続領域３０は、リード１６Ｆ、１６Ｇ、１６Ｈと一体で連続している部位であり、半導体素子１８の側辺と平行に細長く延在している部位である。ここで、金属細線２０Ａ等は、ボールボンディングまたはウェッジボンディングで形成される。   Here, the connection region 30 is a portion that is integrally continuous with the leads 16F, 16G, and 16H, and is a portion that is elongated in parallel to the side of the semiconductor element 18. Here, the fine metal wires 20A and the like are formed by ball bonding or wedge bonding.

金属細線２０Ａは、ボンディングパッド２２と接続される部位である第１接続部２６Ａを一端に有し、リード１６Ｅの上面と接続される部位である第２接続部２８Ａを他端に有する。この構成は、他の金属細線２０Ｂ等も同様であり、金属細線２０Ｂ〜２０Ｇは、ボンディングパッド２４と接続される部位である第１接続部２６Ｂ〜２６Ｇを一端（左側端）に有し、接続領域３０と接続される部位である第２接続部２８Ｂ〜２８Ｇを他端（右端）に有する。   The thin metal wire 20A has a first connection portion 26A that is a portion connected to the bonding pad 22 at one end, and a second connection portion 28A that is a portion connected to the upper surface of the lead 16E at the other end. This configuration is the same for the other fine metal wires 20B and the like, and the fine metal wires 20B to 20G have first connection portions 26B to 26G which are parts connected to the bonding pads 24 at one end (left end), and are connected. It has 2nd connection part 28B-28G which is a site | part connected with the area | region 30 at the other end (right end).

上記した第１接続部２６Ｂ〜２６Ｇは、ボンディングパッド２４の上面に於いて、電流の流れの集中を緩和するために、略等間隔に離間して配置されている。ここでは、第１接続部２６Ｄ、２６Ｆが半導体素子１８の右側の側辺に接近した位置に縦方向に並んで位置している。更に、第１接続部２６Ｂ、２６Ｅ、２６Ｇは、第１接続部２６等よりも内側に（中心に近い位置に）縦方向に並んで配置されている。そして、第１接続部２６Ｃは、前記した他の第１接続部２６Ｂ等よりも中心点５８に近い位置（周辺から離間した位置）に配置されている。ここで、中心点５８とは、半導体素子１８の平面的な中心の点である。   The first connection portions 26B to 26G described above are arranged on the upper surface of the bonding pad 24 so as to be spaced apart at substantially equal intervals in order to alleviate the concentration of current flow. Here, the first connection portions 26 </ b> D and 26 </ b> F are arranged side by side in the vertical direction at positions close to the right side of the semiconductor element 18. Furthermore, the first connection portions 26B, 26E, and 26G are arranged in the vertical direction on the inner side (at a position close to the center) of the first connection portion 26 and the like. The first connection portion 26C is disposed at a position closer to the center point 58 (a position away from the periphery) than the other first connection portions 26B described above. Here, the central point 58 is a planar center point of the semiconductor element 18.

一方、金属細線２０Ｂ〜２０Ｇの第２接続部２８Ｂ〜２８Ｇは、接続領域３０の上面に於いて一直線上（半導体素子１８の側辺に対して平行な直線上）に等間隔に配置される。   On the other hand, the second connection portions 28 </ b> B to 28 </ b> G of the thin metal wires 20 </ b> B to 20 </ b> G are arranged on a straight line (on a straight line parallel to the side of the semiconductor element 18) at equal intervals on the upper surface of the connection region 30.

本実施の形態では、第１接続部が半導体素子の中央寄りの位置する金属細線２０Ｃを、他の金属細線よりも、半導体素子１８の側辺に対して直角に近い角度で外側に引き出している。具体的には、ボンディングパッド２４に接続される金属細線２０の中でも、金属細線２０Ｃの第１接続部２６Ｃは、半導体素子１８の中心点５８に最も接近している。そして、半導体素子１８の右側の側辺と、金属細線２０Ｃとが交差する角度θ３は、例えば、８５度〜９０度程度であり直角に近い。なお、ここで、角度θ１〜θ７は、半導体素子１８の右側の側辺と金属細線２０Ａ〜２０Ｇとが平面的に交差する角度である。この角度が直角（９０度）に近いほど、半導体素子１８の側辺に対して金属細線が直角に引き出されていることになる。   In the present embodiment, the fine metal wire 20C in which the first connection portion is located closer to the center of the semiconductor element is drawn to the outside at an angle closer to a right angle with respect to the side of the semiconductor element 18 than the other fine metal wires. . Specifically, among the fine metal wires 20 connected to the bonding pad 24, the first connection portion 26 </ b> C of the fine metal wire 20 </ b> C is closest to the center point 58 of the semiconductor element 18. The angle θ3 at which the right side of the semiconductor element 18 intersects with the thin metal wire 20C is, for example, about 85 to 90 degrees and is close to a right angle. Here, the angles θ1 to θ7 are angles at which the right side of the semiconductor element 18 and the thin metal wires 20A to 20G intersect in a plane. The closer this angle is to a right angle (90 degrees), the more the fine metal wire is drawn out to the side of the semiconductor element 18.

一方、半導体素子１８の周辺部に接近した位置に第１接続部２６Ｆを有する金属細線２０Ｆでは、角度θ６が例えば１２０度程度となっており、金属細線２０Ｃと比較すると直角（９０度）との差が大きくなっている。また、この事項は、他の金属細線についても言えることであり、角度θ１〜θ７を比較した場合、θ３が最も直角に近い値となっている。   On the other hand, in the thin metal wire 20F having the first connection portion 26F at a position close to the peripheral portion of the semiconductor element 18, the angle θ6 is about 120 degrees, for example, which is a right angle (90 degrees) compared to the thin metal wire 20C. The difference is getting bigger. This matter is also true for other thin metal wires. When the angles θ1 to θ7 are compared, θ3 is a value that is closest to a right angle.

上記のようにすることで、金属細線２０Ｃの線長をできるだけ短くして垂れ下がり等の変形を抑制することができる。具体的には、第１接続部２６Ｃを中心点５８付近に有する金属細線２０Ｃは最も長く形成されるものであり、例えばその長さは２．０ｍｍ程度である。更に、本実施の形態で使用される金属細線は、ボールボンディングを実現するために、直径が２０μｍ程度の細い金線が使用されている。このことから、特に線長が長い金属細線２０Ｃは、ワイヤボンディングの工程で使用される超音波エネルギーや、樹脂封止の際の樹脂圧により、変形しやすい傾向がある。そこで、本実施の形態では、比較的に長い金属細線２０Ｃを、半導体素子１８の側辺に対してできるだけ直角に引き出すことにより、少しでもその線長を短くして、変形を抑制している。なお、例えば、金属細線２０Ｇに関しては、第１接続部２６Ｇが半導体素子１８の周辺寄りに配置されているので、θ７が直角から離れた角度であっても、全体的な線長は長く成らず、変形の恐れが小さい。   By doing as mentioned above, the wire length of the thin metal wire 20C can be made as short as possible to suppress deformation such as drooping. Specifically, the thin metal wire 20C having the first connection portion 26C in the vicinity of the center point 58 is formed to be the longest, for example, the length is about 2.0 mm. Furthermore, the fine metal wire used in the present embodiment is a thin gold wire having a diameter of about 20 μm in order to realize ball bonding. For this reason, the metal thin wire 20C having a particularly long wire length tends to be easily deformed by ultrasonic energy used in the wire bonding process and resin pressure at the time of resin sealing. Therefore, in the present embodiment, by pulling out the relatively long thin metal wire 20C as perpendicular to the side of the semiconductor element 18 as possible, the wire length is shortened as much as possible to suppress deformation. For example, regarding the thin metal wire 20G, since the first connecting portion 26G is disposed near the periphery of the semiconductor element 18, even if θ7 is an angle away from a right angle, the overall line length does not become long. The risk of deformation is small.

換言すると、本実施の形態では、金属細線２０の配置を設計するとき、半導体素子１８の側辺に対して金属細線２０Ｃが略直交するようにしている。具体的には、先ず、互いに略等間隔に配置されるように、ボンディングパッド２４上の第１接続部２６Ｂ〜２６Ｇの位置を決定する。次に、最も線長が長くなる金属細線２０Ｃが、半導体素子１８の側辺と略直交するように、金属細線２０Ｃの向き（θ３）を決定する。次に、他の金属細線２０Ｂ等のレイアウトを決める。具体的には、紙面上にて金属細線２０Ｃよりも上方に位置する金属細線２０Ｂの角度θ２を鋭角にする。また、紙面上にて金属細線２０Ｃよりも下方に位置する金属細線２０Ｄ〜２０Ｇの角度θ４〜θ７を、鈍角にしている。このように設計することで、最も線長が長くなる金属細線２０Ｃの長さをできるだけ短くすることが可能となり、その垂れ下がり等の変形が抑制される。   In other words, in the present embodiment, when designing the arrangement of the fine metal wires 20, the fine metal wires 20 </ b> C are substantially orthogonal to the side of the semiconductor element 18. Specifically, first, the positions of the first connection portions 26B to 26G on the bonding pad 24 are determined so as to be arranged at substantially equal intervals. Next, the direction (θ3) of the fine metal wire 20C is determined so that the fine metal wire 20C having the longest wire length is substantially orthogonal to the side of the semiconductor element 18. Next, the layout of other fine metal wires 20B and the like is determined. Specifically, the angle θ2 of the fine metal wire 20B positioned above the fine metal wire 20C on the paper surface is set to an acute angle. Further, the angles θ4 to θ7 of the thin metal wires 20D to 20G located below the thin metal wire 20C on the paper surface are made obtuse. By designing in this way, the length of the thin metal wire 20C having the longest wire length can be made as short as possible, and deformation such as sagging is suppressed.

ここで、上記した半導体装置１０は、所謂リードフレーム型のパッケージであったが、他の形態のパッケージに、本実施の形態を適用させることもできる。例えば、ガラスエポキシやセラミック等の絶縁材料から成る回路基板が用いられるパッケージに本実施の形態を適用させても良い。この場合は、回路基板の上面に所定の形状の導電パターンを形成し、この導電パターンに半導体素子１８を実装して、半導体素子１８のボンディングパッドと所定の導電パターンとを金属細線を用いて接続する。更に、半導体素子および金属細線が被覆されるように、回路基板の上面が封止樹脂により封止される。また、回路基板の下面には、上面の導電パターンと接続された外部接続電極が設けられる。   Here, the semiconductor device 10 described above is a so-called lead frame type package, but the present embodiment can be applied to other types of packages. For example, the present embodiment may be applied to a package in which a circuit board made of an insulating material such as glass epoxy or ceramic is used. In this case, a conductive pattern having a predetermined shape is formed on the upper surface of the circuit board, the semiconductor element 18 is mounted on the conductive pattern, and the bonding pad of the semiconductor element 18 and the predetermined conductive pattern are connected using a thin metal wire. To do. Furthermore, the upper surface of the circuit board is sealed with a sealing resin so as to cover the semiconductor element and the fine metal wires. An external connection electrode connected to the conductive pattern on the upper surface is provided on the lower surface of the circuit board.

更に、本実施の形態は、アルミニウム等の金属から成る金属基板を用いた半導体装置に適用させることもできる。この場合は、金属基板の上面が樹脂などの絶縁層により全面的に被覆され、この絶縁層の上面に所定の導電パターンが形成される。更に、この導電パターンの上面に半導体素子が実装され、半導体素子のボンディングパッドと導電パターンとが金属細線を用いて接続される。また、この場合は、半導体素子等が被覆されるように金属基板の上面が封止樹脂により被覆されても良いし、回路基板の上面を被覆するケース材により封止が行われても良い。   Furthermore, this embodiment can be applied to a semiconductor device using a metal substrate made of a metal such as aluminum. In this case, the upper surface of the metal substrate is entirely covered with an insulating layer such as a resin, and a predetermined conductive pattern is formed on the upper surface of the insulating layer. Further, a semiconductor element is mounted on the upper surface of the conductive pattern, and the bonding pad of the semiconductor element and the conductive pattern are connected using a fine metal wire. In this case, the upper surface of the metal substrate may be covered with a sealing resin so that the semiconductor element or the like is covered, or sealing may be performed with a case material that covers the upper surface of the circuit board.

更にまた、導電パターンが埋め込まれるタイプの半導体装置に本実施の形態を適用させても良い。この場合は、導電パターンの上面に半導体素子が実装され、半導体素子のボンディングパッドと所定の導電パターンとが金属細線を経由して接続される。そして、導電パターン、金属細線および半導体素子は封止樹脂により被覆され、導電パターンに関しては、上面および側面が封止樹脂により封止され、下面は封止樹脂から外部に露出する。   Furthermore, the present embodiment may be applied to a semiconductor device in which a conductive pattern is embedded. In this case, a semiconductor element is mounted on the upper surface of the conductive pattern, and a bonding pad of the semiconductor element and a predetermined conductive pattern are connected via a fine metal wire. And a conductive pattern, a metal fine wire, and a semiconductor element are coat | covered with sealing resin, and regarding a conductive pattern, an upper surface and a side surface are sealed with sealing resin, and a lower surface is exposed outside from sealing resin.

＜第２の実施の形態＞
本実施の形態では、図３から図８を参照して、半導体装置の製造方法を説明する。本実施の形態の半導体装置の製造方法は、アイランド１４（第１導電部材）に半導体素子１８を実装する工程と、半導体素子１８の上面に設けたボンディングパッドとリード１６（第２導電部材）とを金属細線２０により接続する工程と、突起部５０により下方から金属細線２０を上方に押圧して金属細線２０の中間部を半導体素子１８から離間させる工程とを主に具備する。これらの各工程の詳細を以下にて説明する。 <Second Embodiment>
In the present embodiment, a method for manufacturing a semiconductor device will be described with reference to FIGS. The manufacturing method of the semiconductor device of the present embodiment includes a step of mounting the semiconductor element 18 on the island 14 (first conductive member), a bonding pad and a lead 16 (second conductive member) provided on the upper surface of the semiconductor element 18. And a step of pressing the metal thin wire 20 upward from below by the protrusion 50 to separate the intermediate portion of the metal thin wire 20 from the semiconductor element 18. Details of each of these steps will be described below.

図３を参照して、先ず、アイランド１４およびリード１６から成るユニット３５が多数形成されたリードフレーム３２を用意する。図３（Ａ）はリードフレーム３２を全体的に示す平面図であり、図３（Ｂ）は１つのブロック３４を示す平面図である。   Referring to FIG. 3, first, a lead frame 32 in which a large number of units 35 including islands 14 and leads 16 are formed is prepared. FIG. 3A is a plan view showing the lead frame 32 as a whole, and FIG. 3B is a plan view showing one block 34.

図３（Ａ）を参照して、リードフレーム３２は、例えば銅（Ｃｕ）を主材料とする金属からなり、その厚みは例えば２００μｍ〜５００μｍ程度である。リードフレーム３２は短冊形の形状を有し、５個のブロック３４が等間隔に離間して配置されている。リードフレーム３２の上端部および下端部には、リードフレーム３２を円形に貫通して設けた孔部３６が設けられている。この孔部３６は、各工程に於いてリードフレーム３２の位置合わせや搬送の為に使用される。   Referring to FIG. 3A, the lead frame 32 is made of a metal whose main material is copper (Cu), for example, and has a thickness of about 200 μm to 500 μm, for example. The lead frame 32 has a strip shape, and five blocks 34 are arranged at regular intervals. At the upper end portion and the lower end portion of the lead frame 32, a hole portion 36 that penetrates the lead frame 32 in a circular shape is provided. The hole 36 is used for positioning and transporting the lead frame 32 in each process.

図３（Ｂ）を参照して、１つのブロック３４は複数のユニット３５から成る。ここでは、マトリックス状に配置された６個のユニット３５から１つのブロック３４が構成されている。ここで、ユニット３５とは、１つの半導体装置となるアイランド１４およびリード１６から成る要素単位である。ユニット３５では、中央部付近にアイランド１４が配置され、このアイランド１４を両側から囲むようにリード１６が配置されている。更に、アイランド１４の上下側辺からリードフレーム３２の本体部分に吊りリード３８が延在することにより、アイランド１４は機械的に保持されている。   Referring to FIG. 3B, one block 34 is composed of a plurality of units 35. Here, one block 34 is composed of six units 35 arranged in a matrix. Here, the unit 35 is an element unit composed of the island 14 and the lead 16 that form one semiconductor device. In the unit 35, an island 14 is disposed near the center, and leads 16 are disposed so as to surround the island 14 from both sides. Furthermore, the island 14 is mechanically held by the suspension leads 38 extending from the upper and lower sides of the island 14 to the main body portion of the lead frame 32.

図４を参照して、次に、アイランド１４の上面に半導体素子１８を固着する。図４（Ａ）は本工程を示す平面図であり、図４（Ｂ）は１つのユニット断面図である。   Next, referring to FIG. 4, the semiconductor element 18 is fixed to the upper surface of the island 14. FIG. 4A is a plan view showing this process, and FIG. 4B is a cross-sectional view of one unit.

本工程では、ブロック３４に含まれる全てのユニット３５に於いて、半導体素子１８の固着を行っている。半導体素子１８のアイランド１４の上面への固着は、ＡｕＳｉ共晶法でも良いし、接着剤を用いた固着方法でも良い。ＡｕＳｉ共晶法による場合は、先ず、アイランド１４の上面にＡｕメッキを施し、次に、Ａｕメッキの上に半導体素子１８を載置して高温に加熱することにより、半導体素子１８の実装を行う。ここで、Ａｕメッキに替えてＡｇメッキが使用されても良い。一方、接着剤による場合は、先ず、アイランド１４の上面に接着剤を塗布し、次に、接着剤の上部に半導体素子１８を載置して固着が行われる。ここで接着剤としては、半田、導電性ペースト、絶縁性接着剤等が採用される。半導体素子１８の下面が電極として用いられる場合は、半田または導電性ペースト等の導電性接着材が使用されて半導体素子１８が固着される。一方、半導体素子１８の下面が電極として使用されない場合は、絶縁性接着剤が使用されても良い。   In this step, the semiconductor element 18 is fixed in all the units 35 included in the block 34. The semiconductor element 18 may be fixed to the upper surface of the island 14 by an AuSi eutectic method or a fixing method using an adhesive. In the case of the AuSi eutectic method, first, Au plating is performed on the upper surface of the island 14, and then the semiconductor element 18 is mounted by placing the semiconductor element 18 on the Au plating and heating it to a high temperature. . Here, Ag plating may be used instead of Au plating. On the other hand, in the case of using an adhesive, first, the adhesive is applied to the upper surface of the island 14, and then the semiconductor element 18 is placed on the adhesive to be fixed. Here, solder, a conductive paste, an insulating adhesive, or the like is employed as the adhesive. When the lower surface of the semiconductor element 18 is used as an electrode, the semiconductor element 18 is fixed by using a conductive adhesive such as solder or conductive paste. On the other hand, when the lower surface of the semiconductor element 18 is not used as an electrode, an insulating adhesive may be used.

ここで、実装される半導体素子１８としては、ＭＯＳトランジスタ、ＩＧＢＴ、バイポーラトランジスタ、ＩＣ、ＬＳＩ、システムＬＳＩ等を採用することができる。   Here, as the semiconductor element 18 to be mounted, a MOS transistor, IGBT, bipolar transistor, IC, LSI, system LSI, or the like can be employed.

上記の工程は、図３（Ａ）に示すブロック３４に含まれるユニット３５に対して一括して行われる。   The above steps are performed collectively for the units 35 included in the block 34 shown in FIG.

図５を参照して、次に、アイランド１４に実装された半導体素子１８と、リード１６Ｅ等とを金属細線２０Ａ等を使用して接続する（ワイヤボンディング）。図５（Ａ）は本工程を示す平面図であり、図５（Ｂ）は断面図である。   Referring to FIG. 5, next, the semiconductor element 18 mounted on the island 14 is connected to the lead 16E or the like using a metal thin wire 20A or the like (wire bonding). FIG. 5A is a plan view showing this step, and FIG. 5B is a cross-sectional view.

本工程では、アイランド１４に実装される半導体素子１８として、ＩＧＢＴが採用されている。従って、半導体素子１８の上面に設けたボンディングパッド２２およびボンディングパッド２４は、それぞれが、ゲート電極およびエミッタ電極である。また、半導体素子１８の下面はコレクタ電極と成っており、アイランド１４と導通している。   In this step, an IGBT is employed as the semiconductor element 18 mounted on the island 14. Therefore, the bonding pad 22 and the bonding pad 24 provided on the upper surface of the semiconductor element 18 are a gate electrode and an emitter electrode, respectively. Further, the lower surface of the semiconductor element 18 is a collector electrode and is electrically connected to the island 14.

ワイヤボンディングの方法としては、ボールボンディングとウェッジボンディングが採用可能であり、以下の説明ではボールボンディングが採用された場合を説明する。   As the wire bonding method, ball bonding and wedge bonding can be employed. In the following description, a case where ball bonding is employed will be described.

本工程では、ゲート電極であるボンディングパッド２２は、１本の金属細線２０Ａを経由して接続されており、ボンディングパッド２２側に第１接続部２６Ａを有し、リード１６Ｅ側に第２接続部２８Ａを有する。   In this step, the bonding pad 22 which is a gate electrode is connected via one metal thin wire 20A, has a first connection portion 26A on the bonding pad 22 side, and a second connection portion on the lead 16E side. 28A.

エミッタ電極であるボンディングパッド２４は、複数の金属細線２０Ｂ等を経由して、リードが多数連結された接続領域３０と接続される。ここでは、６本の金属細線２０Ｂ〜２０Ｇを経由して、半導体素子１８のボンディングパッド２４と接続領域３０とが接続されている。金属細線２０Ｂ〜２０Ｇの第１接続部２６Ｂ〜２０Ｇは、ボンディングパッド２４上に略等間隔に配置されており、第２接続部２８Ｂ〜２８Ｇは、接続領域３０の上面に一直線上に配置されている。第２接続部２８Ｂ〜２８Ｇが整列する方向は、半導体素子１８およびアイランド１４の右側の側辺に対して平行である。   The bonding pad 24 which is an emitter electrode is connected to a connection region 30 in which a large number of leads are connected via a plurality of fine metal wires 20B and the like. Here, the bonding pad 24 of the semiconductor element 18 and the connection region 30 are connected via the six fine metal wires 20B to 20G. The first connection portions 26B to 20G of the thin metal wires 20B to 20G are arranged on the bonding pad 24 at substantially equal intervals, and the second connection portions 28B to 28G are arranged on the upper surface of the connection region 30 in a straight line. Yes. The direction in which the second connection portions 28 </ b> B to 28 </ b> G are aligned is parallel to the right side of the semiconductor element 18 and the island 14.

上記した金属細線２０Ｂ〜２０Ｇは、第１接続部２６Ｂ等が接続領域３０に対して接近しているものから順番に形成される。即ち、先ず、金属細線２０Ｄ、２０Ｆが形成され、次に、金属細線２０Ｂ、２０Ｅ、２０Ｇが形成され、最後に、金属細線２０Ｃが形成される。このようにすることで、金属細線同士の接触を抑制して、ワイヤボンディングを行うことができる。   The above-described thin metal wires 20B to 20G are formed in order from the one in which the first connection portion 26B and the like are close to the connection region 30. That is, first, the fine metal wires 20D and 20F are formed, next, the fine metal wires 20B, 20E, and 20G are formed, and finally, the fine metal wire 20C is formed. By doing in this way, contact between metal fine wires can be controlled and wire bonding can be performed.

図６を参照して、次に、上記した金属細線の具体的な製造方法を説明する。図６（Ａ）〜図６（Ｄ）は、ワイヤボンディング工程を説明するための断面図である。本工程では、金属細線２０の上方への盛り上がりを抑制するために、金属細線２０を横から見た形状を、アルファベットのＭ字形状としている。更に、これらの図に於いては、キャピラリ４０が移動する方向を矢印にて示している。なお、以下の説明に於いて、水平方向とは半導体素子１８またはアイランド１４の上面に対して平行な方向であり、垂直方向とはこれらの面に対して垂直な方向である。   Next, a specific method for manufacturing the above-described thin metal wire will be described with reference to FIG. 6A to 6D are cross-sectional views for explaining the wire bonding process. In this step, in order to suppress the upward bulge of the fine metal wires 20, the shape of the fine metal wires 20 viewed from the side is an alphabetic M shape. Furthermore, in these drawings, the direction in which the capillary 40 moves is indicated by an arrow. In the following description, the horizontal direction is a direction parallel to the upper surface of the semiconductor element 18 or the island 14, and the vertical direction is a direction perpendicular to these surfaces.

図６（Ａ）を参照して、先ず、金属細線２０の先端に形成したＡｕボールを半導体素子１８の上面に設けたボンディングパッドに押しつけて、接合エネルギー（超音波振動、加重、加熱）を加え、金属細線２０をボンディングパッドに接合する。ここで、金属細線２０の先端部に設けたＡｕボールを押しつけた部分が第１接続部２６となる。   Referring to FIG. 6A, first, an Au ball formed at the tip of the fine metal wire 20 is pressed against a bonding pad provided on the upper surface of the semiconductor element 18 to apply bonding energy (ultrasonic vibration, weighting, heating). Then, the fine metal wire 20 is bonded to the bonding pad. Here, the portion where the Au ball provided at the tip of the thin metal wire 20 is pressed becomes the first connection portion 26.

次に、キャピラリ４０を半導体素子１８のリード１６から離間する水平方向（Ｓ１）に移動させた後に、垂直上方に移動させる（Ｓ２）。このことにより、金属細線２０の途中に第１屈曲部４２が形成される。   Next, the capillary 40 is moved in the horizontal direction (S1) away from the lead 16 of the semiconductor element 18, and then moved vertically upward (S2). As a result, the first bent portion 42 is formed in the middle of the fine metal wire 20.

図６（Ｂ）を参照して、次に、キャピラリ４０をリード１６側に向かって水平方向（Ｓ３）に移動させ、次に、垂直上方（Ｓ４）に移動させる。このことにより、金属細線２０の途中に第２屈曲部４４が形成される。   Referring to FIG. 6B, next, the capillary 40 is moved in the horizontal direction (S3) toward the lead 16 side, and then moved vertically upward (S4). As a result, the second bent portion 44 is formed in the middle of the fine metal wire 20.

図６（Ｃ）を参照して、次に、キャピラリ４０をリード１６から離間する方向に水平方向（Ｓ５）に移動させた後に、垂直下方（Ｓ６）に移動させて、第３屈曲部４６を形成する。   Referring to FIG. 6C, next, the capillary 40 is moved in the horizontal direction (S5) in a direction away from the lead 16, and then moved vertically downward (S6), so that the third bent portion 46 is moved. Form.

図６（Ｄ）を参照して、最後に、キャピラリ４０をリード１６の上面まで移動させて、金属細線２０をリード１６の上面に着地させた後に、金属細線２０に接合エネルギー（超音波振動、加重、加熱）を加えて、ステッチボンディングする。そして、不図示のワイヤクランプを閉じて金属細線２０を切断する。   6D, finally, after the capillary 40 is moved to the upper surface of the lead 16 and the fine metal wire 20 is landed on the upper surface of the lead 16, the bonding energy (ultrasonic vibration, Apply weight, heat) and stitch bond. Then, the wire clamp (not shown) is closed and the fine metal wire 20 is cut.

以上の工程により、半導体素子１８の上面に設けたボンディングパッドとリード１６とが接続される。上記したワイヤボンディング方法は、図５に示した全ての金属細線２０Ａ〜２０Ｇに対して適用される。ここでは、金属細線２０の中間部に複数の屈曲部を設けて、金属細線２０の断面形状を略Ｍ字としているので、金属細線２０の上方への盛り上がりが抑制されている。このことがパッケージの薄型化に寄与する。   Through the above steps, the bonding pads provided on the upper surface of the semiconductor element 18 and the leads 16 are connected. The wire bonding method described above is applied to all the thin metal wires 20A to 20G shown in FIG. Here, since a plurality of bent portions are provided in the middle portion of the fine metal wire 20 and the cross-sectional shape of the fine metal wire 20 is substantially M-shaped, the upward bulge of the fine metal wire 20 is suppressed. This contributes to thinning of the package.

図７を参照して、次に、金属細線２０を下方から上方に押圧して、金属細線２０の中間部を半導体素子１８から離間させて両者のショートを防止する。図７の各図は、本工程を示す断面図である。   Referring to FIG. 7, next, the fine metal wire 20 is pressed upward from below, and the intermediate portion of the fine metal wire 20 is separated from the semiconductor element 18 to prevent short-circuit between them. Each drawing in FIG. 7 is a cross-sectional view showing this step.

図７（Ａ）を参照して、金属細線２０をリード１６の上面にステッチボンディングするとき、金属細線２０とリード１６の接合部に超音波エネルギーが印加される。ここで、本実施の形態では、ボールボンディングを実現するために金属細線２０として、径が２０μｍ程度の金線を使用しているので、金属細線２０の剛性は弱い。更に、図２等に示されるように、本実施の形態では、一つのボンディングパッドに複数の金属細線２０を接続させるため、どうしても線長が２．０ｍｍ程度以上に長い金属細線２０が存在する。従って、ワイヤボンディング時の超音波エネルギーにより、金属細線２０が垂れ下がり、金属細線２０の中間部が半導体素子１８の肩部に当接してしまう恐れがある。そして、この状態のまま、後の工程を経て半導体装置が完成してしまうと、金属細線２０の中間部と半導体素子１８とがショートして不良が発生する恐れがある。そこで、本実施の形態では、樹脂封止等を行う前に、金属細線２０を下方から上方に押圧して、金属細線２０の中間部を半導体素子１８から離間させている。   Referring to FIG. 7A, when the fine metal wire 20 is stitch bonded to the upper surface of the lead 16, ultrasonic energy is applied to the joint between the fine metal wire 20 and the lead 16. Here, in the present embodiment, since a gold wire having a diameter of about 20 μm is used as the thin metal wire 20 in order to realize ball bonding, the rigidity of the fine metal wire 20 is weak. Further, as shown in FIG. 2 and the like, in the present embodiment, since a plurality of fine metal wires 20 are connected to one bonding pad, there are inevitably long metal wires 20 having a line length of about 2.0 mm or more. Accordingly, there is a possibility that the thin metal wire 20 hangs down due to ultrasonic energy during wire bonding, and an intermediate portion of the thin metal wire 20 comes into contact with the shoulder portion of the semiconductor element 18. And if a semiconductor device is completed through a subsequent process in this state, the intermediate portion of the thin metal wire 20 and the semiconductor element 18 may be short-circuited to cause a defect. Therefore, in the present embodiment, before the resin sealing or the like, the metal thin wire 20 is pressed upward from below to separate the intermediate portion of the metal thin wire 20 from the semiconductor element 18.

図７（Ｂ）を参照して、本実施の形態では、突起部５０が設けられたブロック４８を用いて、金属細線２０を上方に押圧して変形させて、金属細線２０の中間部を半導体素子１８の肩部から離間させている。   Referring to FIG. 7B, in the present embodiment, the metal thin wire 20 is pressed upward and deformed by using the block 48 provided with the protrusion 50, and the intermediate portion of the metal thin wire 20 is formed as a semiconductor. The element 18 is spaced from the shoulder.

ここで、ブロック４８は、例えばステンレス等の金属から成り、図３に示すリードフレーム３２と略同等の平面的大きさであり、リードフレーム３２に下面から当接している。そして、ブロック４８の上面は殆どの領域は平坦面であり、一部を突起させた突起部５０（押圧手段）が設けられている。この突起部５０は、金属細線２０を上方に押圧するために設けられたものであり、その断面は上下方向に長軸を有する楕円を半分にした形状であり、概略的に「かまぼこ形」の形状を有する。   Here, the block 48 is made of a metal such as stainless steel, for example, has a planar size substantially equal to that of the lead frame 32 shown in FIG. The upper surface of the block 48 is almost flat and is provided with a protruding portion 50 (pressing means) partially protruding. The protrusion 50 is provided to press the fine metal wire 20 upward, and its cross section has a shape in which an ellipse having a major axis in the vertical direction is halved, and is roughly “kamaboko”. Has a shape.

突起部５０は、半導体素子１８が実装されるアイランド１４と、金属細線２０が接続されるリード１６との間の領域に設けられている。本実施の形態では、アイランド１４およびリード１６は、図３（Ｂ）に示すようなリードフレーム３２の状態で供給される。従って、突起部５０は、全てのブロック３４に含まれるユニット３５に対応して設けられている。即ち、突起部５０は、これらのユニット３５の内部に於いて、アイランド１４とのリード１６との間の領域に対応する箇所の、ブロック３４の上面に設けられる。   The protrusion 50 is provided in a region between the island 14 on which the semiconductor element 18 is mounted and the lead 16 to which the thin metal wire 20 is connected. In the present embodiment, the island 14 and the lead 16 are supplied in a state of a lead frame 32 as shown in FIG. Accordingly, the protrusions 50 are provided corresponding to the units 35 included in all the blocks 34. That is, the protrusion 50 is provided on the upper surface of the block 34 at a location corresponding to a region between the island 14 and the lead 16 in the unit 35.

本実施の形態では、全ての金属細線２０が半導体素子１８の右側の側面から引き出されているので、１つのユニット３５（図３（Ｂ））に対して１つの突起部５０を設けることにより、１つのユニット３５に含まれる全ての金属細線２０を下方から上方に押圧することができる。   In the present embodiment, since all the thin metal wires 20 are drawn from the right side surface of the semiconductor element 18, by providing one protrusion 50 for one unit 35 (FIG. 3B), All the thin metal wires 20 included in one unit 35 can be pressed upward from below.

図７（Ｃ）を参照して、次に、ブロック４８の上面をリード１６（リードフレーム３２：図３参照）の下面に当接させて、突起部５０により金属細線２０の中間部を下方から上方に押圧して、金属細線２０を半導体素子１８の肩部から離間させる。突起部５０の高さは、ブロック４８をリード１６（リードフレーム）の裏面に当接させたときに、最頂部が半導体素子１８の上面よりも上方に突出するように設定されている。このことにより、突起部５０により、金属細線２０が下方から上方に押圧されるので、先工程にて金属細線２０が垂れ下がっていても、本工程により、金属細線２０の中間部は半導体素子１８から上方に離間される。このとき、金属細線２０は、上方に盛り上がるように塑性変形を起こしているので、ブロック４８をリード１６から離間させても、金属細線２０が再び垂れ下がることはない。   Next, referring to FIG. 7C, the upper surface of the block 48 is brought into contact with the lower surface of the lead 16 (lead frame 32: see FIG. 3), and the intermediate portion of the fine metal wire 20 is viewed from below by the protrusion 50. The metal thin wire 20 is separated from the shoulder portion of the semiconductor element 18 by pressing upward. The height of the protrusion 50 is set so that the topmost portion protrudes above the upper surface of the semiconductor element 18 when the block 48 is brought into contact with the back surface of the lead 16 (lead frame). As a result, the metal thin wire 20 is pressed upward from below by the protrusion 50, so that even if the metal thin wire 20 hangs down in the previous step, the intermediate portion of the metal fine wire 20 is removed from the semiconductor element 18 by this step. Spaced upward. At this time, since the fine metal wires 20 are plastically deformed so as to rise upward, even if the block 48 is separated from the lead 16, the fine metal wires 20 do not hang down again.

更に、本実施の形態では、突起部５０の断面は四角形状ではなく楕円形状と成っているので、上記した工程にて突起部５０が金属細線２０に接触しても、この接触に伴い金属細線２０が損傷したり断線したりする恐れは小さい。   Furthermore, in the present embodiment, the cross section of the protrusion 50 is not rectangular but elliptical, so even if the protrusion 50 comes into contact with the metal thin wire 20 in the above-described process, the metal thin wire is accompanied by this contact. There is little risk that the 20 will be damaged or disconnected.

ここで、上述した突起部５０は、ブロック４８の上面に固定されていたが、突起部５０を可動式にしても良い。   Here, the protrusion 50 described above is fixed to the upper surface of the block 48, but the protrusion 50 may be movable.

図８を参照して、次に、半導体素子１８等を、封止樹脂により封止する。本工程では、熱硬化性樹脂を用いるトランスファーモールドまたは熱可塑性樹脂を用いるインジェクションモールドが採用される。   Referring to FIG. 8, next, the semiconductor element 18 and the like are sealed with a sealing resin. In this step, a transfer mold using a thermosetting resin or an injection mold using a thermoplastic resin is employed.

具体的には、先ず、上金型５４および下金型５６から成る金型５２の内部に形成されたキャビティ６０に、半導体素子１８、アイランド１４、金属細線２０およびリード１６の一部分（インナーリード）を収納させる。次に、キャビティ６０に不図示のゲートから封止樹脂を注入して、半導体素子１８等を封止樹脂により被覆する。その後に、必要に応じて加熱硬化した後に、樹脂封止された半導体素子１８等を金型５２から取り出す。   Specifically, first, the semiconductor element 18, the island 14, the metal thin wire 20, and a part of the lead 16 (inner lead) are formed in the cavity 60 formed in the mold 52 including the upper mold 54 and the lower mold 56. Storing. Next, sealing resin is injected into the cavity 60 from a gate (not shown) to cover the semiconductor element 18 and the like with the sealing resin. Thereafter, after heat-curing as necessary, the resin-encapsulated semiconductor element 18 and the like are taken out from the mold 52.

本工程は、図３に示したリードフレーム３２に構成された各ブロック３４のユニット３５に対して一括して同時に行われる。   This step is performed simultaneously for the units 35 of the respective blocks 34 formed on the lead frame 32 shown in FIG.

上記工程が終了した後は、バリを除去する工程、外装のためのメッキ処理を行う工程、各ユニット３５をリードフレーム３２（図３参照）から分離する工程、各半導体装置を電気的特性により選別する工程、電気的特性や社名等を封止樹脂の外面に印刷する工程、梱包工程等を経て半導体装置は完成品となる。
After the above steps are completed, a step of removing burrs, a step of plating for exterior packaging, a step of separating each unit 35 from the lead frame 32 (see FIG. 3), and selecting each semiconductor device by electrical characteristics The semiconductor device becomes a finished product through a process of performing, a process of printing electrical characteristics, a company name, and the like on the outer surface of the sealing resin, a packing process, and the like.

本発明の半導体装置を示す図であり、（Ａ）は斜視図であり、（Ｂ）は平面図であり、（Ｃ）は断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the semiconductor device of this invention, (A) is a perspective view, (B) is a top view, (C) is sectional drawing. 本発明の半導体装置を示す平面図である。It is a top view which shows the semiconductor device of this invention. 本発明の半導体装置の製造方法を示す図であり、（Ａ）は平面図であり、（Ｂ）は拡大された平面図である。It is a figure which shows the manufacturing method of the semiconductor device of this invention, (A) is a top view, (B) is the enlarged top view. 本発明の半導体装置の製造方法を示す図であり、（Ａ）は平面図であり、（Ｂ）は断面図である。It is a figure which shows the manufacturing method of the semiconductor device of this invention, (A) is a top view, (B) is sectional drawing. 本発明の半導体装置の製造方法を示す図であり、（Ａ）は平面図であり、（Ｂ）は断面図である。It is a figure which shows the manufacturing method of the semiconductor device of this invention, (A) is a top view, (B) is sectional drawing. 本発明の半導体装置の製造方法を示す図であり、（Ａ）−（Ｄ）は断面図である。It is a figure which shows the manufacturing method of the semiconductor device of this invention, and (A)-(D) is sectional drawing. 本発明の半導体装置の製造方法を示す図であり、（Ａ）−（Ｃ）は断面図である。It is a figure which shows the manufacturing method of the semiconductor device of this invention, and (A)-(C) is sectional drawing. 本発明の半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device of this invention. 背景技術の半導体装置を示す図であり、（Ａ）は平面図であり、（Ｂ）は断面図である。It is a figure which shows the semiconductor device of background art, (A) is a top view, (B) is sectional drawing.

符号の説明Explanation of symbols

１０ 半導体装置
１２ 封止樹脂
１４ アイランド
１６、１６Ａ、１６Ｂ、１６Ｃ、１６Ｄ、１６Ｅ、１６Ｆ、１６Ｇ、１６Ｈ リード
１８ 半導体素子
２０、２０Ａ、２０Ｂ、２０Ｃ、２０Ｄ、２０Ｅ、２０Ｆ、２０Ｇ 金属細線
２２ ボンディングパッド
２４ ボンディングパッド
２６、２６Ａ、２６Ｂ、２６Ｃ、２６Ｄ、２６Ｅ、２６Ｆ、２６Ｇ 第１接続部
２８Ａ、２８Ｂ、２８Ｃ、２８Ｄ、２８Ｅ、２８Ｆ、２８Ｇ 第２接続部
３０ 接続領域
３２ リードフレーム
３４ ブロック
３５ ユニット
３６ 孔部
３８ 吊りリード
４０ キャピラリ
４２ 第１屈曲部
４４ 第２屈曲部
４６ 第３屈曲部
４８ ブロック
５０ 突起部
５２ 金型
５４ 上金型
５６ 下金型
５８ 中心点
６０ キャビティ DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 Sealing resin 14 Island 16, 16A, 16B, 16C, 16D, 16E, 16F, 16G, 16H Lead 18 Semiconductor element 20, 20A, 20B, 20C, 20D, 20E, 20F, 20G Metal thin wire 22 Bonding pad 24 Bonding pads 26, 26A, 26B, 26C, 26D, 26E, 26F, 26G First connection portion 28A, 28B, 28C, 28D, 28E, 28F, 28G Second connection portion 30 Connection area 32 Lead frame 34 Block 35 Unit 36 Hole 38 Suspended lead 40 Capillary 42 First bent portion 44 Second bent portion 46 Third bent portion 48 Block 50 Projection portion 52 Mold 54 Upper die 56 Lower die 58 Center point 60 Cavity

Claims (9)

上面にボンディングパッドが設けられた半導体素子と、金属細線を経由して前記半導体素子の前記ボンディングパッドと接続される導電部材とを具備し、
前記半導体素子の前記ボンディングパッドと前記導電部材とは、複数の前記金属細線を経由して接続され、
各々の前記金属細線は、前記ボンディングパッドと接続される第１接続部と、前記導電部材と接続される第２接続部とを含み、
前記第１接続部が前記半導体素子の中央寄りに位置する前記金属細線は、前記第１接続部が前記半導体素子の周辺寄りに位置する前記金属細線よりも、前記半導体素子の側辺に対して直角に近い角度で引き出されることを特徴とする半導体装置。 A semiconductor element provided with a bonding pad on the upper surface, and a conductive member connected to the bonding pad of the semiconductor element via a fine metal wire,
The bonding pad of the semiconductor element and the conductive member are connected via a plurality of the fine metal wires,
Each of the thin metal wires includes a first connection portion connected to the bonding pad and a second connection portion connected to the conductive member,
The thin metal wire in which the first connection portion is located closer to the center of the semiconductor element is closer to the side of the semiconductor element than the thin metal wire in which the first connection portion is located near the periphery of the semiconductor element. A semiconductor device characterized by being drawn out at an angle close to a right angle. 前記半導体素子はディスクリート型トランジスタであり、
前記トランジスタの主電極となる１つの前記ボンディングパッドと、１つの前記導電部材とが、複数の前記金属細線を経由して接続されることを特徴とする請求項１記載の半導体装置。 The semiconductor element is a discrete transistor,
The semiconductor device according to claim 1, wherein one bonding pad serving as a main electrode of the transistor and one conductive member are connected via the plurality of thin metal wires. 前記半導体素子はＩＧＢＴであり、前記半導体素子の上面にゲート電極とエミッタ電極が設けられ、前記半導体素子の裏面にコレクタ電極が設けられ、
前記エミッタ電極が、複数の前記金属細線を経由して前記導電部材と接続されることを特徴とする請求項１記載の半導体装置。 The semiconductor element is an IGBT, a gate electrode and an emitter electrode are provided on the upper surface of the semiconductor element, and a collector electrode is provided on the back surface of the semiconductor element,
The semiconductor device according to claim 1, wherein the emitter electrode is connected to the conductive member via a plurality of the thin metal wires. 全ての前記金属細線を、前記半導体素子の一側辺から引き出すことを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein all the thin metal wires are drawn out from one side of the semiconductor element. 上面にボンディングパッドが設けられた半導体素子を、アイランド形状の第１導電部材の上面に載置する第１工程と、
前記半導体素子の前記ボンディングパッドと、外部端子となる第２導電部材とを金属細線により接続する第２工程と、
押圧手段により前記金属細線を下方から上方に押圧して、前記金属細線の中間部を前記半導体素子から離間させる第３工程と、を具備することを特徴とする半導体装置の製造方法。 A first step of placing a semiconductor element having a bonding pad on the upper surface thereof on the upper surface of the island-shaped first conductive member;
A second step of connecting the bonding pad of the semiconductor element and a second conductive member serving as an external terminal by a thin metal wire;
And a third step of pressing the fine metal wires upward from below by pressing means to separate the intermediate portion of the fine metal wires from the semiconductor element. 前記第３工程では、
前記押圧手段が、前記第１導電部材と前記第２導電部材との間から上方に移動することにより、押圧された前記金属細線の中間部と前記半導体素子とが離間されることを特徴とする請求項５記載の半導体装置の製造方法。 In the third step,
When the pressing means moves upward from between the first conductive member and the second conductive member, the pressed intermediate portion of the thin metal wire and the semiconductor element are separated from each other. A method for manufacturing a semiconductor device according to claim 5. 全ての前記金属細線は、前記半導体素子の１つの側辺から引き出され、
前記第１導電部材と前記第２導電部材との間に直線状に設けた前記押圧手段により前記金属細線を上方に押圧することを特徴とする請求項５記載の半導体装置の製造方法。 All the thin metal wires are drawn from one side of the semiconductor element,
6. The method of manufacturing a semiconductor device according to claim 5, wherein the metal thin wire is pressed upward by the pressing means provided linearly between the first conductive member and the second conductive member. 前記第１工程では、前記第１導電部材および前記第２導電部材は、一体に連結されたリードフレームで供給され、
前記第３工程では、前記第１導電部材と前記第２導電部材との間に前記押圧手段が設けられたブロックをリードフレームの下面に当接させることで、前記押圧手段で前記金属細線を下方から押圧することを特徴とする請求項５記載の半導体装置の製造方法。 In the first step, the first conductive member and the second conductive member are supplied by an integrally connected lead frame,
In the third step, the metal wire is moved downward by the pressing means by bringing the block provided with the pressing means between the first conductive member and the second conductive member into contact with the lower surface of the lead frame. The method of manufacturing a semiconductor device according to claim 5, wherein the pressing is performed from above. 前記押圧手段は、前記ブロックの上面に設けられた、かまぼこ形の突起部であることを特徴とする請求項８記載の半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 8, wherein the pressing means is a semi-cylindrical protrusion provided on the upper surface of the block.
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US10037934B2 (en) 2015-02-05 2018-07-31 Infineon Technologies Austria Ag Semiconductor chip package having contact pins at short side edges
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US9093434B2 (en) 2011-04-04 2015-07-28 Rohm Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US9613927B2 (en) 2011-04-04 2017-04-04 Rohm Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
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