JPS6180846A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6180846A JPS6180846A JP59201674A JP20167484A JPS6180846A JP S6180846 A JPS6180846 A JP S6180846A JP 59201674 A JP59201674 A JP 59201674A JP 20167484 A JP20167484 A JP 20167484A JP S6180846 A JPS6180846 A JP S6180846A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- microcomputer
- memory
- lsi package
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、半導体装置特にマイクロコンピュータのメモ
リー容−ｉＫ関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory capacity of a semiconductor device, particularly a microcomputer.
従来の半導体装置では１例えばＧＡＩＮ３８号日立製作
所発行（１９８３年５月）における５頁に示されるよう
に、ＥＰＲＯＭ搭載形のマイクロコンピュータが知られ
ている。As a conventional semiconductor device, a microcomputer equipped with an EPROM is known, for example, as shown in GAIN No. 38, published by Hitachi, Ltd. (May 1983), page 5.
この方法は、マイクロコンピュータパッケージ上面に搭
載されるメモリ素子の容量が選択可能なため、同一機能
を持ったシングルチップマイクロコンピュータに比ベメ
モリ容量が増加するが、プリント基板実装時、高さに注
意する必要があった。With this method, the capacity of the memory element mounted on the top surface of the microcomputer package can be selected, which increases the memory capacity compared to a single-chip microcomputer with the same functionality, but care must be taken when mounting the printed circuit board. There was a need.
本発明の目的は、１つのＬＳＩパッケージでメモリ容素
の増加が可能なマイクロコンピータを含む半導体装置を
提供することにある。An object of the present invention is to provide a semiconductor device including a microcomputer that can increase the memory capacity in one LSI package.
本発明は、搭載面にマイクロコンビエータチップを搭載
したＬＳＩパッケージにおいて、マイクロコンピュータ
チップ上にメモリーチップを搭載することを特徴とする
ものである。The present invention is characterized in that a memory chip is mounted on the microcomputer chip in an LSI package in which a micro combinator chip is mounted on the mounting surface.
以下１本発明の一実施例を図面を参照して説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第３図は１本発明の上面図であり第４図は第３図におけ
るＡ−Ａ断面図、第３図に示す半導体装置は、第１図に
示すマイクロコンピュータチップと、第２図に示すメモ
リチップと、ＬＳＩパッケージ５から構成されている。FIG. 3 is a top view of the present invention, and FIG. 4 is a sectional view taken along the line A-A in FIG. 3. The semiconductor device shown in FIG. 3 includes the microcomputer chip shown in FIG. It is composed of a memory chip and an LSI package 5.
ＬＳＩパッケージ５の搭載面であるαには、マイクロコ
ンピュータチップ１が搭載されている。このマイクロコ
ンピュータチップ１には、ＬＳＩパッケージ５のピンに
接続するためのポンディングパッド２とメモリーチップ
４との接続を行うバンプ３とを有している。このマイク
ロコンピュータチップに、同様にバンプを有するメモリ
ーチップ４を接続する。A microcomputer chip 1 is mounted on α, which is the mounting surface of the LSI package 5. This microcomputer chip 1 has bonding pads 2 for connecting to pins of an LSI package 5 and bumps 3 for connecting to a memory chip 4. A memory chip 4 similarly having bumps is connected to this microcomputer chip.
以上の様に本実施例によれば、１つのＬＳＩパッケージ
に、マイクロコンピュータチップとメモリーチップが格
納できる効果がある。As described above, this embodiment has the advantage that a microcomputer chip and a memory chip can be housed in one LSI package.
本発明によれば、搭載するメモリーチップに大容量のＲ
σＭを採用することにより、σＳを内蔵したシングルパ
ッケージマイクロコンピュータが可能であり、プリント
基板実装面積の縮少並びにマイクロコンピュータ使用製
品の小型化に効果がある。According to the present invention, the mounted memory chip has a large capacity R.
By employing σM, a single package microcomputer with a built-in σS is possible, which is effective in reducing the printed circuit board mounting area and downsizing products using the microcomputer.
また、搭載するメモリーチップにＲＡＭを採用すること
により、従来のマイクロコンピュータチップのチップ面
積を増大することなく、記憶容量の大きいシングルパッ
ケージマイクロコンピータが可能であり、外付けＲＡＭ
の削減並びにプログラムコントロールの回答性に効果が
ある。In addition, by adopting RAM as the installed memory chip, it is possible to create a single package microcomputer with a large storage capacity without increasing the chip area of a conventional microcomputer chip.
This is effective in reducing the number of requests and improving the responsiveness of program control.
第ｉ図はマイクロコンピュータチップの上面図、第２図
はメモリーチップの上面図、第３図は本発明の一実施例
の半導体装置の上面図、第４図は第３図のＡ−Ａ線断面
図である。
１・・・マイクロコンピュータチップ
２・・・ポンディングパッド
３・・・バンプ、 ４・・・メモリーチップ
５・・・ＬＳＩパッケージウFig. i is a top view of a microcomputer chip, Fig. 2 is a top view of a memory chip, Fig. 3 is a top view of a semiconductor device according to an embodiment of the present invention, and Fig. 4 is a line A-A in Fig. 3. FIG. 1...Microcomputer chip 2...Ponding pad 3...Bump 4...Memory chip 5...LSI package
Claims (1)
ＳＩパッケージにおいて、マイクロコンピュータチップ
上にメモリーチップを搭載することを特徴とする半導体
装置。1.L with a microcomputer chip mounted on the mounting surface
A semiconductor device characterized by mounting a memory chip on a microcomputer chip in an SI package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59201674A JPS6180846A (en) | 1984-09-28 | 1984-09-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59201674A JPS6180846A (en) | 1984-09-28 | 1984-09-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6180846A true JPS6180846A (en) | 1986-04-24 |
Family
ID=16445016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59201674A Pending JPS6180846A (en) | 1984-09-28 | 1984-09-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6180846A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5332922A (en) * | 1990-04-26 | 1994-07-26 | Hitachi, Ltd. | Multi-chip semiconductor package |
| US6534847B2 (en) * | 1999-02-05 | 2003-03-18 | Rohm Co., Ltd. | Semiconductor device |
-
1984
- 1984-09-28 JP JP59201674A patent/JPS6180846A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5332922A (en) * | 1990-04-26 | 1994-07-26 | Hitachi, Ltd. | Multi-chip semiconductor package |
| US5701031A (en) * | 1990-04-26 | 1997-12-23 | Hitachi, Ltd. | Sealed stacked arrangement of semiconductor devices |
| USRE37539E1 (en) | 1990-04-26 | 2002-02-05 | Hitachi, Ltd. | Sealed stacked arrangement of semiconductor devices |
| US6534847B2 (en) * | 1999-02-05 | 2003-03-18 | Rohm Co., Ltd. | Semiconductor device |
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