JPH0574844A - Semiconductor chip - Google Patents
Semiconductor chipInfo
- Publication number
- JPH0574844A JPH0574844A JP3234289A JP23428991A JPH0574844A JP H0574844 A JPH0574844 A JP H0574844A JP 3234289 A JP3234289 A JP 3234289A JP 23428991 A JP23428991 A JP 23428991A JP H0574844 A JPH0574844 A JP H0574844A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- bonding pads
- bonding
- lead frame
- distance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップのボンデ
ィングパッドのレイアウトの改良に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement in the layout of bonding pads on a semiconductor chip.
【０００２】最近のＡＳＩＣ市場の需要は旺盛であり、
高集積，高速，低消費電力，多ピンの要求が高まってい
る。多ピンについての顧客の要求は、小さなチップサイ
ズで出来る限り多くの機能を持たせるように使用ゲート
数を効率良く配置し、かつ出来る限り多数のピンを設け
たいというものである。Demand in the ASIC market has been strong recently,
The demands for high integration, high speed, low power consumption, and high pin count are increasing. A customer's demand for a large number of pins is to efficiently arrange the number of used gates so as to provide as many functions as possible with a small chip size, and to provide as many pins as possible.
【０００３】この傾向は小ゲート(1,000Ｇ〜4,000Ｇ）
のＡＳＩＣに多く、現状では3,000Ｇ〜4,000Ｇの半導体
チップを 160ピンのQuad Flat Package(ＱＦＰ160）や
176ピンのSmall Quad Flat Package(ＳＱＦＰ176 ）に
搭載したいとの要求が多くなっている。This tendency is small gate (1,000G ~ 4,000G)
, 3,000G to 4,000G semiconductor chips are currently used in the ASIC of ASIC of 160 pin Quad Flat Package (QFP160)
There is a growing demand for mounting on a 176-pin Small Quad Flat Package (SQFP176).
【０００４】以上のような状況から、チップサイズの小
さな半導体チップに出来る限り多数のボンディングパッ
ドを設けることが可能な半導体チップが要望されてい
る。Under the circumstances described above, there is a demand for a semiconductor chip in which a large number of bonding pads can be provided on a semiconductor chip having a small chip size.
【０００５】[0005]
【従来の技術】従来の半導体チップについて図２により
詳細に説明する。図２は従来の半導体チップをリードフ
レームに搭載した状態を模式的に示す図である。2. Description of the Related Art A conventional semiconductor chip will be described in detail with reference to FIG. FIG. 2 is a diagram schematically showing a conventional semiconductor chip mounted on a lead frame.
【０００６】図に示すように多数のボンディングパッド
11a を設けた半導体チップ11をリードフレームのダイス
テージ２に搭載し、リードフレームのリード３の先端部
と半導体チップ11のボンディングパッド11a とをボンデ
ィングワイヤ４で接続している。As shown in the figure, a large number of bonding pads
The semiconductor chip 11 provided with 11a is mounted on the die stage 2 of the lead frame, and the tip end of the lead 3 of the lead frame and the bonding pad 11a of the semiconductor chip 11 are connected by the bonding wire 4.
【０００７】この多数のボンディングワイヤ４が相互に
接触するのを避けるための方法として、ボンディング
パッドの間隔を大きくするボンディングワイヤの長さ
に３mm以下という制限を設けるリードのボンディング
点と半導体チップのボンディングパッドの中心とを結ぶ
線と、ボンディングパッドの中心を通る線とのなす角
（以下、入射角と略称する）を30°以上にするという制
限を設けている。As a method for avoiding the contact of a large number of bonding wires 4 with each other, the distance between the bonding wires for increasing the distance between the bonding pads is limited to 3 mm or less. There is a restriction that the angle formed by the line connecting the center of the pad and the line passing through the center of the bonding pad (hereinafter abbreviated as incident angle) is 30 ° or more.
【０００８】中央部のボンディングパッド11a を配置す
る場合には上記の制限に抵触しないが、半導体チップ11
の隅近傍にボンディングパッド11a を配置する場合には
上記の制限に抵触するようになり、良好な状態でワイヤ
ボンディングを行うことが困難になっており、の入射
角の制限を満足させるためには半導体チップ11の隅近傍
のボンディングパッド11aの間隔を拡げて配置しなけれ
ばならなくなり、間隔を拡げるのに応じて限られた範囲
内に配置可能なボンディングパッド11a の数を減少させ
なければならない。When arranging the bonding pad 11a in the central portion, it does not violate the above restriction, but the semiconductor chip 11
When the bonding pad 11a is arranged near the corner of the contact, it violates the above restrictions, making it difficult to perform wire bonding in a good condition. The bonding pads 11a in the vicinity of the corners of the semiconductor chip 11 must be arranged with a wide space, and the number of bonding pads 11a that can be arranged within a limited range must be reduced in accordance with the widening of the space.
【０００９】[0009]
【発明が解決しようとする課題】以上説明した従来の半
導体チップにおいては半導体チップの活性領域に高集積
化し多機能化した素子を搭載することが可能となって
も、良好なワイヤボンディングを行うための上記の三つ
の条件の内のの入射角の条件を満足させるためには半
導体チップ１の隅近傍のボンディングパッドの間隔を拡
げて配置しなければならなくなり、間隔を拡げるのに応
じて限られた範囲内に配置可能なボンディングパッドの
数を減少させなければならないという問題点があり、ど
うしてもボンディングパッドの数を確保するためには半
導体チップの外形寸法を大きくしてボンディングパッド
を配置することが可能な範囲を増加させなければならな
くなり、半導体チップを小型化する傾向に逆行する結果
になるという問題点があった。In the conventional semiconductor chip described above, even if it becomes possible to mount a highly integrated and multifunctional device in the active region of the semiconductor chip, good wire bonding is performed. In order to satisfy the condition of the incident angle among the above three conditions, it is necessary to increase the distance between the bonding pads in the vicinity of the corner of the semiconductor chip 1, and it is limited according to the increase of the distance. There is a problem that the number of bonding pads that can be placed within the range must be reduced, and in order to secure the number of bonding pads, it is necessary to increase the external dimensions of the semiconductor chip and place the bonding pads. There is a problem that it becomes necessary to increase the possible range, which goes against the trend toward miniaturization of semiconductor chips. Was Tsu.
【００１０】本発明は以上のような状況から、簡単且つ
容易に行えるボンディングパッドのレイアウトの変更に
より小型の半導体チップに所望の数のボンディングパッ
ドを配置することが可能となる半導体チップの提供を目
的としたものである。In view of the above circumstances, the present invention has an object to provide a semiconductor chip in which a desired number of bonding pads can be arranged on a small-sized semiconductor chip by simply and easily changing the layout of the bonding pads. It is what
【００１１】[0011]
【課題を解決するための手段】本発明の半導体チップ
は、周辺にボンディングパッドが設けられている半導体
チップであって、このボンディングパッドが均一なピッ
チで設けられており、且つこの半導体チップをダイステ
ージに搭載するリードフレームのリードの先端を連結す
る線と平行して設けられているように構成する。The semiconductor chip of the present invention is a semiconductor chip in which bonding pads are provided on the periphery thereof, and the bonding pads are provided at a uniform pitch, and the semiconductor chip is a die. The lead frame mounted on the stage is configured so as to be provided in parallel with the line connecting the tips of the leads.
【００１２】[0012]
【作用】即ち本発明においては、ボンディングパッドが
半導体チップの辺と平行に設けられておらず、この辺の
中央に設けたボンディングパッドを起点として均一な間
隔で、この半導体チップをダイステージに搭載するリー
ドフレームのリードの先端を連結する線と平行して配置
しているから、ボンディングパッドを配置することが可
能な距離が増加するとともに、半導体チップの隅近傍の
ボンディングパッドと半導体チップの辺との距離がボン
ディングワイヤ長が３mm以内という制限範囲内において
増加することにより、ボンディングパッドの間隔を拡げ
なくても入射角を30°以上にするという制限を満足させ
ることが可能となり、ボンディングパッドの間隔が均一
であることと、ボンディングパッドを配置する距離が増
加することとの相乗作用により、従来の同寸法の半導体
チップのボンディングパッドの数に比してより多くのボ
ンディングパッドを配置することが可能となる。That is, in the present invention, the bonding pads are not provided in parallel with the sides of the semiconductor chip, and the semiconductor chips are mounted on the die stage at uniform intervals with the bonding pad provided at the center of this side as the starting point. Since the tips of the leads of the lead frame are arranged parallel to the connecting line, the distance at which the bonding pads can be arranged is increased, and the bonding pads near the corners of the semiconductor chip and the sides of the semiconductor chip are arranged. By increasing the distance within the limitation range of the bonding wire length of 3 mm or less, it is possible to satisfy the limitation of the incident angle of 30 ° or more without expanding the spacing of the bonding pads, and the spacing of the bonding pads can be increased. Synergy between being uniform and increasing the distance to place bonding pads The use, it is possible to arrange more bonding pads than the number of the bonding pads of the semiconductor chip of the conventional same size.
【００１３】[0013]
【実施例】以下図１により本発明の一実施例の半導体チ
ップについて詳細に説明する。図１は本発明による一実
施例の半導体チップをリードフレームに搭載した状態を
模式的に示す図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor chip according to an embodiment of the present invention will be described in detail below with reference to FIG. FIG. 1 is a diagram schematically showing a state in which a semiconductor chip according to an embodiment of the present invention is mounted on a lead frame.
【００１４】図に示すように多数のボンディングパッド
1aを設けた半導体チップ１をリードフレームのダイステ
ージ２に搭載し、リードフレームのリード３の先端部と
半導体チップ１のボンディングパッド1aとをボンディン
グワイヤ４で接続している。As shown in the figure, a large number of bonding pads
The semiconductor chip 1 provided with 1a is mounted on the die stage 2 of the lead frame, and the tip end of the lead 3 of the lead frame and the bonding pad 1a of the semiconductor chip 1 are connected by the bonding wire 4.
【００１５】本実施例においては、半導体チップ１の辺
の中央に設けたボンディングパッド1aを起点として均一
な間隔で、この半導体チップ１をダイステージ２に搭載
するリードフレームのリード３の先端を連結する線と平
行して配置しているから、ボンディングパッド1aを配置
することが可能な距離が増加するとともに、半導体チッ
プ１の隅近傍のボンディングパッド1aと半導体チップ１
の辺との距離が増加するので、ボンディングパッド1aの
間隔を増加させなくても入射角を30°以上にするという
制限を満足させることが可能となり、ボンディングパッ
ド1aの間隔が均一であることと、ボンディングパッド1a
を配置する距離が増加することとの相乗作用により、従
来の同寸法の半導体チップ１のボンディングパッド1aの
数に比してより多くのボンディングパッド1aを配置する
ことが可能となる。In the present embodiment, the tips of the leads 3 of the lead frame for mounting the semiconductor chip 1 on the die stage 2 are connected at uniform intervals from the bonding pad 1a provided at the center of the side of the semiconductor chip 1. Since the bonding pads 1a are arranged in parallel with each other, the distance at which the bonding pads 1a can be arranged is increased, and the bonding pads 1a near the corners of the semiconductor chip 1 and the semiconductor chip 1 are arranged.
Since the distance from the side of the bonding pad 1a is increased, it is possible to satisfy the restriction that the incident angle is 30 ° or more without increasing the distance between the bonding pads 1a, and the distance between the bonding pads 1a is uniform. , Bonding pad 1a
Due to the synergistic effect of increasing the distance for arranging the bonding pads, it is possible to arrange more bonding pads 1a than the number of bonding pads 1a of the conventional semiconductor chip 1 having the same size.
【００１６】[0016]
【発明の効果】以上の説明から明らかなように、本発明
によれば極めて簡単なボンディングパッドのレイアウト
の変更により、半導体チップの外形寸法を大きくするこ
となく配置可能なボンディングパッドの数を増加するこ
とが可能となる利点があり、著しい経済的及び、信頼性
向上の効果が期待できる半導体チップの提供が可能であ
る。As is apparent from the above description, according to the present invention, the number of bonding pads that can be arranged without increasing the outer dimensions of the semiconductor chip is increased by changing the layout of the bonding pads extremely easily. It is possible to provide a semiconductor chip that has the advantage of being capable of achieving such advantages, and that can be expected to achieve significant economic and reliability improvement effects.
【図１】 本発明による一実施例の半導体チップをリー
ドフレームに搭載した状態を模式的に示す図、FIG. 1 is a diagram schematically showing a state in which a semiconductor chip according to an embodiment of the present invention is mounted on a lead frame,
【図２】 従来の半導体チップをリードフレームに搭載
した状態を模式的に示す図、FIG. 2 is a diagram schematically showing a conventional semiconductor chip mounted on a lead frame;
１は半導体チップ、1aはボンディングパッド、２はダイ
ステージ、３はリード、４はボンディングワイヤ、５は
入射角、1 is a semiconductor chip, 1a is a bonding pad, 2 is a die stage, 3 is a lead, 4 is a bonding wire, 5 is an incident angle,
Claims (1)
れている半導体チップ(1) であって、 前記ボンディングパッド(1a)が均一なピッチで設けられ
ており、且つ前記半導体チップ(1)をダイステージ(2)に
搭載するリードフレームの隣接するリード(3)の先端を
連続して連結する線と平行して設けられていることを特
徴とする半導体チップ。1. A semiconductor chip (1) having a bonding pad (1a) provided on the periphery thereof, wherein the bonding pad (1a) is provided at a uniform pitch, and the semiconductor chip (1) is provided. A semiconductor chip characterized by being provided in parallel with a line that continuously connects the tips of adjacent leads (3) of a lead frame mounted on a die stage (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3234289A JPH0574844A (en) | 1991-09-13 | 1991-09-13 | Semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3234289A JPH0574844A (en) | 1991-09-13 | 1991-09-13 | Semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0574844A true JPH0574844A (en) | 1993-03-26 |
Family
ID=16968653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3234289A Withdrawn JPH0574844A (en) | 1991-09-13 | 1991-09-13 | Semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0574844A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100476925B1 (en) * | 2002-06-26 | 2005-03-17 | 삼성전자주식회사 | Semiconductor chip having pad arrangement for preventing bonding failure and signal skew of pad |
| KR100798296B1 (en) * | 2007-12-12 | 2008-01-28 | 주식회사 파이컴 | Method for arranging a plurality of connection elements along an arch profile |
| US7661809B2 (en) | 2003-11-20 | 2010-02-16 | Canon Kabushiki Kaisha | Method and apparatus for forming image |
-
1991
- 1991-09-13 JP JP3234289A patent/JPH0574844A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100476925B1 (en) * | 2002-06-26 | 2005-03-17 | 삼성전자주식회사 | Semiconductor chip having pad arrangement for preventing bonding failure and signal skew of pad |
| US6949837B2 (en) | 2002-06-26 | 2005-09-27 | Samsung Electronics Co., Ltd. | Bonding pad arrangement method for semiconductor devices |
| US7661809B2 (en) | 2003-11-20 | 2010-02-16 | Canon Kabushiki Kaisha | Method and apparatus for forming image |
| KR100798296B1 (en) * | 2007-12-12 | 2008-01-28 | 주식회사 파이컴 | Method for arranging a plurality of connection elements along an arch profile |
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| A300 | Withdrawal of application because of no request for examination |
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