JP2646988B2 - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JP2646988B2 JP2646988B2 JP5326677A JP32667793A JP2646988B2 JP 2646988 B2 JP2646988 B2 JP 2646988B2 JP 5326677 A JP5326677 A JP 5326677A JP 32667793 A JP32667793 A JP 32667793A JP 2646988 B2 JP2646988 B2 JP 2646988B2
- Authority
- JP
- Japan
- Prior art keywords
- metal substrate
- metal
- resin
- gnd
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
樹脂封止型半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】近年、半導体装置の多ビット並列処理化
に伴ない、バッファーの同時動作数が増加し、ＧＮＤの
強化及びＬＳＩパッケージのインダクタンスを減少させ
る等が必要である。そこで図４に示すように、従来の樹
脂型パッケージは、ピン数を増加してＧＮＤに割り当て
る、ホンディングワイヤの距離をなるべく短かくする等
を行なっていた。またデバイスの縮少化に伴ないパッド
ピッチが狭くなりリードフレームのステッチも狭くな
り、デバイスのパッド近くまでリードフレームのステッ
チをもっていくのが困難なためタブテープを介してデバ
イスとリードフレームを接続していた。また、単にアー
スを目的として金属基板と回路をボンディングワイヤで
接続しているものとして図５ (公開特許公報昭６２−７
３６３８）に示すようなものがある。2. Description of the Related Art In recent years, the number of simultaneous operations of buffers has increased with the parallel processing of multi-bit semiconductor devices, and it is necessary to strengthen GND and reduce the inductance of LSI packages. Therefore, as shown in FIG. 4, in the conventional resin-type package, the number of pins is increased and assigned to GND, and the distance of the bonding wire is made as short as possible. Also, as the device shrinks, the pad pitch becomes narrower and the lead frame stitches become narrower, and it is difficult to stitch the lead frame to near the device pads. Was. FIG. 5 shows that a metal substrate and a circuit are simply connected by bonding wires for the purpose of grounding.
3638).
【０００３】[0003]
【発明が解決しようとする課題】従来の同時動作ノイズ
を減少させる方法では、ＧＮＤピンを多く取らなければ
ならないので信号に使用できるピン数が減少してしま
う、もしくは、ＧＮＤピン数分パッケージのピン数を増
加させるためパッケージが大型化する問題があった。ま
た、ボンディングワイヤの距離を短縮するためデバイス
にリードフレームのステッチを近づけようとするとステ
ッチの幅、強度の点から困難であり、また、リードフレ
ームが細長くなるためインダクタンスが増加という問題
がある。インダクタンスの問題はタブテープを使用して
も同じである。In the conventional method for reducing simultaneous operation noise, the number of GND pins must be increased, so that the number of pins that can be used for signals is reduced, or the number of pins of the package is reduced by the number of GND pins. There has been a problem that the package is increased in size to increase the number. Further, it is difficult to bring the stitches of the lead frame closer to the device in order to shorten the distance of the bonding wires, in view of the width and strength of the stitches, and there is a problem that the lead frame becomes slender and the inductance increases. The problem of the inductance is the same even when the tab tape is used.
【０００４】[0004]
【課題を解決するための手段】本発明の樹脂封止型半導
体装置は、放熱機能を有する金属基板上に絶縁層を介し
てパターン形成された配線層を有し、該金属基板上の一
部に予め形成された金属露出部分にデバイスを固着する
とともに該金属露出部分と該デバイスのＧＮＤをワイヤ
ーボンド等で接続した構造を有する。A resin-encapsulated semiconductor device according to the present invention has a wiring layer patterned on a metal substrate having a heat dissipation function via an insulating layer, and a part of the wiring layer on the metal substrate. The device has a structure in which a device is fixed to an exposed metal portion formed in advance, and the exposed metal portion and the GND of the device are connected by a wire bond or the like.
【０００５】[0005]
【実施例】次に本発明について図面を参照して説明す
る。図１は、本発明の一実施例の樹脂封止型パッケージ
の断面図である。放熱性のある金属基板１上にリードフ
レーム６とデバイス４をボンディングワイヤ５を介して
接続するために絶縁層上に配線層のパターン８を形成す
る。そして金属基板１上の一部に金属露出部分を形成
し、その部分に導電性接着剤２を使用してデバイス４を
固着する。デバイス４は、ボンディングワイヤ５を介し
て信号及びＶDD用の配線層のパターン８に接続され、Ｇ
ＮＤはボンディングワイヤ５によって金属基板１へ接続
される。デバイス４のＧＮＤが金属基板１に接続される
ことによって金属基板１全体をＧＮＤとして使用できる
ため大幅なＧＮＤ強化が計れると共に板状であるために
インダクタンスを大幅に軽減できる。またＧＮＤを金属
基板１で形成するため従来のＧＮＤピン数分を信号に割
当てることができ、パッケージのピンを効率よく使用す
ることができる。その上金属基板１は放熱機能を有する
ためデバイスの熱を効率よく放熱し熱抵抗を減少させ
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a resin-sealed package according to one embodiment of the present invention. A wiring layer pattern 8 is formed on the insulating layer to connect the lead frame 6 and the device 4 via the bonding wires 5 on the metal substrate 1 having heat dissipation. Then, a metal exposed portion is formed on a part of the metal substrate 1, and the device 4 is fixed to the portion using the conductive adhesive 2. The device 4 is connected to a pattern 8 of a signal and VDD wiring layer via a bonding wire 5,
ND is connected to metal substrate 1 by bonding wire 5. When the GND of the device 4 is connected to the metal substrate 1, the entire metal substrate 1 can be used as GND, so that the GND can be greatly enhanced and the plate-like shape can greatly reduce the inductance. In addition, since GND is formed on the metal substrate 1, the number of conventional GND pins can be allocated to signals, and the pins of the package can be used efficiently. In addition, since the metal substrate 1 has a heat radiation function, the heat of the device is efficiently radiated and the thermal resistance is reduced.
【０００６】次に、図２に本発明の一実施例の表面図を
示す。本発明は絶縁層３上に形成した配線層のパターン
８によってパッド９とリードフレーム６を接続するた
め、リードフレームとの直接接続に比べパターン形状に
自由度及び強度があるので、ボンディング及びリードフ
レームの接続が容易になる。またワイヤーボンディング
により接続できるので、タブテープによる方法より組立
が容易である。配線層のパターン８の形状を工夫するこ
とによってインダクタンスを減少できる。Next, FIG. 2 shows a surface view of one embodiment of the present invention. In the present invention, since the pad 9 and the lead frame 6 are connected by the wiring layer pattern 8 formed on the insulating layer 3, the degree of freedom and strength of the pattern shape is higher than the direct connection with the lead frame. Connection becomes easy. Also, since connection can be made by wire bonding, assembly is easier than with a tab tape method. By devising the shape of the wiring layer pattern 8, the inductance can be reduced.
【０００７】図３は、本発明の第２の実施例の樹脂封止
型パッケージの表面図である。これは、図１の一実施例
に加えて、金属基板１の一部を厚い絶縁層１０によって
分離し、ＶDD用金属基板１１を形成する。これによって
ＶDDのピン数を節約することができ、ＶDDのインダクタ
ンスが減少する。またＶDD用金属基板１１が図３のよう
な形状を取ることによりボンディングワイヤを短くでき
コーナ部分でのボンディングワイヤ長の増加を抑えイン
ダクタンス増加を抑えられる。FIG. 3 is a front view of a resin-sealed package according to a second embodiment of the present invention. In this case, in addition to the embodiment of FIG. 1, a part of the metal substrate 1 is separated by a thick insulating layer 10 to form a metal substrate 11 for VDD . This saves V DD pins and reduces V DD inductance. In addition, since the VDD metal substrate 11 has a shape as shown in FIG. 3, the bonding wire can be shortened, and the increase in the bonding wire length at the corner portion can be suppressed, and the increase in inductance can be suppressed.
【０００８】[0008]
【発明の効果】以上説明したように本発明は、金属基板
１上に絶縁層３を介してパターン形成された配線層８を
有し、金属基板１の一部に金属露出部分を持ち、その金
属露出部分にデバイス４を固着し、デバイス４のＧＮＤ
がワイヤボンディングで金属露出部分が接続されている
ことにより、金属基板１がＧＮＤピンの働きをするの
で、パッケージのピンにＧＮＤを割り当てる必要がなく
ピンを効果的に使用できる。ＧＮＤが平板なのでインダ
クタンスを減少できる。広くＧＮＤを取れるので、ＧＮ
Ｄ強化ができる。また、パターン形成された配線層でデ
バイスとリードフレームが接続されるので、パターン形
状を工夫することによりステッチ間隔の狭いリードフレ
ームを作成する必要がない。インダクタンスも減少させ
られ、強度も保てる。また、金属基板１の一部を厚い絶
縁層で分割することによりＶDDも形成でき、ＶDDの強
化、インダクタンスの減少という効果を有する。As described above, the present invention has a wiring layer 8 patterned on a metal substrate 1 with an insulating layer 3 interposed therebetween, and has a metal exposed portion on a part of the metal substrate 1. Device 4 is fixed to the exposed metal part, and GND of device 4
Is connected to the exposed metal portion by wire bonding, the metal substrate 1 functions as a GND pin, so that it is not necessary to assign GND to the package pin, and the pin can be used effectively. Since GND is flat, inductance can be reduced. Because you can get GND widely, GN
D can be strengthened. Further, since the device and the lead frame are connected by the patterned wiring layer, it is not necessary to produce a lead frame with a narrow stitch interval by devising the pattern shape. Inductance is reduced and strength is maintained. V DD can also be formed by dividing a part of the metal substrate 1 with a thick insulating layer, which has the effect of enhancing V DD and reducing inductance.
【図１】本発明の樹脂封止型半導体装置の一実施例の断
面図。FIG. 1 is a sectional view of one embodiment of a resin-sealed semiconductor device of the present invention.
【図２】図１に示す半導体装置の表面図。FIG. 2 is a front view of the semiconductor device shown in FIG. 1;
【図３】本発明の第２の実施例を示す表面図。FIG. 3 is a front view showing a second embodiment of the present invention.
【図４】従来例を示す断面図。FIG. 4 is a sectional view showing a conventional example.
【図５】他の従来例を示す断面図。FIG. 5 is a sectional view showing another conventional example.
１ 金属基板 ２ 導電性接着剤 ３ 絶縁層 ４ デバイス ５ ボンディングワイヤ ６ リードフレーム ７ モールド樹脂 ８ 配線層 ９ パッド １０ 厚い絶縁層 １１ ＶDD用金属基板DESCRIPTION OF SYMBOLS 1 Metal substrate 2 Conductive adhesive 3 Insulating layer 4 Device 5 Bonding wire 6 Lead frame 7 Mold resin 8 Wiring layer 9 Pad 10 Thick insulating layer 11 Metal substrate for VDD
Claims (1)
介してパターン形成された配線層を有し、前記金属基板
上の一部に予め形成された金属露出部分にデバイスを固
着するとともに前記金属露出部分と前記デバイスのＧＮ
Ｄ端をワイヤーボンドで接続し、前記金属露出部分の一
部を絶縁層で分離し、分離した金属露出部分の一方に前
記デバイスのＧＮＤ端を他方に前記デバイスのＶ DD 電源
端をワイヤーボンドで接続したことを特徴とする樹脂封
止型半導体装置。A wiring layer patterned on a metal substrate having a heat radiation function with an insulating layer interposed therebetween, and a device is fixed to an exposed metal portion formed in advance on a part of the metal substrate; Metal exposed part and GN of the device
The D terminal connected by wire bonding, one of the exposed metal
Parts separated by an insulating layer, and one of the separated metal exposed parts is
V DD power supply of the device the GND terminal of the serial device to the other
A resin-encapsulated semiconductor device having ends connected by wire bonds .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5326677A JP2646988B2 (en) | 1993-12-24 | 1993-12-24 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5326677A JP2646988B2 (en) | 1993-12-24 | 1993-12-24 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07183422A JPH07183422A (en) | 1995-07-21 |
| JP2646988B2 true JP2646988B2 (en) | 1997-08-27 |
Family
ID=18190430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5326677A Expired - Fee Related JP2646988B2 (en) | 1993-12-24 | 1993-12-24 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2646988B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005057672A2 (en) * | 2003-12-09 | 2005-06-23 | Gelcore, Llc | Surface mount light emitting chip package |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0217847B2 (en) * | 1982-05-28 | 1990-04-23 | Inoue Japax Res |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0741161Y2 (en) * | 1988-07-20 | 1995-09-20 | 三洋電機株式会社 | Hybrid integrated circuit |
-
1993
- 1993-12-24 JP JP5326677A patent/JP2646988B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0217847B2 (en) * | 1982-05-28 | 1990-04-23 | Inoue Japax Res |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07183422A (en) | 1995-07-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19961022 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970408 |
|
| LAPS | Cancellation because of no payment of annual fees |