JP3305664B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to semiconductor devices, and more particularly to bond pad placement and packaging for semiconductor devices.

[0002]

BACKGROUND OF THE INVENTION The high pin count (hig)
The need for (h pin count) semiconductor devices is well known. Often, high pin count requirements lead to designs that are pad limited. Pad limited des
iign) is determined by the number of pads, as opposed to a core limited design, which is generally limited by the number of transistors required to perform a particular device function. Things. Typically, a semiconductor device is a single row of bond or bond pads with a constant pad pitch.
d pad). The constant pad pitch is considered in the worst case of the semiconductor device (worst cas).
e) Determined by packaging needs. For example, for high pin count packages, the pad pitch is generally determined by the pad located closest to the die corner. These pads generally cause the bonding tools to collide with adjacent bond or bond wires (in
Requires maximum pad pitch to function without terring. Therefore, this worst case pad pitch spacing is used to determine how many pads are fit or fit along the edge of the semiconductor die. A problem with using a single row of evenly spaced bond pads is that it causes a larger die size.

A prior art improvement over traditional single row bond pads having a constant pad pitch is the use of a constant wire pitch as taught in US Pat. No. 5,498,767. A device with a constant wire pitch
A constant wire pitch is maintained while the pad pitch between adjacent pads changes. The constant wire pitch is the orthogonal distance (ort) from the center of the bond pad to the adjacent wire.
(d)
efine). By maintaining a constant wire pitch across the edge of the die, the bond pads are no longer bound by the use of worst case pad spacing. As a result, smaller die dimensions are achieved. However, even with the use of a constant wire pitch arrangement, it is common for a single row of pads to be a limiting factor in the overall dimensions of the device.

[0004]

It has been proposed in the industry to use dual rows of bond pads to further optimize die size for pad limited designs. One such proposal, described in U.S. Pat. No. 5,468,999, describes an orthogonal set of pads.
l sets) to form multiple or multiple rows (mul)
Use a "chip row" bond pad. FIG. 4 of the 5,468,999 patent illustrates how a semiconductor device effectively has three identical bond pad rows. In other words, the second column is a substantial copy or copy of the first column,
Offset or offset from the first row in a direction perpendicular to the die edge. While this offers some die size advantages, the structure is problematic in that it requires the use of multiple loop heights to avoid wire shorting. Using multiple loop heights in the packaging process increases complexity, cost, and reduces overall semiconductor device reliability. In addition, this patent requires bonding wires that are bonded in substantially orthogonal directions. As a result, it is primarily for use in low pin count devices.

Another dual row proposal described in US Pat. No. 5,195,237 uses multiple rows or multiple rows of bond pads. FIG. 3 of the 5,195,237 patent and FIG. 5 of the 5,468,999 patent show that the semiconductor device does not overlap in the direction perpendicular to the die edge (non
-Overlapping, or illustrates how effectively two identical bond pad rows with matching edges can be provided. However,
This prior art teaches individual pads having a constant pad pitch within each row. As a result, the total number of available pads is limited in that the worst case pad pitch must be maintained.

Therefore, a semiconductor device and method that can reduce die size in a pad-limited layout or layout and optimize the number of bond pads for a given die size would be beneficial.

[0007]

SUMMARY OF THE INVENTION The foregoing and other problems are addressed by:
A semiconductor device comprising: a die having four sides (20);
Wherein the first side of the die is the first side of the die
From the first side and parallel to the first side
A first row of bonds positioned substantially along a first axis
A pad, and greater than the first distance from the first side
Is shifted by a second distance and is parallel to the first side.
A second row of bonds positioned substantially along a second axis
And wherein each of the bond pads in the first row is
First and second substantially perpendicular to the first side of the die;
2 sides, and each bond pad in the second row is
A first and a second substantially perpendicular to the first side of b
And the first row of each bond pad in the second row.
Form the pad placement axis, and each pad placement axis is
A corresponding bond pad associated with the first row of bond pads.
And the pad placement axis is the corresponding bond
Does not match the first or second side of the pad and is
The four sides of the die form eight compartments (100) and
Within each of the eight compartments (100)
There is a pitch between the pads, and the pitch is
The distance between the centers of the pads,
Switches within a single compartment from the bond pad at the beginning of the compartment
It varies up to the last bond pad in the compartment.
The problem is solved by the semiconductor device.

The semiconductor device may further include a plurality of conductive interconnects, each of the conductive interconnects being electrically connected to a predetermined one of the first and second rows of bond pads. Extending from the side of the die to outside the die for electrical contact to circuit components, wherein the plurality of conductive interconnects are disposed on substantially the same plane; Can also be provided.

The semiconductor device may further include a plurality of wire bonds in which the plurality of conductive interconnects are connected in a loop between the bond pads and the plurality of bond posts offset from the sides of the die. Wires, each wire connected in a loop between a given bond pad and a given bond post, having substantially the same loop height with respect to the plane containing the conductive interconnects. It can also be configured.

[0010]

[0011] The semiconductor device may also be arranged such that in each section, a bond pad at the beginning of the section is disposed substantially on a center line of one of four sides of the die, and a bond pad at the end of the section is formed at the last bond pad. It may be arranged substantially at a corner of the die, and the pitch between each bond pad may be configured to sequentially increase from the center line to the corner in the first row of bond pads.

[0012]

DETAILED DESCRIPTION It will be appreciated that for simplicity and clarity of description, the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some of the elements have been exaggerated with respect to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.

The present invention provides a dual or constant wire pitch.
es) using multiple row bond pad pad la
Yout) technology. The first of the dual constant wire pitches is obtained between adjacent pads in a pad set or pad set. A second constant wire pitch of the double constant wire pitch is obtained between adjacent pads associated with a different set of pads. The present invention allows for a smaller die area for pad limited designs than the prior art.

The present invention is best understood with reference to the drawings. FIG. 1 shows a peripheral or peripheral area (pe) having an active circuit area 22 for implementing application specific logic and bond pads 26 that may include input / output and power supply pins.
2 illustrates a semiconductor device 20 having a refrigeration area 24. The device 20 has a central edge axis (cent
er edge axes 103, 102, and corner edge axes 10
By dividing the device at 4, 105, it can be divided into octants or octants. The octant 100 present between the corner edge axis 105 and the center edge axis 103 is identified.

FIG. 2 illustrates the octant 100 of FIG. The particular embodiment of FIG. 2 illustrates the use of double constant wire pitch for two rows of bond pads. Starting at the central axis 103 of the octant, adjacent bond pads are divided into specific sets. The number of sets will generally be equal to the number of pads in a given row. In other words, if row 1 and row 2 each had 10 pads per octant, there would be 10 sets of 2 pads each. It should be noted that although the rows need not have the same number of pads, the number of sets will be limited by the rows having a smaller number of pads. In this embodiment, the elements of the set are such that the axes coincident with the sides or sides of the pads intersect or intersect at least one other pad in the set (inter).
(sect) and partially overlap (ove
r-lapping). This is illustrated in FIG. 2 by set 37, wherein axis 61 of pad 60 traverses pad 65, while axis 67 of pad 65 traverses pad 60. Within each set, there will be a minimum overlap of approximately 25% or greater. Another way to explain this relationship is to use a common location coordinate between the first bond pad and at least one other pad in the same set.
). For example, for a two row implementation, both pads have a common X coordinate, assuming that the X axis is parallel to the die edge associated with the bond pad.

As further illustrated in FIG. 2, each individual row has a varying pad pitch. For example,
Row 1 has a first pad pitch that varies between adjacent pads. In the illustrated embodiment, the first pad pitch is smaller near central axis 103 and die corner axis 105
Larger near. For example, pitch P1 is smaller than pitch P2 and pitch P2 is smaller than pitch P3. Row 2 has a corresponding second pad pitch that also varies between adjacent pads. However, the first pad pitch is the second pad pitch.
It does not change to the same as the pad pitch.

In addition, each particular row has a varying rate of pitch increase between adjacent pads. For example, row 1 has a varying first pitch rate (pitch rate: pitch ra).
te). In other words, the value of the pitch P3 obtained by subtracting the value of the pitch P2 is larger than the value of the pitch P2 obtained by subtracting the value of the pitch P1. However, row 2 has a second pitch fraction that is smaller than the pitch fraction of row 1. This should be intuitively illustrated in FIG. 2 by the pitch D1 being greater than the pitch D2, where D1 is the distance from the pad in row 1 closest to the central axis 103 to the pad closest to the corner axis 105. , And D2 is the row 2 closest to the central axis 103.
Is the distance from the pad to the pad closest to the corner axis 105.

Another feature of the present invention is that the pitch between adjacent pads in the set (set pad pitch) is the center split point or center crossover point (cen) of the octant, such as set 36.
That is, the set near the center edge of the octant, such as set 34, is larger than the set pad pitch of the set near ter crossover point.
It should be noted that the term central breakpoint will be discussed further below. Similarly, the set pad pitch near the corners of the octant, such as set 35, is larger than the set pad pitch of the set closer to the midpoint of the octant, such as set 36. In other words, referring to FIG. 2, P1 is greater than P2 and P1
2 is greater than P3.

Still another feature of the present invention is that for a set near the center edge of the octant, a line or line 50 orthogonal to the die edge and a line across or across the center of the set of bond pads. 51 and a positive angle theta (thet
a) 2 occurs. It should be noted that for other embodiments of the invention having three or more rows, only two pads are required to be used to create the traversing line. In other words, not all pads in a set need be linearly aligned. However, closer to the corner of the octant, a negative angle theta 1 occurs between a line 50 'perpendicular to the die edge and a line 52 transverse to the center of the set of bond pads. Therefore, there is a set of pads having an angle of zero degrees, theta, or a set of adjacent pads having opposite angles (ie, one positive and one negative) with respect to orthogonal lines 50, 50 '. There is a central split point. Some octants are reversed such that the negative angle is near the central axis and the positive angle is near the corner axis (reverse
Note that it would be d) or mirrored.

FIG. 3 illustrates a particular embodiment of the present invention in which die 20 is wire bonded to a package to form packaged device 25. Apparatus 25 illustrates a dual constant wire pitch apparatus. Double constant wire pitch is best understood by first analyzing the pads in each set. For example, FIG. 3 shows a set 30 including bond pads 205 and 206 and bond pad 2
A set 31 including 03 and 204 is illustrated. Set 3
Within zero, bond pads 205 and 206 have a wire pitch of WP1. WP1 is the bond pad 206
Note that this is the orthogonal distance between the center of the wire 225 and the wire 225. In this embodiment of the invention, the distance WP1 is the same for all sets and for all adjacent bond pads. Therefore, bond pads 203 and 204 associated with set 31 will also have a wire pitch of a value of WP1. The second of the double wire pitch is obtained by analyzing bond pads that are in adjacent but different sets. For example, bond pad 205 belonging to set 30 and bond pad 204 belonging to set 31
Are considered adjacent bond pads, because the posts to which they are joined are adjacent. Therefore, the wire pitch WP2 is equal to the bond pad 20.
4 is the orthogonal distance between the center of wire 4 and wire 225. The pitch WP2 is repeated between adjacent pads in different sets. Therefore, the wire pitch between pad 202 and pad 203 will also be WP2.

By using a double constant wire pitch as described in this specification, traditional packaging techniques are still used, whereby all wire bonds have a common loop height. It has been determined that it is possible to achieve substantial area savings while having. This avoids problems associated with the prior art where variable loop heights were used to avoid joining different rows.

The empirical or observation that the implementation of the two row double constant wire pitch of the present invention, illustrated in FIG. 4, results in a die area savings of approximately 30% over a single row constant wire pitch device. (Empirically). In addition, it has been determined based on experience or observation that using multiple loop heights and reducing WP1 in the disclosed invention further reduces die area. For example, it has been noted based on the observation that the implementation of the two-row double-constant wire pitch of the present invention with WP1 of zero microns results in a die area savings of approximately 68% over a single-row constant wire pitch device. .

The discussion of the dual-row embodiment extends to other multiple-row embodiments. For example, as illustrated in FIGS. 5 and 6, a three-row embodiment can be implemented. However, when three rows are used, one set has a matching edge (co) across at least one other pad in the group.
defined by those pads that have incident edges.

It has been noted based on experience or observation that the implementation of the three row double constant wire pitch of the present invention results in approximately 39% die area savings over a single row constant wire pitch apparatus. In addition, using multiple loop heights in the disclosed invention, and reducing WP1,
Further reduction in die area was determined based on observations. For example, 3 of the present invention with WP1 equal to zero
For a row configuration, a single row constant wire pitch device (device is a core limit by logic area 22)
It has been noted based on observations that this results in a die area savings of approximately 81% for d).

In addition, a dual row single constant arrangement
A wire pitch layout (not shown) was also considered by the applicant (inventor). However, data based on experience or observation has shown that a double row single wire pitch arrangement results in an increase in die size over a single row constant wire pitch arrangement. Later, it was discovered that the double row double constant wire pitch design resulted in improved die dimensions.

FIGS. 8, 9, and 11 illustrate particular embodiments for a method of determining pad placement within a particular octant. The methods illustrated in FIGS. 8, 9 and 11 are best described with reference to FIGS.

In step 1001, the locations for all bond posts are provided. Generally, the location will be provided in an XY coordinate system. In step 1002, the positions (R1, R2) of the first and second columns are provided. The first and second
Column position specifies the offset from the die edge for each column. R1 and R2 are FIGS. 10 and 12 as lines passing through the center of each pad in the row.
Is illustrated in It should be noted that it does not matter whether the center point or another reference point is used to refer to the location of the pad. Next, a first bond pad is placed in step 1003. In general, the placement of the first bond pad will be determined by the pad pitch and offset from the die edge, and the octant centerline. In one embodiment, the offset is 150 microns. It is also envisioned by the present invention that the first pad can be located partially over the center line.

The first and second wire pitches (WP1,
WP2) is defined in step 1004. Considerations that determine the selection of WP1 and WP2 are included. WP2 is the minimum wire pitch based on manufacturability because it has a direct effect on wire bond tool interference or collision. Wire bond tool interference is WP1
Is not an issue at all, and therefore WP1 is less than WP2. In one embodiment, WP1 is 50 microns, which is the same as the diameter of the two wires, and WP2 is 80 microns. If WP1 is equal to zero,
Multiple loop heights would have to be used.

In step 1007, pad 2 (P
A determination is made as to whether ad2) is a set adjacent pad or a column adjacent pad. If pad 2 is a group adjacent pad, flow proceeds to step 1005. If pad 2 is a row adjacent pad, flow proceeds to step 1006.

FIG. 9 illustrates the detailed method of step 1005 for determining the placement of the set adjacent pads. In step 1101, a line or line P2S2 is defined or defined. As illustrated in FIG. 10, line P2S
2 starts at the second bond pad location and ends at the second bond post location. It should be noted that in step 1101 this is only a definition, because the location of the second pad is not yet known. However, the certain relationship of this line is known, as discussed below.

In step 1102, a line P1I is defined. P1I is the length WP1 (first wire pitch)
Since it is a set adjacent pad. Line P1I is orthogonal to line P2S2. Line P1I
Represents one end point on the first bond pad (P1) and a line P2
It has another end point (I) on S2.

In step 1103, the length of the line P1S2 is defined. This is the distance from pad 1 to post 2. In one embodiment, the length of the line P1S2 is determined using the distance formula and the XY coordinates of the endpoint. Step 11
At 04, the length of line IS2 is determined. This is the distance from the endpoint or endpoint I on line P2S2 to the second bond post. In one embodiment, the distance is determined using Pythagorean theorem and triangle IP1S2. In step 1105, the lines P1S2, IS
2, and the angle of the triangle formed by P1I is determined given the information previously described. In one embodiment, the angle is determined by trigonometry, knowing one angle and two sides. In step 1106, the XY coordinates of point I are determined with the previously determined information. In one embodiment, the XY coordinates of point I are determined by knowing the angle of line IS2 and the XY coordinates of S2. At step 1107, the intersection (intersec) of P2S2 and R2
) is determined to define a second bond pad location (P2). In one embodiment, P2S2
The intersection of and R2 is determined by solving the equation of the two lines. Finally, in step 1108, pad P2 is arranged. In general, the placement step will require defining the pad placement in a semiconductor device layout database.

FIG. 11 illustrates a detailed method of step 1006 for determining the placement of column adjacent pads. In step 1201, a line P2S2 is defined. FIG.
As illustrated at 2, line P2S2 begins at the second bond pad location and ends at the second bond post location.
In step 1202, a line P3I is defined. P
3I has a length WP2 (second wire pitch). Line P3I is orthogonal to line P2S2. Line P3I has one end point on the third bond pad (P3) and the other end point (I) on line P2S2. The actual XY coordinates of line P3I are not yet known because the final placement of pad 3 has not yet been determined. In step 1203,
An XY intersection (N) between the lines P2S2 and R1 is determined. In one embodiment, the XY intersection is determined by knowing the X coordinate of R1 and the equation of line P2S2. In step 1204, the length of line P3N is determined. In step 1205, the line P3N is a line from the pad 3 to the point N on the line P2S2. In one embodiment, the length of line P3N is determined by WP2 divided by the cosine or cosine of angle 1 from step 1202. In step 1206, Y of pad 3
The coordinates are determined by adding the Y coordinate of N and the length of line P3N.

[0034] Once the layout or placement for a given octant is determined, it can be directly or flip-flopped to provide a bond pad layout for the other octants of the die.
g) or can be duplicated or duplicated through mirroring or mirroring techniques.

Although the present invention has been described and illustrated with respect to particular embodiments, it is not intended that the invention be limited to these illustrative embodiments. Modifications and improvements that can be made without departing from the spirit and scope of the invention will occur to those skilled in the art. Therefore, it is intended that the present invention cover all such modifications and improvements as fall within the scope of the appended claims.

[0036]

A semiconductor device and method are provided that can reduce die size in a pad-limited layout or arrangement and optimize the number of bond pads for a given die size.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device divided into octants having two rows of bond pads.

FIG. 2 is a plan view of a bond pad associated with the octant of FIG. 1;

FIG. 3 is a partial plan view of the octant of FIG. 2 with bond pads connected to bond posts of the package.

FIG. 4 is a plan view of the semiconductor device of FIG. 1 with bond pads connected to bond posts of the package.

FIG. 5 is a plan view of a semiconductor device divided into octants having three rows of bond pads.

FIG. 6 is a plan view of a bond pad associated with the octant of FIG. 5;

FIG. 7 is a plan view of the semiconductor device of FIG. 5 with bond pads connected to bond posts of the package.

FIG. 8 is a flowchart of a method for determining a pad arrangement for a semiconductor device.

FIG. 9 is a flowchart of a method of determining a pad arrangement for a semiconductor device.

FIG. 10 is a plan view of a bond pad to bond post connection supporting the method of FIGS. 8, 9 and 11;

FIG. 11 is a flowchart of a method for determining a pad arrangement for a semiconductor device.

FIG. 12 is a plan view of a bond pad to bond post connection supporting the method of FIGS. 8, 9 and 11;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 12 Bond post 14 Wire 20 Semiconductor device 22 Active circuit area 24 Peripheral area 26 Bond pad 30-37 set 100 Octant 102, 103 Central edge axis 104, 105 Corner edge axis 201-206 Bond pad 211-216 Bond post 221 226 wire 322 active circuit area 324 peripheral area 401-409 bond pad 411-419 bond post 421-429 wire

Continued on the front page (72) Inventor Ashok Sri Kantappa Metric Boulevard, Austin, 78758, Texas, USA 12349 Apartment 1319 (72) Inventor Laxmina Leyan Shama 78729, Texas, U.S.A., Tantara Drive, 12720 (56) References JP-A-4-361538 (JP, A) JP-A-1-278736 (JP, A) JP-A-5-29377 (JP, A) JP-A-2-56942 (JP, A) ( 58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/60

Claims (4)

(57) [Claims] 1. A semiconductor device, comprising:A die (20) having four sides, Wherein the first side of the die comprises: Offset from the first side of the die by a first distance and forward
Substantially along a first axis parallel to the first side.
A first row of bond pads, and Before the first side
Shifted by a second distance greater than the first distance and before
And substantially disposed along a second axis parallel to the first side.
A second row of bond pads, Has, Each bond pad in the first row is connected to the first row of the die.
Having first and second sides substantially perpendicular to the sides, Each bond pad of the second row is connected to the first row of the die.
A first side and a second side substantially perpendicular to the side;
The first side of each bond pad in the second row is a pad arrangement.
Form a stationary axis, Each pad placement axis is associated with the first row of bond pads.
Across the corresponding bond pads in a row
An axis is the first or second of the corresponding bond pads.
Does not match the side of The four sides of the die are eight compartments
(100) and that of said eight compartments (100)
The pitch between each bond pad in each row within each
The pitch is the distance between the centers of adjacent bond pads.
The pitch for each row is
From the first bond pad to the last bond pad
Change up to A semiconductor device characterized by the above-mentioned. 2. A plurality of conductive interconnects (14).
Wherein each of said conductive interconnects (14) is in electrical contact with a predetermined one of said first and second rows of bond pads (26) and is electrically connected to circuit components. 2. The method of claim 1, further comprising extending from an edge of the die to outside of the die for contact, wherein the plurality of conductive interconnects (14) are disposed on substantially the same plane. Semiconductor device. 3. The plurality of conductive interconnects (14) comprise a plurality of wires forming a looped wire bond between the bond pad and a plurality of bond posts offset from a side of the die. Yes, given bond pad (2
Each wire connected in a loop between 6) and a given bond post (12) has substantially the same loop height relative to the plane containing said conductive interconnect (14); The semiconductor device according to claim 2. 4. In each section, the first bond pad (26) of the section is located substantially at the center line of one of the four sides of the die, and the last bond pad of the section is located on the die. 2. The semiconductor device according to claim 1 , wherein the semiconductor device is disposed substantially at a corner, and the pitch between the bond pads sequentially increases from the center line to the corner in the first row of bond pads.