JPS63244853A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS63244853A JPS63244853A JP62080201A JP8020187A JPS63244853A JP S63244853 A JPS63244853 A JP S63244853A JP 62080201 A JP62080201 A JP 62080201A JP 8020187 A JP8020187 A JP 8020187A JP S63244853 A JPS63244853 A JP S63244853A
- Authority
- JP
- Japan
- Prior art keywords
- pads
- lsi chip
- pad
- electrical inspection
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 238000012360 testing method Methods 0.000 claims description 19
- 238000007689 inspection Methods 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 2
- 239000010931 gold Substances 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 239000011347 resin Substances 0.000 abstract description 2
- 229920005989 resin Polymers 0.000 abstract description 2
- 208000032544 Cicatrix Diseases 0.000 abstract 1
- 229920001721 polyimide Polymers 0.000 abstract 1
- 239000009719 polyimide resin Substances 0.000 abstract 1
- 231100000241 scar Toxicity 0.000 abstract 1
- 230000037387 scars Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 241001422033 Thestylus Species 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011253 protective coating Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特に集積回路チッ
プ（以下、ＬＳＩチップという、）のパッド構造を改善
した半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which the pad structure of an integrated circuit chip (hereinafter referred to as an LSI chip) is improved.
従来、この種のＬＳＩチップにおいては、ＬＳＩチップ
表面上に形成する電源用パッド及び入出力信号用パッド
が周辺部に一列配列され、それらパッドを用いて電気検
査および端子接続を行なう構造となっていた。Conventionally, this type of LSI chip has a structure in which power supply pads and input/output signal pads formed on the surface of the LSI chip are arranged in a row around the periphery, and these pads are used to perform electrical inspection and terminal connections. Ta.
第５図はかかる従来のＬＳＩチップの平面図である。FIG. 5 is a plan view of such a conventional LSI chip.
第５図に示すように、ＬＳＩチップ１の四辺にはその周
辺部に接続用パッド８が形成され、このパッド８を用い
てＬＳＩチップ１の電気検査および外部リードとの接続
を行なっている。As shown in FIG. 5, connection pads 8 are formed around the four sides of the LSI chip 1, and the pads 8 are used for electrical testing of the LSI chip 1 and for connection to external leads.
上述した従来のＬＳＩチップは、要するにウェーハでの
ＬＳＩチップの電気検査用のパッドとボンディング接続
するためのパッドとを兼ねた構造が最も一般的である。In short, the conventional LSI chip described above most commonly has a structure that serves both as a pad for electrical inspection of the LSI chip on a wafer and as a pad for bonding connection.
しかしながら、かかる構造のＬＳＩチップにおいては、
電気検査時における検査針の針圧による機械的ストレス
によってパッドにへこみや傷が発生してしまう問題があ
る。従って、結果的にはＬＳＩチップにおけるリード剥
れやバッド剥れが発生し易くなり、十分な接続の信頼性
が保証できないという欠点がある。However, in an LSI chip with such a structure,
There is a problem in that the pad is dented or scratched due to mechanical stress caused by the pressure of the test needle during electrical testing. Therefore, as a result, lead peeling and pad peeling in the LSI chip are likely to occur, and there is a drawback that sufficient connection reliability cannot be guaranteed.
本発明の目的は、かかる接続の信頼性を向上させる半導
体集積回路装置を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit device that improves the reliability of such connections.
本発明は表面上の四辺の各辺にそれぞれ複数個のパッド
を設けた半導体集積回路装置において、内側に形成する
電気検査用パッドと、前記電気検査用パッドに対応して
その外側に設けた外部リード接続用パッドと、前記電気
検査用パッドおよび前記外部リード接続用パッドをそれ
ぞれ接続する電気的接続手段とを含んで構成される。The present invention relates to a semiconductor integrated circuit device in which a plurality of pads are provided on each of the four sides on the surface, in which electrical testing pads are formed on the inside, and external pads are provided on the outside corresponding to the electrical testing pads. The device includes a lead connection pad, and electrical connection means for connecting the electrical testing pad and the external lead connection pad, respectively.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第一の実施例を説明するためのＬＳＩ
チップの平面図である。FIG. 1 is an LSI for explaining the first embodiment of the present invention.
FIG. 3 is a plan view of the chip.
第１図に示すように、かかるＬＳＩチップ１はその表面
の周辺部に周知のメッキ技術により金メッキされたポン
ディングパッド２と電気検査用パッド３及びこれらパッ
ド２，３を電気的に接続する配線４が形成されている。As shown in FIG. 1, such an LSI chip 1 includes a bonding pad 2 and an electrical testing pad 3 which are plated with gold using a well-known plating technique on the periphery of the surface thereof, and wiring that electrically connects these pads 2 and 3. 4 is formed.
第２図は第１図に示すＬＳＩチップのＡ−Ａ’線断面図
である。FIG. 2 is a cross-sectional view taken along line AA' of the LSI chip shown in FIG.
第２図に示すように、かかるＬＳＩチップはシリコン等
の半導体基板５上に前述したポンディングパッド２．電
気検査用パッド３．配線４が形成され、次いで、ポリイ
ミド樹脂のような保護用樹脂６により前記両バッド２，
３及び配線４を含まない範囲を被覆して実現している。As shown in FIG. 2, such an LSI chip has the above-mentioned bonding pads 2. Electrical testing pad 3. A wiring 4 is formed, and then both the pads 2,
This is achieved by covering the area that does not include 3 and wiring 4.
かかる構造とすることにより、ウェーハでのＬＳＩチッ
プ１の電気検査用のパッド３と外部リードへの接続を行
なうためのパッド２とが独立しているので、前記パッド
３を用いた電気検査時の検査針の針圧によるへこみや傷
等の機械的ストレスはポンディングパッド２に影響を及
ぼさないで済む。With this structure, the pads 3 for electrical testing of the LSI chip 1 on the wafer and the pads 2 for connecting to external leads are independent, so that the pads 3 for electrical testing using the pads 3 are independent of each other. Mechanical stress such as dents and scratches caused by the pressure of the test needle does not affect the bonding pad 2.
第３図は本発明の第二の実施例を説明するためのＬＳＩ
チップの平面図である。FIG. 3 is an LSI for explaining the second embodiment of the present invention.
FIG. 3 is a plan view of the chip.
第３図に示すように、かかるＬＳＩチップ１はポンディ
ングパッド２および電気検査用パッド３を形成するに先
立ち、基板上に配線層７を形成しておくものである。As shown in FIG. 3, in the LSI chip 1, a wiring layer 7 is formed on the substrate before the bonding pads 2 and the electrical testing pads 3 are formed.
第４図は第３図におけるＬＳＩチップのＢ−Ｂ′線断面
図である。FIG. 4 is a sectional view taken along line B-B' of the LSI chip in FIG.
第４図に示すように、シリコン基板５上に配線７を形成
した後、両バッド２，３を形成し、その上から保護用被
覆６を形成するものである。この場合も電気検査用パッ
ド２とポンディングパッド３とを電気的に接続している
ので、前述の第一の実施例と同様の利点がある。As shown in FIG. 4, after wiring 7 is formed on a silicon substrate 5, both pads 2 and 3 are formed, and a protective coating 6 is formed thereon. Also in this case, since the electrical testing pad 2 and the bonding pad 3 are electrically connected, there are advantages similar to those of the first embodiment described above.
以上説明したように、本発明はＬＳＩチップの表面上の
四辺の周辺部の内側に電気検査を行なうためのパッドと
その外側に外部リードを・接続するためのパッドとを配
置しそれぞれ電気的に接続することにより、ウェーハで
の電気検査は前記内側のパッドのみで行なうことが可能
になった。従って、検査針の針圧の機械的ストレスによ
るへこみや傷が外側のパッドには全く影響を及は゛さな
いので、ＬＳＩチップにおける接続の信頼性を向上させ
ることができる効果がある。As explained above, the present invention arranges pads for electrical testing inside the peripheral parts of the four sides on the surface of an LSI chip, and pads for connecting external leads on the outside of the pads, respectively. By connecting them, it became possible to perform electrical testing on the wafer using only the inner pads. Therefore, dents and scratches caused by the mechanical stress of the stylus pressure of the test needle do not affect the outer pads at all, which has the effect of improving the reliability of connections in the LSI chip.
第１図は本発明の第一の実施例を説明するためのＬＳＩ
チップの平面図、第２図は第１図におけるＬＳＩチップ
のＡ−Ａ’線断面図、第３図は本発明の第二の実施例を
説明するためのＬＳＩチップの平面図、第４図は第３図
における同様のＢ−Ｂ′線断面図、第５図は従来の一例
を説明するためのＬＳＩチップの平面図である。
１・・・ＬＳＩチップ、２・・・ポンディングパッド、
３・・・電気検査用パッド、４．７・・・配線、５・・
・シリコン基板、６・・・保護用樹脂。
八゛
＃Ｉ凹
第２ 凹
り
奉３ 図
第４図FIG. 1 is an LSI for explaining the first embodiment of the present invention.
A plan view of the chip, FIG. 2 is a sectional view taken along the line AA' of the LSI chip in FIG. 1, FIG. 3 is a plan view of the LSI chip for explaining a second embodiment of the present invention, and FIG. is a similar sectional view taken along the line B-B' in FIG. 3, and FIG. 5 is a plan view of an LSI chip for explaining an example of the prior art. 1... LSI chip, 2... Ponding pad,
3...Electrical inspection pad, 4.7...Wiring, 5...
・Silicon substrate, 6...protective resin. 8゛#I Concave 2 Concave 3 Figure 4
Claims (1)
体集積回路装置において、内側に形成する電気検査用パ
ッドと、前記電気検査用パッドに対応してその外側に設
けた外部リード接続用パッドと、前記電気検査用パッド
および前記外部リード接続用パッドをそれぞれ接続する
電気的接続手段とを含むことを特徴とする半導体集積回
路装置。In a semiconductor integrated circuit device in which a plurality of pads are provided on each of four sides on the surface, an electrical testing pad formed on the inside, and an external lead connection pad provided on the outside corresponding to the electrical testing pad. , and electrical connection means for respectively connecting the electrical testing pad and the external lead connection pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62080201A JPS63244853A (en) | 1987-03-31 | 1987-03-31 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62080201A JPS63244853A (en) | 1987-03-31 | 1987-03-31 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63244853A true JPS63244853A (en) | 1988-10-12 |
Family
ID=13711773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62080201A Pending JPS63244853A (en) | 1987-03-31 | 1987-03-31 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63244853A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5962926A (en) * | 1997-09-30 | 1999-10-05 | Motorola, Inc. | Semiconductor device having multiple overlapping rows of bond pads with conductive interconnects and method of pad placement |
| US5965948A (en) * | 1995-02-28 | 1999-10-12 | Nec Corporation | Semiconductor device having doubled pads |
| EP1150355A1 (en) * | 1998-11-20 | 2001-10-31 | Sony Computer Entertainment Inc. | Integrated circuit chip, integrated circuit, printed-circuit board and electronic device |
| JP2011249366A (en) * | 2010-05-21 | 2011-12-08 | Panasonic Corp | Semiconductor device and manufacturing method thereof |
| CN103229286A (en) * | 2010-11-29 | 2013-07-31 | 丰田自动车株式会社 | Semiconductor device |
-
1987
- 1987-03-31 JP JP62080201A patent/JPS63244853A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5965948A (en) * | 1995-02-28 | 1999-10-12 | Nec Corporation | Semiconductor device having doubled pads |
| US5962926A (en) * | 1997-09-30 | 1999-10-05 | Motorola, Inc. | Semiconductor device having multiple overlapping rows of bond pads with conductive interconnects and method of pad placement |
| EP1150355A1 (en) * | 1998-11-20 | 2001-10-31 | Sony Computer Entertainment Inc. | Integrated circuit chip, integrated circuit, printed-circuit board and electronic device |
| EP1150355A4 (en) * | 1998-11-20 | 2003-09-10 | Sony Computer Entertainment Inc | Integrated circuit chip, integrated circuit, printed-circuit board and electronic device |
| JP2011249366A (en) * | 2010-05-21 | 2011-12-08 | Panasonic Corp | Semiconductor device and manufacturing method thereof |
| US8927987B2 (en) | 2010-05-21 | 2015-01-06 | Panasonic Corporation | Semiconductor device including external connection pads and test pads |
| CN103229286A (en) * | 2010-11-29 | 2013-07-31 | 丰田自动车株式会社 | Semiconductor device |
| EP2648212A1 (en) * | 2010-11-29 | 2013-10-09 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
| EP2648212A4 (en) * | 2010-11-29 | 2014-05-07 | Toyota Motor Co Ltd | Semiconductor device |
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