JPH01137640A - Semiconductor storage circuit device - Google Patents

Semiconductor storage circuit device

Info

Publication number
JPH01137640A
JPH01137640A JP62297019A JP29701987A JPH01137640A JP H01137640 A JPH01137640 A JP H01137640A JP 62297019 A JP62297019 A JP 62297019A JP 29701987 A JP29701987 A JP 29701987A JP H01137640 A JPH01137640 A JP H01137640A
Authority
JP
Japan
Prior art keywords
pad
bonding
chip
check
aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62297019A
Other languages
Japanese (ja)
Inventor
Shigemitsu Nakamura
中村　重光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62297019A priority Critical patent/JPH01137640A/en
Publication of JPH01137640A publication Critical patent/JPH01137640A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]

Abstract

PURPOSE:To eliminate an improper bonding in a chip by forming the shape of an aluminum bonding pad on the chip in the same direction so that a P/W check and a wire bonding are conducted at separate positions on the same pad. CONSTITUTION:A chip 1 is composed to have a contact face on an aluminum bonding pad 2 disposed on the chip 1 to be used for a P/W check and the wire bonding peculiarly at the upper side or right side in the same direction by altering the shape of the pad 2. Then, the wire bonding on the pad 2b is performed irrespective of the wear of the aluminum on the pad 2a in the P/W check. Thus, an improper bonding in the chip is eliminated.

Description

【発明の詳細な説明】 〔産業上の利用分計〕 本発明は半導体記憶回路装置に関し、特にアルミボンデ
ィングパッドを有する半導体記憶回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a semiconductor memory circuit device, and more particularly to a semiconductor memory circuit device having aluminum bonding pads.

〔従来の技術〕[Conventional technology]

従来、半導体記憶回路装置（以下、チップと称す）上に
あるアルミボンディングパッドのＰ／Ｗ（バス／゛ウェ
ーハ）チェックとワイヤーボンディングは同一パッド上
の同一位置で行っていた。Conventionally, P/W (bus/wafer) checking and wire bonding of aluminum bonding pads on a semiconductor memory circuit device (hereinafter referred to as a chip) have been performed at the same position on the same pad.

第３図はかかる従来の一例を説明するためのチップの平
面図である。FIG. 3 is a plan view of a chip for explaining an example of such a conventional device.

第３図に示すように、かかるチップ１はその周辺部にポ
ンディングパッド２を形成しており、このパッド２を用
いてＰ／Ｗチェックとアルミボンディングを行っている
。As shown in FIG. 3, this chip 1 has a bonding pad 2 formed around its periphery, and this pad 2 is used to perform P/W check and aluminum bonding.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のチップはアルミボンディングのＰ／Ｗチ
ェックとワイヤーボンディングとを同一の位置（個所）
で行っていたので、Ｐ／Ｗチェックでパ・ｙド上のアル
ミが磨耗し、ワイヤーボンディングができなくなるとい
う欠点があった。The conventional chip mentioned above performs the P/W check of aluminum bonding and wire bonding at the same location (location).
This had the disadvantage that the aluminum on the pad was worn out during the P/W check, making wire bonding impossible.

本発明の目的は、パッドのＰ／Ｗチェックとワイヤーボ
ンディングとで同一位置く又は同−接触面）を使わない
ようにしてＰ／Ｗチェックにおけるパッド上のアルミの
磨耗の影響を排除する半導体記憶回路装置を提供するこ
とにある。It is an object of the present invention to provide a semiconductor memory device that eliminates the influence of abrasion of aluminum on a pad in P/W checking by avoiding using the same position or the same contact surface for P/W checking and wire bonding. The purpose of the present invention is to provide a circuit device.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体記憶回路装置は、チ゛ツブ上に配置され
たアルミボンディングパッドの形状゛をＰ／Ｗチェック
およびワイヤーボンディングに使用するパッド上の接触
面を独自に持たせ且つ同一方向に形成して構成される。The semiconductor memory circuit device of the present invention is configured such that the shape of the aluminum bonding pads arranged on the chip has a unique contact surface on the pad used for P/W check and wire bonding and is formed in the same direction. be done.

〔実施例〕〔Example〕

次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.

第１図（ａ）、（ｂ）はそれぞれ本発明の第一の実施例
を説明するためのチップの平面図およびホンディングパ
ッドの拡大図である。FIGS. 1(a) and 1(b) are a plan view of a chip and an enlarged view of a bonding pad, respectively, for explaining a first embodiment of the present invention.

第１図（ａ）に示すように、かかるチップ１はその上に
配置されたアルミボンディングパッド２の形状を変えて
Ｐ／Ｗチェックとワイヤーボンディングに使用するパッ
ド上の接触面を上辺あるいは右辺で独自に同一方向に持
たせる様にしたものである。As shown in FIG. 1(a), such a chip 1 is designed by changing the shape of the aluminum bonding pad 2 placed on it so that the contact surface on the pad used for P/W check and wire bonding is on the top or right side. It is designed to be uniquely held in the same direction.

また、第１図（ｂ）に示すように、拡大したポンディン
グパッドは従来例と比較してチップ上にあるアルミボン
ディングパッドがＰ／Ｗチェックとワイヤーボンディン
グとにおいてパッド２上の同一位置く又は同一接触面）
を使わない点が異なる。すなわち、Ｐ／Ｗチェックにお
けるパッド２ａ上でのアルミの磨耗に関係なく、パッド
２ｂ上へのワイヤーボンディングが可能になる。In addition, as shown in FIG. 1(b), compared to the conventional example, the enlarged bonding pad has the aluminum bonding pad on the chip at the same position on pad 2 during P/W check and wire bonding. (same contact surface)
The difference is that it does not use . That is, wire bonding onto pad 2b is possible regardless of the wear of aluminum on pad 2a during P/W check.

第２図は本発明の第二の実施例を説明するためのチップ
の平面図である。FIG. 2 is a plan view of a chip for explaining a second embodiment of the present invention.

第２図に示すように、アルミボンディングパッドをＰ／
Ｗチェック用のポンディングパッド４とワイヤーボンデ
ィング用のパッド３を独、自に同一方向に設けた例であ
る。そのため、Ｐ／Ｗチェックにおいて、パッド４上で
のアルミが磨耗してもワイヤーポンデイグ用のパッド３
に影響が無いので、ワイヤーボンディングを容易に実現
し、且つ接続不良などの解消に役立つという利点がある
。As shown in Figure 2, connect the aluminum bonding pad to P/
This is an example in which the bonding pad 4 for W check and the pad 3 for wire bonding are independently provided in the same direction. Therefore, in the P/W check, even if the aluminum on pad 4 is worn out, the pad 3 for wire ponding
Since this method has no effect on wire bonding, it has the advantage of easily realizing wire bonding and helping to eliminate connection failures.

〔発明の効果〕〔Effect of the invention〕

以上説明じなように、本発明の半導体記憶回路装置はチ
ップ上に配置されたアルミボンディングパッドの形状を
変えることでＰ／Ｗチェックとワイヤーボンディングに
使用するパッド上の接触面を別に設けることができ、そ
のため、Ｐ／Ｗチェックにおけるパッド上でのアルミの
磨耗に関係なくパッド上への→イヤーボンディングがで
き、チップにおけるボンディング不良が無くなるという
効果がある。また、Ｐ／Ｗチェックとワイヤーボンディ
ング用に独自のパッドを設けたチップでも上記と同様の
効果が得られる。As explained above, in the semiconductor memory circuit device of the present invention, by changing the shape of the aluminum bonding pads arranged on the chip, it is possible to separately provide a contact surface on the pads used for P/W check and wire bonding. Therefore, → ear bonding can be performed on the pad regardless of the wear of aluminum on the pad during P/W check, and bonding defects on the chip can be eliminated. Further, the same effect as described above can be obtained even with a chip provided with unique pads for P/W check and wire bonding.

更に、両パッドを同一方向に設けることにより、製造上
も容易に半導体記憶回路装置が得られるという効果があ
る。Further, by providing both pads in the same direction, there is an effect that a semiconductor memory circuit device can be easily manufactured.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）、（ｂ）はそれぞれ本発明の第一の実施例
を説明するためのチップの平面図とポンディングパッド
拡大図、第２図は本発明の第二の実施例を説明するため
のチップの平面図、第３図は従来の一例を説明するため
のチップの平面図である。 １・・・チップ、２，２ｂ、３・・・アルミボンディン
グパッド、２ａ、４・・・チェック用パッド。FIGS. 1(a) and (b) are a plan view of a chip and an enlarged view of a bonding pad for explaining a first embodiment of the present invention, respectively, and FIG. 2 is a diagram for explaining a second embodiment of the present invention. FIG. 3 is a plan view of a chip for explaining a conventional example. 1... Chip, 2, 2b, 3... Aluminum bonding pad, 2a, 4... Check pad.

Claims (1)

【特許請求の範囲】[Claims] 　ケースに半導体素子を搭載した半導体記憶回路装置に
おいて、チップ上のアルミボンディングパッドの形状を
Ｐ／Ｗチェックおよびワイヤーボンディングが同一パッ
ド上の別位置で行えるように同一方向に形成したことを
特徴とする半導体記憶回路装置。A semiconductor memory circuit device in which a semiconductor element is mounted in a case, characterized in that aluminum bonding pads on the chip are formed in the same direction so that P/W check and wire bonding can be performed at different positions on the same pad. Semiconductor memory circuit device.
JP62297019A 1987-11-24 1987-11-24 Semiconductor storage circuit device Pending JPH01137640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62297019A JPH01137640A (en) 1987-11-24 1987-11-24 Semiconductor storage circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62297019A JPH01137640A (en) 1987-11-24 1987-11-24 Semiconductor storage circuit device

Publications (1)

Publication Number Publication Date
JPH01137640A true JPH01137640A (en) 1989-05-30

Family

ID=17841189

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62297019A Pending JPH01137640A (en) 1987-11-24 1987-11-24 Semiconductor storage circuit device

Country Status (1)

Country Link
JP (1) JPH01137640A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5962926A (en) * 1997-09-30 1999-10-05 Motorola, Inc. Semiconductor device having multiple overlapping rows of bond pads with conductive interconnects and method of pad placement

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5962926A (en) * 1997-09-30 1999-10-05 Motorola, Inc. Semiconductor device having multiple overlapping rows of bond pads with conductive interconnects and method of pad placement

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