JPS60198835A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS60198835A
JPS60198835A JP59055601A JP5560184A JPS60198835A JP S60198835 A JPS60198835 A JP S60198835A JP 59055601 A JP59055601 A JP 59055601A JP 5560184 A JP5560184 A JP 5560184A JP S60198835 A JPS60198835 A JP S60198835A
Authority
JP
Japan
Prior art keywords
pads
case
bonding
semiconductor chip
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59055601A
Other languages
Japanese (ja)
Inventor
Hitonori Hayano
早野　仁紀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59055601A priority Critical patent/JPS60198835A/en
Publication of JPS60198835A publication Critical patent/JPS60198835A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Abstract

PURPOSE:To facilitate bonding of a semiconductor chip to the cases of various kinds by a method wherein bonding pads of the plural number of pieces connected electrically mutually are provided on the semiconductor chip, and only a part of the pads thereof is connected electrically to the case according to lead wires. CONSTITUTION:Bonding pads 9, 9', 10' of the plural number are formed on a semiconductor chip 6, while the pads 9, 9' out of the pads thereof are connected using respectively lead wires 8, 8' to wirings 7, 7' provided respectively to the outside peripheral part of the case. However the pad 10 is left idle without connecting to anywhere. The chips 6 are formed in the same shape like this, accommodated in a ceramic or plastic case, and only the necessary pads are connected to the wirings to simplify formation of an IC, etc.

Description

【発明の詳細な説明】 本発明は、半梼体記＋！ｌ装置、特にポンディングパッ
ドの配泗、に関するものである３゜ケー来、半導体５じ
俯装値のケースには、枠々のものか用いられているが、
その中のいくつカ・は、半いう点から、半導体チップ上
のパッドの１飯に互いに相反する制約を課している。こ
の点について以下でセラミックケースとプラスチックケ
ースの場合を例・にして訃Ｉ明する。DETAILED DESCRIPTION OF THE INVENTION The present invention is based on the semi-transparent +! Since 3°C, which is related to the arrangement of l devices, especially the placement of bonding pads, frames have been used in cases of semiconductors with a depreciation value of 5°.
Some of them impose contradictory constraints on each pad on a semiconductor chip. This point will be explained below using examples of ceramic cases and plastic cases.

第１図（ａ）は、セラミックケースにポンチインクされ
た半導体チップを、第１図の）は、同一チップをプラス
チックケースにボンディングした場合を示す。いずれの
図もチップの１つのコーナー剖・分のボンディング状態
のみを示した。、なお、セラミックケースはこの後ふた
をする仁とで、又、プラスチックケースは樹脂を流し込
んで整形することでケースとしての形ができあがる。ま
た、いずれの図中も、２は半導体チップ、３．３’はケ
ース内の導体部分もしくはリードフレームのリードの部
分すなわちケースの配線部分４，４′はリード線、５．
５′はチップ上のポンディングパッドを示し、３と５，
３′と５′がそれぞれリード線４，４′によって、電気
的に接糾されている。FIG. 1(a) shows a semiconductor chip punched into a ceramic case, and FIG. 1(a) shows the same chip bonded to a plastic case. Each figure shows only the bonding state of one corner of the chip. , Incidentally, the shape of the ceramic case is completed by putting the lid on after this, and the shape of the plastic case is completed by pouring resin and shaping it. In each figure, 2 is a semiconductor chip, 3.3' is a conductor part in the case or a lead part of a lead frame, that is, the wiring part 4, 4' of the case is a lead wire, and 5.
5' indicates the bonding pad on the chip, 3 and 5,
3' and 5' are electrically connected by lead wires 4 and 4', respectively.

ここで、セラミックケースとンラスナックケーの導体部
分（各図中の３．３’）の位置が異なり、チップのコー
ナー付近に記動されたパッドに関しては、パッドの位動
によってはリード線どおしのショートが起こる。Here, the positions of the conductor parts (3.3' in each figure) of the ceramic case and the plastic case are different, and with respect to the pads marked near the corners of the chip, the lead wires may differ depending on the position of the pads. A short circuit occurs.

第１図（ｂ）ではポンティングワイヤのリード線４′と
ボンティングパッド５又はリード線４がショートしやす
くなっている。In FIG. 1(b), the lead wire 4' of the ponting wire and the bonding pad 5 or the lead wire 4 tend to short-circuit.

このことを防ぐためには、第２図のようにパッド５′を
コーナ一部分に配置すれはよい。なお、第２図中の番号
は、＆’Ｓ　１　ｆｙ１中の番号と対応している。In order to prevent this, it is advisable to arrange a pad 5' at a part of the corner as shown in FIG. Note that the numbers in FIG. 2 correspond to the numbers in &'S 1 fy1.

しかるに第２図のようなパッド配置にした場合には、プ
ラスチックケースではボンディングできても、センミン
クケースでは、リード線がショートするため、ポンディ
グできないことは明らかである。However, when the pads are arranged as shown in FIG. 2, it is clear that bonding is possible with a plastic case, but bonding is not possible with a Senmink case because the lead wires will be short-circuited.

以上のことから明らかなように、プラスチックケースで
のボンティングのしやすさという点からは、パッド５′
はチップのコーナー付近に配置されることがｌ要である
か、他方、セラミックケースでのボンディングのしやす
さという点からは、パッド５′はチップのコーナーから
ｗＦｔまた場所に配置されることが必要であるという。As is clear from the above, from the viewpoint of ease of bonding with a plastic case, pad 5'
On the other hand, from the point of view of ease of bonding in a ceramic case, pad 5' should be placed near the corner of the chip. It is said that it is necessary.

バッド１俤に関して、互いに相反する制約が課せられる
ことに力る。I am impressed by the fact that there are contradictory constraints imposed on Bad 1 yen.

特に上記の問題は、近年、半導体記憶装置の大容量化に
伴い、チップの大きさか大きくなり、ケースとの間に余
裕がなくなってくると顕著になる。In particular, the above-mentioned problem becomes noticeable as the capacity of semiconductor memory devices increases in recent years, and as the size of the chip increases, there is no margin between the chip and the case.

このため、従来のパッドの記動法ではそれぞれのケース
に適したパッド配置をもつチップを別々に作るか、パッ
ド配置を工夫して、いずれのケースでもボンディングで
きるようにするか、しなければならない。しかるに徒者
の場合には組立歩留が低下することもありうるし、又、
前者のを合でも、ケース別にチップを作るにはむだな工
数を必扱とする。For this reason, with conventional pad marking methods, it is necessary to create separate chips with pad placement suitable for each case, or to devise pad placement so that bonding can be performed in either case. . However, if it is done by an unscrupulous person, the assembly yield may decrease, and
Even with the former option, making chips for each case requires wasted man-hours.

本発明の目的は、同一チップで種々のケースに容易にボ
ンディングできるパッドをもった半導体記憶装置を提供
するものである。An object of the present invention is to provide a semiconductor memory device having pads that can be easily bonded to various cases using the same chip.

す力わち、本発明によれば、互いに電気的に接続された
桧数個のポンディングパッドを半導体チップ上に配置し
、その内の一部のパッドのみにボンディングすることに
より、上記欠点を除去することができる６、 以下に図面を用いて不発１の実施例について１明する。According to the present invention, several bonding pads that are electrically connected to each other are arranged on a semiconductor chip, and bonding is performed to only some of the pads, thereby solving the above drawbacks. 6. An example of misfire 1 will be explained below using the drawings.

ｍ３図（ａ）、Φ）に於いて（ａ）はセラミックケース
、（ｂ）はプラスチックケースに於ける実施例を示し６
はチップ、７．７’はケース内の導体部分もしくはリー
ドフレームのリードの部分す々わちケースの配線部分８
，８″はリード線、９．９’、１０’はンボンティング
パッドであり、ボンディングバット９′と１０′は電気
的に接続されており、どちらのポンディングパッドにリ
ード線７′がボンディングされても、との半導体記憶装
置は正常に動作するようになっている１、そして、セラ
ミックケースでは１０’の方をボンディングして９′は
ボンディングせず、プラスチックケースでＦｉ９’の方
をボンディングして、１０′はボンティングしないよう
にすれば、リード線のショートなどをおこすことなく、
いずれ第４図には、上記実施例のコーナ一部を拡大した
図を示した。ここで９．９’、１０’はそれぞれ第３図
中の同じ番号のボンティングパッドに対応し、１１は半
導体チップ、１２はアルミ力どの配線材料で第４図中同
じ番号のものは同じ配線材料で形成されていることを示
している。又、ポンディングパッド９′と１０′は上記
配線材料１２によって電気的に接続されている。In Figures m3 (a) and Φ), (a) shows an example in a ceramic case, and (b) shows an example in a plastic case6.
is the chip, 7.7' is the conductor part in the case or the lead part of the lead frame, i.e. the wiring part 8 of the case.
, 8'' are lead wires, 9.9' and 10' are bonding pads, bonding pads 9' and 10' are electrically connected, and to which bonding pad the lead wire 7' is bonded. 1, and in the ceramic case, 10' is bonded, but 9' is not bonded, and in the plastic case, Fi 9' is bonded. If you do not bond 10', there will be no short circuit of the lead wire.
FIG. 4 shows an enlarged view of a part of the corner of the above embodiment. Here, 9.9' and 10' correspond to the bonding pads with the same numbers in Figure 3, 11 is the semiconductor chip, 12 is the wiring material such as aluminum, etc., and the same numbers in Figure 4 are the same wires. Indicates that it is made of material. Further, the bonding pads 9' and 10' are electrically connected by the wiring material 12.

なお、一般に、ポンディングパッドには静電耐圧対策用
の回路素子が一組、接続されているが、これは、ポンデ
ィングパッド９’、１０’に共通のものを一組接続して
もよいし、あるいは、９’、１０’別々に一組ずつ接続
してもよく、その接続法に関しては、本発明の請求か囲
は伺ら制限を加えるものではない。Generally, a set of circuit elements for electrostatic withstand voltage countermeasures is connected to the bonding pad, but a set of circuit elements common to the bonding pads 9' and 10' may also be connected. Alternatively, 9' and 10' may be connected as a pair separately, and the claims of the present invention do not impose any limitations on the connection method.

また、以上の説明ではセラミックケースとプラスチック
ケースの場合を例として用いたが、本発明は、他のケー
スでも同様の効果かえられる。Further, although the above explanation uses a ceramic case and a plastic case as examples, the present invention can have similar effects in other cases as well.

このように、本発明は、半導体チップ上に互いドを有し
、前記複数個のポンディングパッドの一部のみがリード
線によってケースに外気的に接続され、残りのポンディ
ングパッドは接続されていないことを特命とした半導体
記怪装置で、種々のケースへのボンティングを容易に実
現することができる。As described above, the present invention has mutual pads on a semiconductor chip, and only some of the plurality of bonding pads are connected to the case via lead wires, and the remaining bonding pads are not connected. This is a semiconductor recording device that is specially designed to be completely free, and can easily be bonded to various cases.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）　、　（ｂ）及び第２図は従来のパッド配
置でケースにボンディングした状態を示した平面図。 第３　［１Ｑｌ（ａ）　、Φ）は本発明の東飾物を示す
平面図。第４図は本発明が実施ネれているチップ上の一
部を拡大した平面図でを・る。 同、図において、２，６．１１−・・・・・半導体チッ
プ、３　、３ニア　、　７’・・・・・・ケース内の配
紳角分、４，４’、８゜８′・・・・・・リードｉｌ！
、５．５’　、９．９’　、１０・・・・・・ポンディ
ングパッド、１２・・・・・・配線徊料。 身与　／　江Ｑ　Ｃａノ イず’ｔ　／　ｒｎ　（ｂ） 第２区FIGS. 1(a), 2(b) and 2 are plan views showing a state in which the conventional pad arrangement is bonded to the case. 3rd [1Ql(a), Φ) is a plan view showing the east decoration of the present invention. FIG. 4 is an enlarged plan view of a part of the chip on which the present invention is implemented. In the same figure, 2, 6.11-...semiconductor chip, 3, 3 near, 7'... arrangement angle in the case, 4, 4', 8°8'. ...Lead il!
, 5.5', 9.9', 10...ponding pad, 12...wiring material. Kimyo / Jiang Q Ca Noiz't / rn (b) 2nd Ward

Claims (1)

【特許請求の範囲】[Claims] 半導体チップ上に互いに電気的に接続された枠数側のボ
ンデングパッドを有し、前記複数個のポンディングパッ
ドの一部のみがリード線によってケースの配線部分に電
り的に接続された前記ポンディングパッド以外のボンテ
ィングパッドは、ケース西［・線部分に接続されていな
いことを特徴とする半導体ｎ１悌装餉。The semiconductor chip has a plurality of bonding pads electrically connected to each other, and only some of the plurality of bonding pads are electrically connected to the wiring part of the case by lead wires. The bonding pads other than the bonding pads are not connected to the case west line.
JP59055601A 1984-03-23 1984-03-23 Semiconductor memory device Pending JPS60198835A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59055601A JPS60198835A (en) 1984-03-23 1984-03-23 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59055601A JPS60198835A (en) 1984-03-23 1984-03-23 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS60198835A true JPS60198835A (en) 1985-10-08

Family

ID=13003294

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59055601A Pending JPS60198835A (en) 1984-03-23 1984-03-23 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS60198835A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01107548A (en) * 1987-10-20 1989-04-25 Hitachi Ltd Semiconductor device
US4974053A (en) * 1988-10-06 1990-11-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device for multiple packaging configurations

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01107548A (en) * 1987-10-20 1989-04-25 Hitachi Ltd Semiconductor device
US4974053A (en) * 1988-10-06 1990-11-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device for multiple packaging configurations

Similar Documents

Publication Publication Date Title
US6927478B2 (en) Reduced size semiconductor package with stacked dies
US6476474B1 (en) Dual-die package structure and method for fabricating the same
JP2537014B2 (en) Lead frame package for electronic devices
JP4847525B2 (en) Integrated circuit implementation
JPH04307943A (en) Semiconductor device
US7719845B1 (en) Chamfered memory card module and method of making same
JPS60198835A (en) Semiconductor memory device
JP3316409B2 (en) Structure of a semiconductor device having a plurality of IC chips
JP2005167286A (en) Semiconductor device and manufacturing method thereof
US20090021921A1 (en) Memory card and its manufacturing method
JP2522455B2 (en) Semiconductor integrated circuit device
JP2788196B2 (en) IC board for IC card
JPH0661297A (en) Semiconductor device
JPH0621329A (en) Resin sealed semiconductor device
JPS60101938A (en) Semiconductor device
TW516193B (en) Multi-chip package structure and the manufacturing method thereof
JPH05299575A (en) Semiconductor device with built-in memory
JPS61274349A (en) Plastic sealed type semiconductor device
JPS6081852A (en) Semiconductor device
JPS6039254U (en) Semiconductor integrated circuit device
JPS58133837U (en) semiconductor equipment
JPH05102442A (en) Semiconductor integrated circuit
JPS6059541U (en) Lead frame for integrated circuits
JPH01114049A (en) Integrated circuit chip of variable size
JPH0637234A (en) Semiconductor device