516193 A7 五、發明說明（j ) (一） 發明技術領域： 本發明係有關於一種多晶片封裝結構及其製法，尤指 二種可將兩個以上相同或不同功能之晶片堆疊於同一包裝 中，且兩兩晶片間沒有懸空區域之多晶片封裝結構及其製 法。 (二） 習用技術的說明： 在現今半導體製造的趨勢中，如何能在愈小的半導體 包裴中擠入愈多的邏輯電路而成本卻能柑對降低，乃是全 球^體業者所—致全力研究的課題’解於此領域中的 研九Λ兄爭也因此非常激烈。除了以不斷研發縮小晶片上 之電路設計的最小元件尺寸方式之外，另一種可以最低成 本直接達到單一半導體包裝之記憶容量倍增的方式，便是 在同—包裝中擠入兩片以上的晶片。 曰最常見的多晶片封裝構造為並排式⑷de-by-side)多 ^片封裝構造’其係將兩個以上之晶片彼此並排地安褒於 rt基板之主要安裝面。晶片與共同基板上導電線路間 -般係藉由線銲法(wire b〇nding)達成。然而該並 2夕晶片龍構造之缺點為職效率太低，因為該共同 土板之面積會隨著晶片數目的增加而增加。 2圖-A所示，美目專鄉532細 stacked dev.ce) ¥體晶f 110設於一基板120並且電性連接至基板12〇， 以及-第二半導體晶片13Q堆疊於該第—半導體晶片⑽ 本紙張尺度刺516193 A7 V. Description of the invention (j) (1) Technical field of the invention: The present invention relates to a multi-chip package structure and a manufacturing method thereof, especially two kinds of chips that can stack two or more chips with the same or different functions in the same package. The multi-chip packaging structure and the manufacturing method there are no floating areas between the two chips. (2) Explanation of conventional technology: In the current semiconductor manufacturing trend, how to squeeze more logic circuits into smaller semiconductor packages and reduce the cost can be achieved by global players. The full-fledged research topic 'Resolving the research in this field' is also very fierce. In addition to continuous research and development to reduce the minimum component size of the circuit design on the wafer, another method that can directly reach the memory capacity of a single semiconductor package at the lowest cost is to squeeze more than two wafers into the same package. The most common multi-chip package structure is a side-by-side multi-chip package structure, which is to mount two or more chips side by side on the main mounting surface of the RT substrate. Between the chip and the conductive lines on the common substrate-this is generally achieved by wire bonding. However, the shortcomings of the wafer chip dragon structure are too low, because the area of the common soil plate will increase as the number of wafers increases. As shown in Figure 2-A, Meme Village 532 is finely stacked dev.ce) ¥ bulk crystal f 110 is provided on a substrate 120 and is electrically connected to the substrate 120, and a second semiconductor wafer 13Q is stacked on the first semiconductor Wafer
--------訂---------- (請先閱讀背面之注音？事項再填寫本頁) 516193 A7 五、發明說明（) 上亚且電性連接至基板12〇,其特徵在於利用一設於兩晶 片間的膠層140來提供銲線線弧（the loops of the bonding wires)所需之空隙（ciearance)。並且該膠層HQ =厚，必須大於銲線之弧高u〇〇p hdght)，係指第一半 2體晶片110正面與銲線150線弧頂點間的距離，以避免 第一半導體晶片130接觸到銲線15〇之線弧。 •習知在晶片銲塾與基板銲塾間形成銲線連接 interconnect ion)之打線技術一般係包含（a)球接合 bond)於晶片銲墊，（b)形成線弧於日日日片銲塾與基板鲜塾間 以及⑷壓印接合（stitch b_至基板銲墊而完成該鮮線 連接。般其孤南約為10至15密爾（mil)。雖然藉著調 整線弧參數，外形以及型式，習用打線技術可以將孤高將 低至大約6密爾（nul)。然而這已是可得到的最小弧高， 因為若更低將使線受損並且使其拉力變差。 因此，使用習知打線技術時，該膠層14〇之厚度必須 大於8密爾以完全防止第二半導體晶片13〇接觸到鲜線 150之線弧。該膠層14〇之材料一般為環氧膠(印㈣或膠 帶（tape)。然而要形成厚度達δ密爾之環氧膠層是非常困 難的。此外，當使用厚度達8密爾之膠帶，其一方面將大 幅增加製造成本；另一方面，該膠層14〇與矽晶片間的熱 膨脹係數不一致(GTE mismatch)也將嚴重損壞所製得封穿' 構造之可靠性。 ~ 因此，如圖一B所示，美國專利第6〇〇5778號揭示另— 多晶片堆疊裝置(multichip stacked device)，其包含一 ___3 卜紙張尺度適用中國國家S準（CNS)A4規格（210 X 297公爱 (請先閱讀背面之注意事項再填寫本頁) ---------訂-------.—- 經濟部智慧財產局員工消費合作社印製 516193 A7 B7 五、發明說明（2 ) 第一半導體晶片110設於一基板12〇並且電性連接至基板 120 ’以及-第二半導體晶片13Q堆疊於該第—半導體晶片 110上並且電性連接至基板12Q。該錢專利第_則號 之付敗利用一没於兩晶片間的間隔物⑹來 提供銲線 150線弧（the l〇Qp of the b〇ndlng wires)所需 之空隙（clearance)。此外，以金屬導電材料製成之間隔 物（spaCer)160亦可作為半導體晶片之接地面，及提供電 容之安裝。雖然，美國專利第6005778號之間隔物 (spacer)160已解決美國專利第5323〇6〇號前述膠層丨4〇之 缺失，但由於間隔物必需小於實際的晶片尺寸，如此一來 在豐上層晶片時，則與間隔物會有懸空區域產生，此一結 構會造成在打上層晶片的金線時，產生製程上的困難性， 且易於打金線發生位移，影響其精準度，而降低製程的良 率，進而影響競爭力。 (三）發明概述： ，本發明之主要目的在於提供—種多晶片封裝結構及其 製法’使得打金線的方式更容易控制。 本發明之3 -目的在於提供—種乡^封裝結構及其 製法，使得打金線時更為精準。 八 本發明之再-目的在於提供_種多晶#封裝結構及其 製法，以有效提高製程之良率。 本發明為達成上述目的，故提出-種多晶片封裝結 構’其係包括有：—基板、複數個晶片，其係位於該基板 ----- I ^ TT-------------^---------- (請先閱讀背面之注咅？事項再填寫本頁) 五 、發明說明（ 上方 若干個用打金線的方式與該基板導通電性' j丄以及若干個間隔物，其係包覆於各該厂成為一月 以支擇各該 較佳者 晶片 :黏著層内，用 ’多晶片封裝結構之製法，係包括有下列步 經濟部智慧財產局員工消費合作社印製 (a)將一第一晶片接合於一基板上· 第一晶片以打金線之方式:與該_ (C)將一間隔物以一第一黏著層接合於該第一晶片上，且 該間隔物較該第一晶片尺寸小； W再覆蓋-第二黏著層以接合m其中該第一 黏=層與該第二黏著層形成將該間隔物包覆於内之一 黏著層，且該第-晶片、該黏著層及該第二晶片形成 三明治狀； (e)將该第二晶片以打金線之方式，與該基板導通電性。 車父佳者，更可重覆步驟酿步驟⑹，以完成更多晶片 之封裝。 為使貴審查委員對於本發明之目的、特徵及功效， 月b有更進一步之認識與瞭解，茲配合圖式詳細說明如後。 (四）圖式之簡要說明： 圖一A為習用技術之多晶片半導體封裝結構之一例 圖0 5 本紙張尺度過用f國國家標準（CNS)A4規格（210 516193 A7 、發明說明（f 圖 圖一B 用技術之多晶片半導體封裝結 構之另/例 圖二 示意圖 為本發明之多晶#封裝結構之第—較佳實施例 示實施例之多W封裝結構之 版法的幸乂 版私步驟流程實施例示意圖。 四為本發明之多晶片封裝結構之第二較佳實施例 圖 示意圖。 佳實發明之第-較佳實施例與外界柄合之-較 較佳=意本:明之第—較佳實施例與外·之另- 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 圖號說明： 110〜第一半導體晶片 130〜苐^一半導體晶片 120〜基板 140〜膠層 150〜銲線 160〜間隔物 2、3〜多晶片封裝結構（兩較佳實施例） 21、 31〜第一晶片 、 22、 32〜第二晶片 210、220〜作動面 —1 —^-------------訂--------—線 (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標‘（CNS)A4規格（210；^ 公釐） 516193 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 A7 B7 五、發明說明（& ) 211、 221〜非作動面 212、 222〜連接墊 213、 223〜金線 23、 33〜基板 24、 34〜晶片黏著層 25、 35a、35b、35c〜黏著層 250、 350a、350b、350c〜第一黏著層 251、 351a、351b、351c〜第二黏著^ 26、 36a、36b、36c〜間隔物 27、 39〜封裝樹脂 37〜第三晶片 38〜第四晶片 4〜錫球 5〜引腳 (五）發明之詳細說明·· 本發明係有關於-種多晶片封 兩個以上相同或不同功能之晶片堆叠:同一 =片夕，有懸㈣域之多晶片封裝結構及其製法。本發 片二:日片封裝結構’其係包括有：-基板、複數個晶 ，、糸位於雜板上方，且各該晶片可用打金線的方式 與該基板導通電性、若干個黏著層，其係位於該兩兩晶片 之間，使其成為三明治狀；以及若干個間隔物，其係包覆 於各該黏著層内，用以支撐各該晶片。 本紙張尺度適而國家標準 297公釐） -----1---V--------------訂---------- MT (請先閱讀背面之注意事項再填寫本頁) 516193 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 請參閱圖二所示，其係為本發明之多晶片封裝結構第 一較佳實施例示意圖。而圖三A〜：F則為圖二所示第一較 佳實施例之製程步驟流程的一較佳實施例。 於圖二所示之第一較佳實施例中，該多晶片封裝結構 2，包括有：複數個晶片、一基板23、若干個黏著層和若 干個間隔物。该複數個晶片，係位於基板上方23，於本實 施例中係包含有一第一晶片21及一第二晶片22，各個晶片 21、22均具有一作動面210、220 (Active Side)及一非 作動面211、221 ( Inactive Side)，該作動面21〇、220 即為晶片21、22之電路設計所在的一側表面，並且，於各 個晶片21、22的作動面上210、220的預定位置處均設有複 數個連接塾212、222以成為晶片21、22上之電路與外界連 結之介面，於本較佳實施例中該連接墊212、222即為業界 所俗稱的金屬墊或鋁墊（A1 Pad)。 第一晶片21之作動面210與第二晶片22之作動面220上 的複數個連接墊212、222係藉由打金線213、223的方式與 基板23導通電性，且第一晶片21之非作動面211係結合於 基板23上。於本較佳實施例中，該第一晶片21之非作動面 211係藉由晶片黏著層24貼合於基板23上，而晶片黏著層 24可採用熱溶性雙面膠帶（Dual-Sided Adhesive Tape)、銀膠、環氧樹脂（ΕΡΟΠ)等具黏著性之材料。 該若干個黏著層，其係位於該兩兩晶片之間，使其成 為三明治狀，於本實施例中黏著層25係包括有第一黏著層 250與第二黏著層251，其中第一黏著層250用以黏著間隔 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----i.---V-------------訂---------- (請先閱讀背面之注意事項再填寫本頁) 516193-------- Order ---------- (Please read the note on the back? Matters before filling out this page) 516193 A7 V. Description of the invention () Shangya and is electrically connected to the substrate 12 It is characterized in that an adhesive layer 140 provided between two wafers is used to provide gaps required for the loops of the bonding wires. And the adhesive layer HQ = thick, must be greater than the arc height of the bonding wire (u〇〇p hdght), refers to the distance between the front face of the first half 2-body wafer 110 and the apex of the bonding wire 150 line to avoid the first semiconductor wafer 130 Touch the wire arc of wire 15. • Known wire bonding technology to form a wire bond interconnect ion between the wafer bonding pad and the substrate bonding pad generally includes (a) ball bonding bond) on the wafer pad, and (b) forming a wire arc on the daily bonding pad. The fresh wire connection is completed with the substrate and the embossing (stitch b_ to the substrate pad). Generally, the isolated south is about 10 to 15 mils. Although by adjusting the arc parameters, the shape and Type, the conventional wiring technology can reduce the solitary height to about 6 mils. However, this is already the minimum arc height available, because if it is lower, the wire will be damaged and its pulling force will be worse. Therefore, using conventional When the wire bonding technology is known, the thickness of the adhesive layer 14 must be greater than 8 mils to completely prevent the second semiconductor wafer 130 from contacting the line arc of the fresh wire 150. The material of the adhesive layer 14 is generally epoxy glue (printed ink) Or tape. However, it is very difficult to form an epoxy adhesive layer with a thickness of δ mil. In addition, when using a tape with a thickness of 8 mil, it will greatly increase the manufacturing cost on the one hand; on the other hand, the The thermal expansion coefficient between the adhesive layer 14 and the silicon wafer is not consistent (GTE mismatch) will also severely damage the reliability of the manufactured seal-through structure. ~ Therefore, as shown in Figure 1B, US Patent No. 60005778 discloses another-a multichip stacked device, which includes ___3 The paper size is applicable to China National Standard S (CNS) A4 (210 X 297 public love (please read the precautions on the back before filling this page) --------- Order ----- --.--- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 516193 A7 B7 V. Description of the invention (2) The first semiconductor wafer 110 is provided on a substrate 120 and is electrically connected to the substrate 120 ′ and the second semiconductor wafer 13Q is stacked on the first semiconductor wafer 110 and is electrically connected to the substrate 12Q. The payment of the patent No. _ rule uses a spacer 没 between the two wafers to provide a bonding wire 150 line arc (the l0). Qp of the bondlng wires). In addition, a spacer 160 made of a metal conductive material can also be used as a ground plane for semiconductor wafers and provide capacitor mounting. Although, US patent Spacer 1605778 has been resolved in the United States The above-mentioned adhesive layer of Patent No. 5323〇60 is missing, but because the spacer must be smaller than the actual wafer size, so when the upper layer wafer is enriched, there will be a suspended area with the spacer. This structure will As a result, it is difficult to process the gold wire on the upper layer of the chip, and it is easy to shift the gold wire, which affects its accuracy, and reduces the yield of the process, thereby affecting competitiveness. (III) Summary of the invention: The main purpose of the invention is to provide a multi-chip package structure and its manufacturing method, which makes the way of punching gold wires easier to control. The third object of the present invention is to provide a hometown package structure and a manufacturing method thereof, so as to make the gold wire more accurate. 8. The purpose of the present invention is to provide a _kind polycrystalline # package structure and a manufacturing method thereof, so as to effectively improve the yield of the manufacturing process. In order to achieve the above object, the present invention proposes a multi-chip package structure including a substrate and a plurality of wafers, which are located on the substrate ----- I ^ TT --------- ---- ^ ---------- (Please read the note on the back? Matters before filling out this page) 5. Description of the invention (Several of the above methods use gold wire to conduct electricity with the substrate 'j 丄 and several spacers, which are wrapped in each factory to become one month to support each of the better wafers: inside the adhesive layer, using the' multi-chip packaging structure manufacturing method, including the following steps of the Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative (a) Bonding a first chip to a substrate · The first chip is punched with gold wire: and (C) a spacer is bonded to the first adhesive layer On the first wafer, and the spacer is smaller in size than the first wafer; W is then covered-a second adhesive layer to join m wherein the first adhesive layer and the second adhesive layer are formed to cover the spacer on An inner adhesive layer, and the first wafer, the adhesive layer and the second wafer form a sandwich shape; (e) the second wafer is punched with gold It is electrically conductive with the substrate. The car driver can repeat the steps and steps to complete the packaging of more chips. In order for your review committee to further the purpose, features and effects of the present invention, month b has further Recognition and understanding, the detailed description is given below in conjunction with the drawings. (4) Brief description of the drawings: Figure 1A is an example of a multi-chip semiconductor package structure of conventional technology. ) A4 specification (210 516193 A7, description of the invention (f Fig. 1B) Another / example of a multi-chip semiconductor packaging structure using technology Figure 2 is a schematic diagram of the polycrystalline # packaging structure of the present invention-the preferred embodiment of the embodiment Schematic illustration of the private steps of the multi-W package structure version method. The fourth is a schematic diagram of the second preferred embodiment of the multi-chip package structure of the present invention. The first and preferred embodiment of the good invention and the external handle Together-better = Italian version: the first of the Ming-the preferred embodiment and the other · the other-the printed number description of the employee consumer cooperatives of the Ministry of Economics and Intellectual Property Bureau: 110 ~ the first semiconductor wafer 130 ~ 苐 ^ 一Conductor wafer 120 ~ substrate 140 ~ adhesive layer 150 ~ bonding wire 160 ~ spacer 2, 3 ~ multi-chip package structure (two preferred embodiments) 21, 31 ~ first wafer, 22, 32 ~ second wafer 210, 220 ~ Operating surface—1 — ^ ------------- Order ---------- line (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard '(CNS) A4 specification (210; ^ mm) 516193 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. & Description of the invention 211, 221 ~ non-acting surface 212, 222 ~ connection pad 213 , 223 ~ gold wire 23, 33 ~ substrate 24, 34 ~ wafer adhesive layer 25, 35a, 35b, 35c ~ adhesive layer 250, 350a, 350b, 350c ~ first adhesive layer 251, 351a, 351b, 351c ~ second adhesive ^ 26, 36a, 36b, 36c ~ spacers 27, 39 ~ encapsulation resin 37 ~ third wafer 38 ~ fourth wafer 4 ~ solder ball 5 ~ pin (five) Detailed description of the invention ·· This invention relates to- A multi-chip package of two or more chips with the same or different functions: the same = chip evening, a multi-chip package structure with a hanging area and System of law. This hair sheet 2: Japanese chip packaging structure 'its system includes:-a substrate, a plurality of crystals, and 糸 are located on a miscellaneous board, and each of the chips can be conductive with the substrate by a gold wire, a number of adhesive layers It is located between the two wafers to make it sandwich-shaped; and a plurality of spacers is wrapped in each of the adhesive layers to support each wafer. The size of this paper is appropriate and the national standard is 297 mm) ----- 1 --- V -------------- Order ---------- MT (please first Read the notes on the back and fill in this page) 516193 Α7 Β7 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (see Figure 2) This is the first preferred implementation of the multi-chip package structure of the present invention The schematic diagram of the example. And Figures A ~: F are a preferred embodiment of the process flow of the first preferred embodiment shown in Figure 2. In the first preferred embodiment shown in Figure 2, the multi-chip The package structure 2 includes a plurality of wafers, a substrate 23, a plurality of adhesive layers, and a plurality of spacers. The plurality of wafers are located above the substrate 23, and in this embodiment include a first wafer 21 and a The second wafer 22, each of the wafers 21 and 22 has an active side 210, 220 (Active Side) and an inactive side 211, 221 (Inactive Side). The active surfaces 21 and 220 are the circuits of the wafers 21 and 22. The side surface on which the design is located, and a plurality of contacts are provided at predetermined positions 210 and 220 on the operating surfaces of each of the wafers 21 and 22 The connection pads 212 and 222 are used to become the interface between the circuits on the chips 21 and 22 and the outside world. In this preferred embodiment, the connection pads 212 and 222 are commonly known as metal pads or aluminum pads (A1 Pad) in the industry. The plurality of connection pads 212 and 222 on the operating surface 210 of one wafer 21 and the operating surface 220 of the second wafer 22 are electrically conductive with the substrate 23 by way of gold wires 213 and 223. The active surface 211 is bonded to the substrate 23. In the preferred embodiment, the non-active surface 211 of the first wafer 21 is attached to the substrate 23 through a wafer adhesive layer 24, and the wafer adhesive layer 24 can be thermally bonded. Soluble double-sided tape (Dual-Sided Adhesive Tape), silver glue, epoxy resin (EPOΠ) and other adhesive materials. The several adhesive layers, which are located between the two wafers, make it a sandwich shape, In this embodiment, the adhesive layer 25 includes a first adhesive layer 250 and a second adhesive layer 251, wherein the first adhesive layer 250 is used to adhere to the space 8. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297) Mm) ---- i .--- V ------------- Order ---------- (Please read the back first (Please fill in this page again for the above precautions) 516193
五、發明說明（ 經濟部智慧財產局員工消費合作社印製 祕⑽咖），且_二黏著層251填充第_晶片21與第 二晶片22__㈣，使第二晶㈣緊紅平整的黏合 於第二黏著層251，實際上，第-黏著層250與第二黏著層 251亦是採用熱熔性雙面膠帶〜卜V. Description of the invention (printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the secret cocoa), and the second adhesive layer 251 is filled with the first wafer 21 and the second wafer 22__㈣, so that the second crystal is tightly and flatly bonded to the second wafer The adhesive layer 251, in fact, the first-adhesive layer 250 and the second adhesive layer 251 are also made of hot-melt double-sided tape ~
Tape)、銀膠、環氧樹脂（Ερ〇χγ)等具黏 ，其可當作整雜著層25來看，_隔物_包覆於該黏 著層25内，用以支撐第二晶片22。 藉由如圖二所示之三明治般之結構，由於該第一晶片 21與第二晶片22間並無空隙，所以，本發明多曰 結構2不僅使得打金線的方式更容易控制，且使二打金線 時更為精準，以有效提高製程之良率。該第一晶片21與第 二晶片22可為具有不同功能之晶片，例如，第一晶片21可 為一邏輯電路之晶片而第二晶片22係為一記憶體電路之晶 片，因而可在同一 1C中同時包括有數種不同功能之晶片， 使1C之設計及使用彈性大為增加。當然，任何熟習半導體 之人士在參閱前述說明後，當可輕易思及，而令該第一晶 片21與第二晶片22係為具有相同功能之晶片。 於以下所述之實施例中，相同於前述之元件將以相同 的編號及名稱命名，且不再重覆贅述其結構功能。 請參閱圖三Α〜三F為圖二所示實施例之多晶片封裝結 構2之製法的一較佳製程步驟流程實施例，其包括有下列 步驟： (a)於一第一晶片21之非作動面211上藉由晶片黏著 層24結合於基板23上。 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） \ Ϊ --------訂--------— (請先閱讀背面之注意事項再填寫本頁) 516193 經濟部智慧財產局員工消費合作社印製 A7 一 ~~ ______ 五、發明說明（7) (b) 以打金線之方式，將第一晶片21之作動面21〇上 的連接墊212藉由金線加連接輕合於基板23上，使第一晶 片21上之電路可經由金線213與該基板23導通電性，而該 基板23再與外界導通電性。 (c) 將間隔物26以一第一黏著層25〇接合於第一晶片 21之作動面210上，且該間隔物26較該第一晶片21尺寸 小，以避免壓垮金線213。 (d) 再覆蓋一第二黏著層251，包覆第一晶片21之作 動面210露出之部分及間隔物26與第一黏著層25〇露出之部 分，用以接合第二晶片22之非作動面221，其中該第一黏 著層250與該第二黏著層251形成將間隔物26包覆於内之一 黏著層25，且该第一晶片21、該黏著層25及該第二晶片22 形成三明治狀的結構。 (e) 以打金線之方式，將第二晶片22之作動面22〇上 的連接墊222藉由金線223連接耦合於基板23上，使第二晶 片22上之電路可經由金線223與該基板23導通電性，並完 成6亥多晶片封裝結構2。 (0然後，再以封裝樹脂27進行封裝（Molding)包 覆該多晶片封裝結構以保護之，以形成完整之多晶片封裝 結構2。 請參閱圖四，其係為本發明之多晶片封裝結構之第二 較佳實施例示意圖。 於圖四所示之第二較佳實施例中，該多晶片封裝結構 3亦是將第一晶片31藉由晶片黏著層3 4結合於基板3 3上 (請先閱讀背面之注意事項再填寫本頁) --------訂--------. 10 A7 A7 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 、發明說明（丨P ) 後、，以打金線之方式，使第_晶片31上之電路可與基板33 導通電性，之後’重覆第—較佳實施例之步驟⑹至步驟 (e)可將間物36a用第-黏著層35〇a與第二黏著層3犯所 組成之黏著層35am，且藉由黏著層—接合第二晶片 32、間隔物36b用第-黏著層35〇b與第二黏著層35化所組 成之黏著層35b包覆住，且藉由黏著層咖接合第三晶片 37、間隔物36c用第-黏著層35Qc與第二黏著層351。所組成 =黏著層35c包覆住’且藉由黏著層35c接合第四晶片％， 最後’再以封裝樹脂39進行封裝⑽ding)包覆該多晶 片封裝結構絲護之，㈣成完整之多晶料裝結構3， 如此便可完成更多晶片之封裝’且晶片與晶片間仍然都沒 有空隙’故其不會_較多晶片，而影響打金線的控 制’且不會降低打金線之精準度，更能有效提高製程之良 率、速度等等，再此不多加贅述。 如圖五A所示’其係為本發明之第—較佳實施例與外 界搞合之-較佳實施例，其中可於該多晶片封裝結構2之 基板23上裝設複數個錫球4，並·所述之錫球4餘它電 路板轉合以完成電性連接。如圖划所示，其係為本發明 之第-較佳實施例與外界耗合之另—較佳實施例，其中可 於該多晶片封裝結構2之基板以引腳5插入的方式就它電 路板搞合以完成電性連接。當然，任何熟習半導體之人士 在參閱前述說明後，t可輕易思及，本發明之第二較佳實 ^=外_合亦可_上述之方式，或其它常用之方式 本紙張尺度適财關家標準 ----Ί--Ί-------------訂---------- SI (請先閱讀背面之注意事項再填寫本頁) 516193Tape), silver glue, epoxy resin (Eρ〇χγ), etc. are sticky, which can be viewed as the entire hybrid layer 25. The _spacer_ is wrapped in the adhesive layer 25 to support the second chip 22 . With a sandwich-like structure as shown in FIG. 2, since there is no gap between the first wafer 21 and the second wafer 22, the structure 2 of the present invention not only makes it easier to control the way of punching gold wires, but also It is more accurate when hitting the golden line to effectively improve the yield of the process. The first wafer 21 and the second wafer 22 may be wafers having different functions. For example, the first wafer 21 may be a wafer of a logic circuit and the second wafer 22 is a wafer of a memory circuit. It also includes several chips with different functions, which greatly increases the design and use flexibility of 1C. Of course, anyone who is familiar with semiconductors can easily think about it after referring to the foregoing description, so that the first wafer 21 and the second wafer 22 are wafers having the same function. In the embodiments described below, the same components as those described above will be named with the same numbers and names, and their structural functions will not be described repeatedly. Please refer to FIGS. 3A to 3F, which are a preferred process step embodiment of the method for manufacturing the multi-chip package structure 2 of the embodiment shown in FIG. 2, which includes the following steps: (a) a non- The operating surface 211 is bonded to the substrate 23 through the wafer adhesive layer 24. 9 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) \ Ϊ -------- Order --------— (Please read the precautions on the back before filling (This page) 516193 A7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs I ~~ ______ V. Description of the invention (7) (b) The connection pad on the operating surface 21 of the first chip 21 is gold-plated. 212 is lightly connected to the substrate 23 by a gold wire connection, so that the circuit on the first chip 21 can be electrically conductive with the substrate 23 through the gold wire 213, and the substrate 23 is electrically conductive with the outside. (c) The spacer 26 is bonded to the operating surface 210 of the first wafer 21 with a first adhesive layer 25, and the spacer 26 is smaller in size than the first wafer 21 to avoid crushing the gold wire 213. (d) Cover a second adhesive layer 251 to cover the exposed part of the active surface 210 of the first wafer 21 and the exposed part of the spacer 26 and the first adhesive layer 25, for bonding the non-actuated part of the second wafer 22 Surface 221, wherein the first adhesive layer 250 and the second adhesive layer 251 form an adhesive layer 25 that covers the spacer 26 therein, and the first wafer 21, the adhesive layer 25, and the second wafer 22 are formed Sandwich-like structure. (e) Coupling the connection pad 222 on the operating surface 22 of the second chip 22 with the gold wire to the substrate 23 through the gold wire 223, so that the circuit on the second chip 22 can pass through the gold wire 223. Conductivity with the substrate 23 is completed, and the CMOS multi-chip package structure 2 is completed. (0) Then, the multi-chip packaging structure is encapsulated with molding resin 27 to protect it to form a complete multi-chip packaging structure 2. Please refer to FIG. 4, which is the multi-chip packaging structure of the present invention. Schematic diagram of the second preferred embodiment. In the second preferred embodiment shown in FIG. 4, the multi-chip packaging structure 3 also combines the first chip 31 with the substrate 3 3 through the wafer adhesive layer 3 4 ( (Please read the precautions on the back before filling this page) -------- Order --------. 10 A7 A7 Printed and Invented by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (丨 P) After that, the circuit on the _th wafer 31 can be electrically conductive with the substrate 33 by way of gold wire, and then 'repeat the step of the preferred embodiment-step (e) to use the intervening 36a' The first-adhesive layer 35oa and the second-adhesive layer 35am are composed of an adhesive layer 35am, and the first-adhesive layer 35ob and the second-adhesive layer 35 are used to bond the second wafer 32 and the spacer 36b with the adhesive layer The adhesive layer 35b composed of the coating is covered, and the third wafer 37 and the spacer 36c are bonded with the first layer through the adhesive layer coffee. The adhesive layer 35Qc and the second adhesive layer 351. Composition = the adhesive layer 35c is covered and the fourth wafer% is bonded by the adhesive layer 35c, and finally the encapsulation resin 39 is used to encapsulate the multi-chip packaging structure. The wire is protected, and a complete polycrystalline material packaging structure 3 is formed, so that more packages can be completed ', and there is still no gap between the wafers', so it will not _ more wafers, which affects the gold wire Control 'without reducing the precision of the gold line, it can effectively improve the yield, speed, etc. of the process, so I won't go into details here. As shown in FIG. 5A, it is the first preferred embodiment of the present invention and the outside world is a preferred embodiment, in which a plurality of solder balls 4 can be mounted on the substrate 23 of the multi-chip package structure 2. And the other 4 solder balls are turned on to complete the electrical connection. As shown in the figure, it is the first preferred embodiment of the present invention and the other preferred embodiment, in which the substrate of the multi-chip package structure 2 can be inserted by means of pins 5 The circuit boards are engaged to complete the electrical connection. Of course, anyone who is familiar with semiconductors can easily think about it after referring to the foregoing description. The second preferred embodiment of the present invention is ^ = foreign_ 合 可以 _the above-mentioned method, or other commonly used methods. Home Standard ---- Ί--Ί ------------- Order ---------- SI (Please read the precautions on the back before filling this page) 516193
五、發明說明（ 禱 、τ上所述本發明之多晶片封裝結構及其製法，不僅 f寻打金線㈣式更容易控制，且使得打金線時更為精 效提向製程之良率。且本發明之多晶片封裝結構 適用在同一 IC中同時包括有數種不同功能 之曰曰片（或也可是相同的晶片），之設計及使用彈性 ^為=加二其整體結構非常簡單、體積面積與長度均較 小、裝程容易、成本亦非常低廉，充份顯示出本發明之目 士均深富實施之進步性’極具產業之利用價值， f ϋ市社前所未狀新發明，完全符合發明專利之 要件，麦依法提出申請。 、唯以上所述者’僅為本發明之較佳實施㈣已， ==本發明所實施之範圍。即大凡綱明申;專 菩^之均轉化與修飾，冑應仍屬於本發明專利涵 I粑内，錢貴審查委員明鑑，並祈惠准，是所至 (請先閱讀背面之注意事項再填寫本頁) ---- 訂----- 經濟部智慧財產局員工消費合作社印製V. Description of the invention (prayer, the multi-chip packaging structure and manufacturing method of the present invention described on τ, not only is it easier to control the fetching of the gold wire type, but also makes it more efficient to improve the yield of the manufacturing process And the multi-chip package structure of the present invention is suitable for simultaneously including several different functions of the chip (or the same chip) in the same IC, the design and use flexibility is ^ == plus two, its overall structure is very simple, volume Both the area and length are small, the installation process is easy, and the cost is very low. It fully shows that the progress of this invention is rich in the implementation of the advanced 'high industrial use value, f. , In full compliance with the requirements of the invention patent, Mai made an application according to law. The only ones mentioned above are only the preferred implementation of the present invention, == the scope of the implementation of the present invention. All are transformed and modified. They should still fall within the scope of the present patent patent. Qian Gui's reviewing committee made a clear reference and prayed for it. (Please read the precautions on the back before filling this page) ---- Order- ---- Staff of Intellectual Property Bureau, Ministry of Economic Affairs Printed cooperatives fee