JPS59132154A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59132154A JPS59132154A JP58005261A JP526183A JPS59132154A JP S59132154 A JPS59132154 A JP S59132154A JP 58005261 A JP58005261 A JP 58005261A JP 526183 A JP526183 A JP 526183A JP S59132154 A JPS59132154 A JP S59132154A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor element
- lead frame
- uneven parts
- deviation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は単導体装置にかかり、特に半導体製造に用いる
リードフレームに関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a single conductor device, and particularly to a lead frame used in semiconductor manufacturing.
（従来例の構成とその問題点）
第１図に半導体素子】をアイランド部２に゛載置する工
程（ダイボンド工程）の後、半導体素子１のポンディン
グパッド３とリードフレームの内部リード４を電気的伝
導線（金線あるいはアルミニ゛ウム線〕５により電気的
接続を４る工程（ワイヤボンディング工程）を終了した
従来構造のカードブ レームを用いて構成された半導体
装置の平面図を示す。本構辺の問題点の１つは、リード
フレームのアイランド部２上に載置された半導体素子１
がアイランド部、の中央にダイボンドされず、ずれてダ
イボンドされた場合に、そのダイボンド位置ずれ量の検
出が容易にできないことであり、まだワイヤボンディン
グ工程およびその後工程の封止前のボンディング検査工
程において、ポンディングパッド３と対応した内部リー
ド４とが正しくワイヤボンディングされているか否かを
確認する際、特に半導体装置の外部接続ルピン数が多く
なるにつれて目視検査作業が困難となり、多くの時間を
要する等の問題点があった。(Structure of conventional example and its problems) Figure 1 shows that after the process (die bonding process) of placing the semiconductor element on the island part 2, the bonding pads 3 of the semiconductor element 1 and the internal leads 4 of the lead frame are connected. This is a plan view of a semiconductor device constructed using a card frame of a conventional structure that has undergone the step of electrical connection (wire bonding step) using an electrically conductive wire (gold wire or aluminum wire). One of the problems with the construction is that the semiconductor element 1 mounted on the island part 2 of the lead frame
If the die bond is not die-bonded to the center of the island part and is die-bonded at a deviation, the amount of deviation in the die bond position cannot be easily detected, and it is difficult to detect the amount of deviation in the die bond position. When checking whether the bonding pad 3 and the corresponding internal lead 4 are wire-bonded correctly, visual inspection becomes difficult and takes a lot of time, especially as the number of externally connected pins of a semiconductor device increases. There were problems such as.
（発明の目的）
本発明の目的は上記の問題点を軽減し、より能率的な作
業が行なわれるためのリードフレームを有する半導体装
置を提供するものである。(Object of the Invention) An object of the present invention is to provide a semiconductor device having a lead frame that alleviates the above-mentioned problems and enables more efficient work.
（発明の構成）
本発明は半導体素子を載置するアイランド部の少なくと
も１辺以上に凹凸部を設けたことを特徴とする半導体装
置用リードフレームで構成される半導体装置である。(Structure of the Invention) The present invention is a semiconductor device constituted by a lead frame for a semiconductor device, characterized in that an uneven portion is provided on at least one side of an island portion on which a semiconductor element is placed.
（実施例の説明）
第３図に本発明の一実施例を示す。リードル−ムの半導
体素子１を載置するアイランド部団周囲に凹凸部６を設
けたことＫよシダイボンド位置ズレが容易に判別できる
。また凹凸部６の形状寸法および凹部と凸部間隔を規則
正しい寸法にすることにより、その位置と半導体素子１
の外周線から、ダイボンドずれ量等を容易に検出できる
。(Description of Embodiment) FIG. 3 shows an embodiment of the present invention. Since the uneven portion 6 is provided around the island group on which the semiconductor element 1 of the lead room is placed, the deviation in the position of the die bond can be easily determined. In addition, by making the shape and dimensions of the uneven portion 6 and the interval between the concave portion and the convex portion regular, the position and the semiconductor element 1 can be adjusted.
The amount of deviation of the die bond, etc. can be easily detected from the outer circumferential line.
また第４図も本発明の一実施例であり、リードフレーム
の半導体素子１を載置するアイランド部２の周囲にその
先端が配置・されたリード部４の５本おきのリードに向
って、凹凸部６を設けたことによりピン番号が容易に判
別できる。また凹凸部６の凹凸部の筒数、寸法の大小、
形状の変化によシ更にピン番号の特定番号、たとえば１
番、１０番、グラウンド接地ピン（アース端子）の認識
判２ 別を容易にすることができる。FIG. 4 also shows an embodiment of the present invention. By providing the uneven portion 6, the pin number can be easily identified. In addition, the number of cylinders and the size of the uneven portion of the uneven portion 6,
Due to the change in shape, a specific number of the pin number, e.g. 1
No. 2, No. 10, and ground pin (earth terminal) can be easily identified.
（発明の効果）
本発明により、半導体装置組立作業上の能率向上がはか
れるのみでなぐ、すでに製造完了した半導体装置の解析
の際にも有効である。(Effects of the Invention) The present invention not only improves the efficiency of semiconductor device assembly operations, but is also effective in analyzing semiconductor devices that have already been manufactured.
第１図は従来構造のリードフレームを用いて構成された
半導体装置の平面図、第２図は従来構造のリードフレー
ムに半導体素子がずれてマウントされたときの平面図、
第３図、第４図は本発明の詳細な説明する平面図である
。
」 ・・・・・・・半導体素子、 ２・・・・・・アイ
ランド部、３°°°゛゛°ポンデイングパツド、 ４・
・・・・・・内部リード、 ５・・ ・・・′電気的伝
導線、 ６・・・・・・・・・凹凸部。
第１図
第２図
第３図
第４図FIG. 1 is a plan view of a semiconductor device constructed using a lead frame of a conventional structure, and FIG. 2 is a plan view of a semiconductor device mounted on a lead frame of a conventional structure with a misalignment.
FIGS. 3 and 4 are plan views illustrating details of the present invention. ”...Semiconductor element, 2...Island portion, 3°°°゛゛°ponding pad, 4.
...Inner lead, 5...'Electrical conductive wire, 6...Irregularities. Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
上に凹凸部を有している半導体装置用リードフレームを
有することを特徴とす暮半導体装置。A semiconductor device comprising a lead frame for a semiconductor device having an uneven portion on at least one side of an island portion on which a semiconductor element is mounted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58005261A JPS59132154A (en) | 1983-01-18 | 1983-01-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58005261A JPS59132154A (en) | 1983-01-18 | 1983-01-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59132154A true JPS59132154A (en) | 1984-07-30 |
Family
ID=11606282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58005261A Granted JPS59132154A (en) | 1983-01-18 | 1983-01-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59132154A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07161911A (en) * | 1993-12-10 | 1995-06-23 | Nec Corp | Resin-sealed type semiconductor device |
-
1983
- 1983-01-18 JP JP58005261A patent/JPS59132154A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07161911A (en) * | 1993-12-10 | 1995-06-23 | Nec Corp | Resin-sealed type semiconductor device |
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