JPH10189648A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH10189648A
JPH10189648A JP34221996A JP34221996A JPH10189648A JP H10189648 A JPH10189648 A JP H10189648A JP 34221996 A JP34221996 A JP 34221996A JP 34221996 A JP34221996 A JP 34221996A JP H10189648 A JPH10189648 A JP H10189648A
Authority
JP
Japan
Prior art keywords
chip
integrated circuit
semiconductor integrated
area
square
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP34221996A
Other languages
Japanese (ja)
Inventor
Taketo Fukuda
健人 福田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP34221996A priority Critical patent/JPH10189648A/en
Publication of JPH10189648A publication Critical patent/JPH10189648A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit chip which is small in area but can have a large number of bonding pads. SOLUTION: A semiconductor integrated circuit chip is formed in a triangle. If the length of the one side of a conventional square chip is set L, the total circumferential length of the conventional square chip is represented by 4L. A triangular semiconductor integrated circuit chip is obtained by cutting a square chip into two pieces along its diagonal line, the triangular semiconductor integrated circuit chip is half as large in area as the square chip, but its circumferential length is about 3.41L, so it is found that a reduction in circumfernetial length is smaller than that in area. Therefore, bonding pads 2 are arranged along the periphery of chip 1, whereby a triangular chip can ensure a larger number of bonding pads than a square chip of conventional arts. When comparing a rectangular chip with a triangular chip formed by cutting the rectangular chip into two pieces along its diagonal line, the reduction of a chip in peripheral length is smaller, although its area becomes half, that is the same as in a square chip.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体集積回路装
置に関するものである。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit device.

【０００２】[0002]

【従来の技術】図４に示すように、従来の半導体集積回
路チップの形状は、主に四辺形のチップを使い、そのチ
ップの周囲にボンディングパッド（以下「パッド」とも
いう。）を配置している。また、図５に示すように、こ
れらのボンディングパッド２は、パッケージの外部端子
と接続するためのリード４にボンディングワイヤ３によ
って接続される。そのためボンディングパッド２は、こ
のボンディングワイヤ３がショートしないよう十分な間
隔を持ってチップ１の周囲に配置することが必要であ
る。つまり、ボンディングパッドの数は、半導体集積回
路チップの周囲長によって決定される。2. Description of the Related Art As shown in FIG. 4, a conventional semiconductor integrated circuit chip mainly uses a quadrilateral chip, and bonding pads (hereinafter also referred to as "pads") are arranged around the chip. ing. As shown in FIG. 5, these bonding pads 2 are connected to leads 4 for connecting to external terminals of the package by bonding wires 3. Therefore, it is necessary to arrange the bonding pads 2 around the chip 1 with a sufficient interval so that the bonding wires 3 are not short-circuited. That is, the number of bonding pads is determined by the peripheral length of the semiconductor integrated circuit chip.

【０００３】[0003]

【発明が解決しようとする課題】従来の四辺形または多
角形の半導体集積回路チップでは、多くのボンディング
パッドを持たせようとすると、チップの面積もまた大き
なものになるという問題を有する。そこで本発明はこの
ような問題点を解決するもので、その目的は小さな面積
で多くのボンディングパッドを持つことのできる半導体
集積回路チップを提供することにある。In a conventional quadrilateral or polygonal semiconductor integrated circuit chip, there is a problem that the area of the chip also becomes large if many bonding pads are provided. Accordingly, the present invention is to solve such a problem, and an object of the present invention is to provide a semiconductor integrated circuit chip having a small area and having many bonding pads.

【０００４】[0004]

【課題を解決するための手段】本発明の請求項１に記載
された半導体集積回路装置は、半導体集積回路装置より
外部装置の電気的導通をとるための端子として用いるパ
ッドを、外周に具備する半導体集積回路チップにおい
て、チップ形状を三角形にすることによってその周囲長
と面積の比（周囲長／面積）を、従来の四辺形または多
角形のチップより大きくすることを特徴とする。According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device having a pad used as a terminal for electrically connecting an external device to the semiconductor integrated circuit device. A semiconductor integrated circuit chip is characterized in that the shape of the chip is triangular so that the ratio of the perimeter to the area (perimeter / area) is larger than that of a conventional quadrilateral or polygonal chip.

【０００５】[0005]

【作用】チップ面積が小さく、多くのボンディングパッ
ドを持つ半導体集積回路チップを実現できる。The semiconductor integrated circuit chip having a small chip area and many bonding pads can be realized.

【０００６】[0006]

【発明の実施の形態】本発明について、実施例に基づき
詳細に説明する。図１に本発明の一実施例を示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail based on embodiments. FIG. 1 shows an embodiment of the present invention.

【０００７】図４のように、正方形の半導体集積回路チ
ップの形状を考えた場合、そのボンディングパッド２
は、チップ１の周囲に可能な限り多く配置されている。
つまり、ボンディングパッドの数は、その半導体集積回
路チップの周囲長にほぼ比例すると考えられる。そこ
で、図４のような正方形のチップ１の一辺の長さをＬと
すると、その周囲長は４Ｌとなる。しかし、図１のよう
な正方形の対角線上で切った三角形の形をした半導体集
積回路チップ２を考えてみると、その面積は２分の１に
なっているが、その周囲長は約３．４１Ｌとなり、面積
が半分になるのに対し周囲長の減少は面積の減少に比べ
少ないことがわかる。そのため、ボンディングパッド２
をチップ１の周囲に配置することにより、図４のような
従来の正方形のチップに比べ小さな面積で多くのボンデ
ィングパッドを確保することができる。また、長方形の
チップとその対角線上で切った三角形のチップを比べて
みても、正方形の場合と同様に面積は半分になるが、そ
の周囲長の減少は少ない。As shown in FIG. 4, when the shape of a square semiconductor integrated circuit chip is considered, the bonding pad 2
Are arranged around the chip 1 as much as possible.
That is, it is considered that the number of bonding pads is substantially proportional to the peripheral length of the semiconductor integrated circuit chip. Therefore, assuming that the length of one side of the square chip 1 as shown in FIG. 4 is L, its peripheral length is 4L. However, when considering a semiconductor integrated circuit chip 2 having a triangular shape cut on a diagonal line of a square as shown in FIG. 1, its area is halved, but its peripheral length is about 3. 41L, which indicates that the area is reduced by half, while the decrease in the perimeter is smaller than that of the area. Therefore, the bonding pad 2
Are arranged around the chip 1, it is possible to secure more bonding pads in a smaller area than in a conventional square chip as shown in FIG. Also, when comparing a rectangular chip with a triangular chip cut on the diagonal line, the area is halved as in the case of a square, but the perimeter is little reduced.

【０００８】図２は、図１のチップを実際のウェハー上
に作成する際のチップの配置である。また、図３は本発
明の他の実施例でのウェハー上でのチップ配置を示して
いる。図２および図３の三角形はそれぞれ半導体集積回
路チップ１である。これらの例から分かるように実際の
ウェハーのダイシング工程は非常に簡単なものであり、
ウェハー上に無駄な領域を作ることなく製造することが
できる。FIG. 2 shows an arrangement of chips when the chip of FIG. 1 is formed on an actual wafer. FIG. 3 shows a chip arrangement on a wafer in another embodiment of the present invention. Each of the triangles in FIGS. 2 and 3 is a semiconductor integrated circuit chip 1. As can be seen from these examples, the actual wafer dicing process is very simple,
It can be manufactured without creating a useless area on a wafer.

【０００９】以上のように、チップ形状を三角形にする
ことにより、従来の四辺形または多角形の半導体集積回
路チップより、小さな面積で周囲長の長いチップが実現
できる。そして、そのチップの周囲にボンディングパッ
ドを配置することによって、面積が小さく多くのボンデ
ィングパッドを持つことのできる半導体集積回路チップ
を実現できる。As described above, by making the chip shape a triangle, a chip having a smaller area and a longer perimeter than conventional quadrilateral or polygonal semiconductor integrated circuit chips can be realized. By arranging bonding pads around the chip, a semiconductor integrated circuit chip having a small area and having many bonding pads can be realized.

【００１０】[0010]

【発明の効果】小さな面積で多くのボンディングパッド
を持つ半導体集積回路チップを実現できる。As described above, a semiconductor integrated circuit chip having many bonding pads in a small area can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体集積回路チップの図。FIG. 1 is a diagram of a semiconductor integrated circuit chip of the present invention.

【図２】本発明の一実施例を示す半導体ウェハーの図。FIG. 2 is a view of a semiconductor wafer showing one embodiment of the present invention.

【図３】本発明の他の実施例を示す半導体ウェハーの
図。FIG. 3 is a view of a semiconductor wafer showing another embodiment of the present invention.

【図４】従来の半導体集積回路チップの図。FIG. 4 is a diagram of a conventional semiconductor integrated circuit chip.

【図５】チップとリードの接続方法を示す部分図。FIG. 5 is a partial view showing a method of connecting a chip and a lead.

【符号の説明】[Explanation of symbols]

１ チップ ２ ボンディングパッド ３ ボンディングワイヤ ４ リード 1 chip 2 bonding pad 3 bonding wire 4 lead

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】半導体集積回路装置より外部装置の電気的
導通をとるための端子として用いるパッドを、外周に具
備する半導体集積回路装置において、チップ形状を三角
形にすることによってその周囲長と面積の比（周囲長／
面積）を、従来の四辺形または多角形のチップより大き
くすることを特徴とする半導体集積回路装置。1. A semiconductor integrated circuit device having a pad used as a terminal for establishing electrical conduction from an external device to a semiconductor integrated circuit device on an outer periphery. Ratio (perimeter /
(Area) is larger than that of a conventional quadrilateral or polygonal chip.
JP34221996A 1996-12-20 1996-12-20 Semiconductor integrated circuit device Withdrawn JPH10189648A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34221996A JPH10189648A (en) 1996-12-20 1996-12-20 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34221996A JPH10189648A (en) 1996-12-20 1996-12-20 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH10189648A true JPH10189648A (en) 1998-07-21

Family

ID=18352044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34221996A Withdrawn JPH10189648A (en) 1996-12-20 1996-12-20 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH10189648A (en)

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20040302