KR980012334A - Multilayer semiconductor chip package and manufacturing method thereof - Google Patents

Abstract

[0001] The present invention relates to a semiconductor chip package, and more particularly, to a stacked semiconductor chip package capable of achieving thinnestness of a device by using a tape automated bonding technology (TAB) A bonding pad is formed on both sides of an edge of an upper surface of a semiconductor chip so as to face each other and is electrically connected to the bonding pad by bumps to transmit an electrical signal to the outside And a protective film is formed on a surface of the exposed semiconductor chip, wherein the protective film is bonded to the back surface of the semiconductor chip.

Description

Multilayer semiconductor chip package and manufacturing method thereof

[0001] The present invention relates to a semiconductor chip package, and more particularly, to a stacked semiconductor chip package capable of achieving thinnestness of a device by using a tape automated bonding technology (TAB) .

2. Description of the Related Art [0002] In recent years, with the tendency that a semiconductor device becomes multifunctional, a large number of input / output, a high speed, and a surface mounting, a semiconductor chip package tends to be reduced in size, thickness and function. In this trend, TQFP (Thin Quart Flat Package), TSOP (Thin Small Outline Package) and TAB package are attracting attention.

Despite this trend, however, semiconductor chip packages (CSPs) of the same size as the bare chip have been developed.

Further, a stacked semiconductor chip package in which a plurality of semiconductor chip packages are stacked in a pig-back form or a plurality of chips are stacked in a single semiconductor package, rather than a conventional method of mounting one semiconductor chip in one semiconductor package It is known.

1 is a cross-sectional view of a conventional SOP type semiconductor chip package. As shown in the figure, the upper surface of the die pad 7 of the lead frame and the lower surface of the semiconductor chip 2 are attached by an insulating adhesive 6 or an insulating tape (not shown) or the like The semiconductor chip 2 is electrically connected to the bonding pads 1 and the inner leads 3 which are formed so as to correspond to the edge portions of the upper surface of the semiconductor chip 2 by the conductive wires 4, The wires 4 and the inner leads 3 are sealed by the body 5 of the molding resin.

FIG. 2 is a perspective view showing the semiconductor chip package of FIG. 1 stacked in a pig-back form. As shown in the figure, a plurality of semiconductor chip packages 20 are stacked on the lowermost semiconductor chip package 10, and the outriggers 11 constituting the upper semiconductor chip package 20 are stacked on the lower semiconductor chip package 10, And is generally fixed to the outward 12 constituting the battery 10 so as to be electrically connectable.

Out leads 12 of the lowermost semiconductor chip package 10 are formed outwardly in the form of a known small outline package (SOP) and mounted on a PCB substrate (not shown).

Here, the out lead 11 of the semiconductor chip package 20 may be formed in a dual inline package (DIP) instead of the SOP type.

However, the conventional semiconductor package having the above-described structure has the advantage of improving the degree of integration. However, it is a structure in which several semiconductor chip packages formed separately are stacked. In each semiconductor chip package, wire- (wire loop height) and the molding thickness of the molding resin, the semiconductor chip package has a disadvantage that it is inferior to the thin and light shortening of the semiconductor chip package.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a stacked semiconductor chip package capable of achieving thinning of a device using TAB technology and high density packaging, and a method of manufacturing the same The purpose is to provide.

1 is a sectional view of a conventional SOP type semiconductor chip package;

FIG. 2 is a perspective view showing an SOP type laminated in a pig-back form. FIG.

3 is an exploded perspective view of the semiconductor chip package according to the present invention.

FIG. 4 is an assembled cross-sectional view of FIG. 3; FIG.

FIG. 5 is a cross-sectional view of a semiconductor chip package according to the present invention stacked. FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

30: semiconductor chip 31: protective film

32: bonding pad 33: bump

34: tap film 35: conductive pattern

36, 42: Adhesive tape 37: Via hole

40: upper conductive pattern 41, 43: lower conductive pattern

44, 45, 46, 47: Both end conductive patterns 100, 200: Semiconductor chip package

According to an aspect of the present invention, there is provided a semiconductor chip package, wherein bonding pads are formed on opposite sides of an upper surface of a semiconductor chip so as to face each other, and are electrically connected to the bonding pads by bumps, And a protective film is formed on a surface of the exposed semiconductor chip, wherein the protective film is formed on the exposed surface of the semiconductor chip, .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 3 is an exploded perspective view of the tap film of the semiconductor chip package according to the present invention in a state where it is not bent, and Fig. 4 is an assembled cross-sectional view of Fig. As shown in the figure, a via hole 37 is formed at one side of the tab film 34 corresponding to the bonding pads 32 of the semiconductor chip 30, A conductive pattern 35 is formed on the upper surface of the tap film 34 at regular intervals. The lower surface of the via hole 37 and the upper surface of the bonding pad 32 are adhered and fixed to the solder bump 33 so that the lead 35 is electrically connected to the bonding pad 32. And an adhesive tape 36 is attached to the other side of the lower surface thereof.

The end of the semiconductor chip 30 in the width direction and the back surface of the semiconductor chip 30 are shielded from the outside by the bent tap film 34, (36).

A protective film 31 is formed on the surface of the semiconductor chip 30 except for the portion where the tap film 34 is adhered to and a portion where the tap film 34 on the back surface of the semiconductor chip 30 is not adhered The protective film 31 can be formed.

5 is a cross-sectional view showing a stacked structure of the semiconductor chip package according to the present invention. As shown in FIG. 5, the surface of the upper conductive pattern 40 of the semiconductor chip package 100 and the lower conductive pattern of the semiconductor package 200 41 are adhered by a conductive adhesive tape 42 so as to be electrically connectable.

The semiconductor chip package 100 and 200 can be electrically connected to each other by using a general adhesive agent (not shown). The semiconductor chip package 100 can be electrically connected to the surface of the upper conductive pattern 40 of the semiconductor chip package 100 The surface of the conductive pattern 41 of the semiconductor chip package 200 is bonded with a general adhesive. Thereafter, the conductive patterns 44 and 45 at the widthwise ends of the semiconductor chip package 100 and the conductive patterns 46 and 47 at the widthwise ends of the semiconductor chip package 200 are soldered (not shown) And can be electrically connected by soldering.

The lower conductive pattern 43 of the semiconductor chip package 100 has a structure that is mounted on a PCB substrate (not shown) by a known surface mounting method.

Here, the number of stacked semiconductor chip packages is not limited to the above-described embodiment, and a plurality of semiconductor chip packages may be stacked on the semiconductor chip package 100.

A method of manufacturing the semiconductor chip package according to the present invention will now be described.

First, a wafer (not shown) is sawed to the size of each semiconductor chip, separated into respective semiconductor chips, and then a bump (not shown) is formed on the bonding pad 32 of the semiconductor chip 30, 33 are bonded to the lower surface of the via hole 37 formed on one side of the tap film 34 so as to be electrically connected.

In this state, the tab film 34 is bent in a " C "shape so that the back surface of the semiconductor chip 30 is sealed with the adhesive tape 36 so that the end portions in the width direction of the semiconductor chip 30 are blocked from the outside. 34 are adhered to each other.

Thereafter, the protective film 31 is formed on the surface of the semiconductor chip 30 except for the portion where the tap film 34 is adhered, with a non-conductive coating liquid.

The surface of the upper lead 40 of the completed semiconductor chip package 100 and the surface of the lower conductive pattern 41 of the semiconductor chip package 200 are bonded with the conductive adhesive tape 42 in this way. Then, a new semiconductor chip package is stacked on the semiconductor chip package 200 by the above-described method. Thus, the stacked semiconductor chip package 300 is completed.

As described above, the multilayered semiconductor chip package according to the present invention includes bonding pads formed on opposite sides of a surface of a semiconductor chip so as to face each other, and electrically connected to the bonding pads by bumps to transmit electrical signals to the outside And a protective film is formed on the exposed surface of the semiconductor chip, so that the entirety of the semiconductor chip package can be prevented from being damaged, Not only the thickness can be made thinner but also the structure is simplified, the manufacturing process is simplified, and the manufacturing cost is reduced.

Claims (7)

A semiconductor device, comprising: a semiconductor chip; a semiconductor chip mounted on the semiconductor chip; a semiconductor chip mounted on the semiconductor chip; a semiconductor chip mounted on the semiconductor chip; And a protective film is formed on a surface of the exposed semiconductor chip, wherein the protective film is bonded to the back surface of the semiconductor chip. 2. The semiconductor device according to claim 1, wherein the transmission means comprises a via hole formed in the tap film corresponding to the bonding pad, and a conductive pattern formed on an inner wall surface of the via hole and an upper surface of the tap film. Chip package. The semiconductor chip package according to claim 1, wherein the tap film is bonded to the back surface of the semiconductor chip by a polyimide tape. The semiconductor chip package according to claim 1, characterized in that a plurality of semiconductor chip packages are laminated by being attached by adhesive means so that the transfer means on the lower surface of the semiconductor chip package is electrically connected to the transfer means on the upper surface of the semiconductor chip package . The semiconductor chip package according to claim 4, wherein the bonding means is a conductive adhesive tape. Bonding and fixing the tab film to the upper surface of the bonding pad formed on the upper surface of the semiconductor chip so that the via hole formed in communication with the conductive pattern is electrically connected to the outer surface of the tap film; Bending the semiconductor chip so as to be cut off from the outside and bonding and fixing the semiconductor chip to the back surface of the semiconductor chip; and applying a protective film to the exposed surface of the semiconductor chip. The semiconductor chip package according to claim 6, wherein a plurality of semiconductor chip packages are stacked by adhering the conductive pattern of the upper surface of the semiconductor chip package and the conductive pattern of the lower surface of the semiconductor chip package electrically connected to each other, Wherein the semiconductor chip package is manufactured by the method. ※ Note: It is disclosed by the contents of the first application.