JP2001196407A - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same

Info

Publication number
JP2001196407A
JP2001196407A JP2000006507A JP2000006507A JP2001196407A JP 2001196407 A JP2001196407 A JP 2001196407A JP 2000006507 A JP2000006507 A JP 2000006507A JP 2000006507 A JP2000006507 A JP 2000006507A JP 2001196407 A JP2001196407 A JP 2001196407A
Authority
JP
Japan
Prior art keywords
ic
protective material
semiconductor
semiconductor device
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000006507A
Other languages
Japanese (ja)
Inventor
Takashi Hosaka
俊 保坂
Original Assignee
Seiko Instruments Inc
セイコーインスツルメンツ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc, セイコーインスツルメンツ株式会社 filed Critical Seiko Instruments Inc
Priority to JP2000006507A priority Critical patent/JP2001196407A/en
Publication of JP2001196407A publication Critical patent/JP2001196407A/en
Application status is Granted legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/119Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/1191Forming a passivation layer after forming the bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116Lead [Pb] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

PROBLEM TO BE SOLVED: To form IC packages in the wafer state so as to provide the IC packages of the same size with an IC chip.
SOLUTION: Bumps are bonded to electrode pads in a wafer state, then protective material is applied on a wafer, and the bumps are exposed. Thereafter, the wafer is cut off along scribe lines, and an IC package is completed.
COPYRIGHT: (C)2001,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明はICチップと同じ大きさの、いわゆるチップサイズパッケージの構造と、その製造方法に関する。 The present invention relates to the of the same size as the IC chip, the structure of a so-called chip size package, a manufacturing method thereof.

【0002】 [0002]

【従来の技術】これまでに作成されているチップサイズパッケージと呼ばれるものは、ICチップを一個に分離してからICパッケージを作成していた。 BACKGROUND OF THE INVENTION what is called a chip size package which has been created so far, have created an IC package IC chip after separation one.

【0003】 [0003]

【発明が解決しようとする課題】ICパッケージの中にICを入れるためには、かなりの余裕度を取らねばならず、チップサイズパッケージといいながら、実際のサイズはICチップよりかなり大きくなっていた。 In order to put the IC in the IC package [0006] is not must take a considerable margin, while called a chip size package, the actual size had become much larger than the IC chip . また、I In addition, I
Cパッケージ製造の工程が複雑で長いため費用がかかり、かつ作成期間が長かった。 Step C-package production takes a long for cost and complexity, and was longer created period.

【0004】 [0004]

【課題を解決するための手段】上記の問題点を解決するために、本発明はウエハ状態でICパッケージを作成し、ICチップと同じ大きさのICパッケージを提供する。 In order to solve the above problems SUMMARY OF THE INVENTION The present invention creates an IC package in a wafer state, to provide an IC package having the same size as the IC chip. すなわち、ウエハ状態で電極パッドにバンプを接着した後で、保護材料を塗布し、バンプ部分を露出させる。 That is, after bonding the bumps on the electrode pads in a wafer state, the protective material is applied to expose the bump portion. その後スクライブラインでウエハを切断し、ICパッケージを完成させる。 Thereafter, the wafer is cut at the scribe line, to complete the IC package.

【0005】 [0005]

【実施例】本発明は、集積回路(IC)チップと同じ大きさのICパッケージを提供する技術に関するものである。 EXAMPLES The invention relates to a technique to provide an IC package having the same size as the integrated circuit (IC) chip. 以下に本発明の実施例を図面に基づいて説明する。 It is described with reference to embodiments of the present invention with reference to the drawings hereinafter.

【0006】図1は、ウエハサイズで形成された本発明の構造を示すICパッケージの断面図を示す。 [0006] Figure 1 shows a cross-sectional view of an IC package illustrating the structure of the present invention formed by wafer size. 半導体基板1の表面に電極パッド2が形成されている。 The electrode pads 2 are formed on the surface of the semiconductor substrate 1. また、半導体基板1の表面は保護膜3でおおわれている。 Further, the surface of the semiconductor substrate 1 is covered with a protective film 3. 半導体基板内には集積回路が形成されている。 Integrated circuits are formed in a semiconductor substrate. 図1では半導体基板内の集積回路は省略する。 Integrated circuits in the semiconductor substrate in FIG. 1 will be omitted.

【0007】以上のようにしてICチップが構成される。 [0007] The above-way IC chip is configured. 本発明は、このICチップの電極パッド2にバンプ4が接着している。 The present invention, bumps 4 are bonded to the electrode pad 2 of the IC chip. バンプ4の形状は図1に示すように凸形をしている。 The shape of the bumps 4 are the convex, as shown in FIG. ICチップの表面は保護材料5で覆われている。 The surface of the IC chip is covered with a protective material 5.

【0008】以上のようなICパッケージは次のような特徴がある。 [0008] IC package as described above has the following features.

【0009】(1)ICチップと同じ大きさである。 [0009] (1) it is the same size as the IC chip.

【0010】(2)バンプ4の上で保護材料5で切れているため、ICチップは完全に保護材料でおおわれている。 [0010] (2) Since the cut in the protective material 5 on the bump 4, IC chip is covered with completely protected material. この事により、ICチップヘの外部環境からの異物の浸入は阻止されている。 By this thing, infiltration of foreign matter from the external environment of the IC Chippuhe have been prevented. 例えば外部の水分の浸入がないため、ICチップの水分による問題である、電極パッドの腐食等は発生しない。 For example, since there is no penetration of external moisture is a problem due to moisture IC chip, corrosion of the electrode pad is not generated.

【0011】(3)バンプ4の柱部分4aは保護材料5 [0011] (3) of the pillar portion 4a of the bump 4 protective material 5
より飛び出しているため、外部電極との接続が容易である。 Since the more pop-out, it is easy to connect the external electrodes. この事を図2により説明する。 To explain this by FIG. 図2(a)は、図1 2 (a) is, FIG. 1
のウエハサイズで形成されたICパッケージの集合体を個片にした状態の1個のICパッケージの断面構造図である。 The collection of the IC package formed by the wafer size is a sectional view of a single IC package while in pieces. 図2(b)は、図2(a)のICパッケージを実装基板に取付けた状態を示す。 2 (b) shows a state of attaching the IC package on a mounting substrate of FIG. 2 (a). 実装基板16の表面に配線17が形成されている。 Wiring 17 is formed on the surface of the mounting substrate 16. 配線17とバンプ14の柱部分14aが接着している。 Pillar portion 14a of the wiring 17 and the bump 14 is adhered. バンプ14の柱部分14aが保護材料15より飛び出しているため、外部配線17との接続が容易となる。 Since the pillar portion 14a of the bump 14 is jumped out from the protective material 15, it becomes easy to connect the external wiring 17.

【0012】(4)保護材料5はICチップを強固に保持しているため、ICパッケージの強度はICチップ単体の強度に比較し、格段に向上している。 [0012] (4) Since the protective material 5 is firmly holding the IC chip, the strength of the IC package compared to the intensity of the IC chip itself, it is significantly improved.

【0013】(5)構造が簡単なため、材料費を含めた製造コストが非常に安い。 [0013] (5) Since the structure is simple, is very cheap manufacturing costs, including material costs.

【0014】以上のように、本発明によるICパッケージはチップサイズパッケージとして使用できる。 [0014] As described above, IC package according to the present invention can be used as a chip size package.

【0015】次に、本発明のICパッケージの製造方法について詳細に述べる。 Next, it will be described in detail a manufacturing method of the IC package of the present invention.

【0016】図3(a)は、ICチップがまだ切断されていない段階のウエハ状態を示す図である。 [0016] FIG. 3 (a) is a diagram showing a wafer condition of the stage of IC chip has not yet been cut. ウエハ内には多数のICが存在する。 It is in the wafer a large number of IC exist. 21は半導体基板、22は電極パッド、23は保護膜である。 21 denotes a semiconductor substrate, 22 is an electrode pad, 23 is a protective film. 半導体基板21内には半導体素子が多数形成されている。 Semiconductor elements are formed a large number on the semiconductor substrate 21. 半導体基板21は、 Semiconductor substrate 21,
シリコン(Si)半導体やガリウムひ素などの化合物半導体、あるいは他の半導体である。 Silicon (Si) semiconductor or gallium arsenide compound semiconductors or other semiconductor, such as. 電極パッド22の材料は、アルミニウム(Al)や、アルミニウムの合金や、不純物元素の入ったアルミニウム。 Material of the electrode pad 22, an aluminum (Al) or, or aluminum alloys, containing the impurity elements aluminum. あるいは銅(C Or copper (C
u)や、銅の合金や不純物の入った銅、あるいは他の金属などである。 u) or the like of copper containing a copper alloy or impurity, or other metals. 保護膜23の材料は,シリコン酸化膜(SiO2)やシリコン窒化膜(SiNx)やポリイミド膜、あるいは他の絶縁膜などである。 Material of the protective film 23 is a silicon oxide film (SiO2) or silicon nitride film (SiNx) or a polyimide film or other insulating films.

【0017】次に図3(b)に示すように、ICが多数形成されたウエハ状態のままで、電極パッド22にバンプ24を接着する。 [0017] Then, as shown in FIG. 3 (b), IC are in the original number formed wafer state, bonding the bump 24 on the electrode pads 22.

【0018】図3(c)は、図3(b)の1個の電極パッドを拡大した図である。 [0018] FIG. 3 (c) is an enlarged view of one of the electrode pads of FIG. 3 (b). バンプ24の形状は図3 The shape of the bump 24 is 3
(c)に示すように凸形の形状をするように形成する。 It formed to the shape of the convex, as shown in (c).
ひとつの形成方法として、ワイヤボンダー装置を用いる方法がある。 One of the forming method, there is a method using a wire bonder.

【0019】すなわち図4(a)において、金属線34 [0019] That is, FIG. 4 (a), the metal wire 34
の先をワイヤボンディング装置で丸い金属ボール35を形成する。 The previous to form a round metal balls 35 in a wire bonding apparatus. 次に図4(b)に示すように、金属ボール3 Next, as shown in FIG. 4 (b), metal balls 3
5をICの電極パッド32に押し付け、熱圧着か超音波圧着などの方法により金属ボール35とICの電極パッド32を接着する。 Pressing the 5 to the electrode pads 32 of the IC, by a method such as thermocompression bonding or ultrasonic bonding for bonding the metal ball 35 and the IC electrode pads 32. 次に図4(c)に示すように・金属線34を適当な長さの所で切断する。 Then cutting the-metal wire 34 at the appropriate length, as shown in FIG. 4 (c). 以上の事をウエハレベルで行うのであるが、ウエハサイズで見ればバンプ36の高さはばらつきがあるので全体の高さをそろえるために、図4(c)の工程の後でべベリングという工程を加える事もある。 Although it performed that more than at the wafer level, in order to align the overall height the height of the bump 36 when viewed in the wafer size is uneven, steps of downy Belling after the FIG. 4 (c) step there also be added.

【0020】バンプ34、35の材料として金(A [0020] As the material of the bumps 34 and 35 gold (A
u)、パラジウム(Pd)、アルミニウム(Al)、銀(Ag)、鉛(Pd)と錫(Sn)の半田合金、銀(A u), palladium (Pd), aluminum (Al), silver (Ag), lead (Pd) and a solder alloy of tin (Sn), silver (A
g)と錫(Sn)の合金、その他の金属などがある。 g) an alloy of tin (Sn), and the like other metals.

【0021】次に図3(d)に示すように、保護材料2 [0021] Next, as shown in FIG. 3 (d), the protective material 2
5を付着する。 5 to attach. 図3(e)は、図3(d)の1個の電極部分を拡大した図である。 Figure 3 (e) is an enlarged view of one of the electrode portions of FIG. 3 (d). 保護材料25は液体状の材料で、ウエハ全体に塗布する事ができる。 The protective material 25 is a liquid-like material, it can be applied to the entire wafer. 塗布した時の液体状の厚みは、硬化後の最終的な厚みを考慮して決定しなければならない。 Liquid thickness when coated must be determined by considering the final thickness after curing. すなわちバンプ24の柱部分が充分に露出し、実装する時に実装基板上の配線と接着する程度にバンプ24の柱部分を確保できるように、塗布後の液体状の厚みを調整する。 That post portion of the bump 24 is sufficiently exposed, so that post portion of the bump 24 to the extent of bonding the wiring on the mounting board when mounting can be secured, to adjust the liquid thickness after coating. 塗布した後で適当な温度でべ一クして液体状のものを固形化する。 And base one click a suitable temperature after application to solidify those liquid and. このベーク温度を適度に選ぶことにより材料25は、より安定した保護材料となり、ICを機械的化学的に強化する。 Material 25 by selecting the baking temperature appropriately enhances more becomes stable protective material, the IC mechanically chemically.

【0022】これでウエハの中に多数のICパッケージが完成したわけであるが、次にこれらをひとつひとつ分離する工程について述べる。 [0022] Now although many IC packages in the wafer is not completed will be described next process for each one separating them.

【0023】ウエハ内のスクライブラインに沿ってダイシング装置を用いて切断し、個々のICパッケージに分離する。 [0023] along the scribe line in the wafer is cut by using a dicing apparatus, separated into individual IC packages. これにより個片のICパッケージが形成される。 Thus IC package pieces are formed. 図3ではバンプの柱部分24aの途中に保護材料2 Figure 3 protective material 2 in the middle of the pillar portion 24a of the bump
5が来るようにしたが、図5に示すように、バンプの水平部分より下に保護材料45が来るようにしても良い。 5 but is to come, as shown in FIG. 5, it may be protective material 45 comes below the horizontal portion of the bump.

【0024】 [0024]

【発明の効果】以上、説明したようにウエハ状態でIC According to the present invention above, IC in the wafer state as described
パッケージを作成するので、工程が少なくなり、大幅な費用削減と大幅な納期短縮ができる。 Because to create a package, the process is reduced, it is significant cost savings and significantly shorten delivery times.

【0025】また、凸形バンプを使用し保護材料がバンプの水平部分を覆っているので、信頼性と品質が非常に高い。 Further, since the protective material using convex bumps covers the horizontal part of the bump, a very high reliability and quality.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の半導体装置であるウエハサイズのIC A semiconductor device of the present invention; FIG IC wafer size
パッケージの構造を示す図である。 Is a diagram showing the structure of the package.

【図2】本発明の半導体装置を実装状態を示す図である。 2 is a diagram showing a mounting state of the semiconductor device of the present invention.

【図3】本発明の半導体装置の製造方法を示す図である。 3 is a diagram showing a method of manufacturing a semiconductor device of the present invention.

【図4】本発明の半導体装置に用いるバンプを作成する方法を示す図である。 Is a diagram showing how to create a bump used for a semiconductor device of the present invention; FIG.

【図5】本発明の半導体装置の製造方法の他の実施例である。 Figure 5 is another embodiment of a method of manufacturing a semiconductor device of the present invention.

【符号の説明】 DESCRIPTION OF SYMBOLS

1、11、21、31、41 半導体基板 2、12、22、32、42 電極パッド 3、13、23、33、43 保護膜 4、14、24、36、44 バンプ 5、15、25、45 保護材料 4a,14a,24a,44a バンプの柱部分 1,11,21,31,41 semiconductor substrate 2,12,22,32,42 electrode pads 3,13,23,33,43 protective film 4,14,24,36,44 bump 5,15,25,45 protection material 4a, 14a, 24a, the pillar portion of 44a bump

Claims (5)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 半導体素子が形成されている半導体基板の電極パッドに凸形バンプが接着しており、凸形バンプの水平部分の一部と柱部分が露出し他の部分は保護材料でおおわれている事を特徴とする半導体装置。 [Claim 1] A bonded is convex bump on the electrode pad of the semiconductor substrate on which a semiconductor element is formed, the other part part and the bar portion is exposed in the horizontal part of the convex bump enveloped with a protective material the semiconductor device according to claim that is.
  2. 【請求項2】 凸形バンプ柱部分は保護材料より飛び出している事を特徴とする請求項1記載の半導体装置。 2. A convex bump pillar portion semiconductor device according to claim 1, wherein a that protrudes from the protective material.
  3. 【請求項3】 半導体素子が形成されている半導体基板の電極パッドに凸形バンプが接着しており、凸形バンプの柱部分が露出し他の部分は保護材料でおおわれている事を特徴とする半導体装置。 Wherein and convex bump bonded to the semiconductor substrate electrode pads of the semiconductor element is formed, the other portions exposed post portion of the convex bump and characterized in that is covered with a protective material semiconductor device.
  4. 【請求項4】 半導体素子が形成されている半導体基板の電極パッドに凸形バンプが接着しており、凸形バンプの水平部分の一部と柱部分が露出し他の部分は保護材料でおおわれている半導体装置において、半導体基板の中に半導体素子を形成した後に、半導体素子の電極パッドにバンプを接着する工程と、半導体素子を保護する材料を塗布する工程と、前記保護材料を熱処理する工程を含む事を特徴とする半導体装置の製造方法。 4. has adhesion convex bump on the electrode pad of the semiconductor substrate on which a semiconductor element is formed, the other part part and the bar portion is exposed in the horizontal part of the convex bump enveloped with a protective material in the semiconductor device has, after forming the semiconductor element in a semiconductor substrate, a step of bonding the bumps on the electrode pads of the semiconductor element, a step of applying a material to protect the semiconductor element, the step of heat treating the protective material the method of manufacturing a semiconductor device, which comprises a.
  5. 【請求項5】 凸形バンプはワイヤボンディング装置を用いて形成する事を特徴とする請求項4記載の半導体装置の製造方法。 5. A convex bumps method according to claim 4, wherein it is formed using a wire bonding apparatus.
JP2000006507A 2000-01-14 2000-01-14 Semiconductor device and method of forming the same Granted JP2001196407A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000006507A JP2001196407A (en) 2000-01-14 2000-01-14 Semiconductor device and method of forming the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000006507A JP2001196407A (en) 2000-01-14 2000-01-14 Semiconductor device and method of forming the same
CN 01101509 CN1306300A (en) 2000-01-14 2001-01-13 Semiconductor device and its mfg. method

Publications (1)

Publication Number Publication Date
JP2001196407A true JP2001196407A (en) 2001-07-19

Family

ID=18535025

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000006507A Granted JP2001196407A (en) 2000-01-14 2000-01-14 Semiconductor device and method of forming the same

Country Status (2)

Country Link
JP (1) JP2001196407A (en)
CN (1) CN1306300A (en)

Cited By (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8004370B2 (en) 2006-03-31 2011-08-23 Kyocera Corporation Surface acoustic wave element, surface acoustic wave apparatus, and communication apparatus
US8089163B2 (en) 2002-11-21 2012-01-03 Rohm Co., Ltd. Semiconductor device production method and semiconductor device
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
US8623706B2 (en) 2010-11-15 2014-01-07 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US8728865B2 (en) 2005-12-23 2014-05-20 Tessera, Inc. Microelectronic packages and methods therefor
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8941999B2 (en) 2010-10-19 2015-01-27 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9093435B2 (en) 2011-05-03 2015-07-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9093291B2 (en) 2011-04-21 2015-07-28 Tessera, Inc. Flip-chip, face-up and face-down wirebond combination package
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10290613B2 (en) 2018-06-14 2019-05-14 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100481415C (en) 2004-03-12 2009-04-22 联华电子股份有限公司 Chip packaging member and manufacturing method thereof
CN100578766C (en) * 2006-08-29 2010-01-06 日月光半导体制造股份有限公司 Chip packaging construct and manufacturing method thereof

Cited By (95)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8089163B2 (en) 2002-11-21 2012-01-03 Rohm Co., Ltd. Semiconductor device production method and semiconductor device
US8531020B2 (en) 2004-11-03 2013-09-10 Tessera, Inc. Stacked packaging improvements
US9570416B2 (en) 2004-11-03 2017-02-14 Tessera, Inc. Stacked packaging improvements
US8927337B2 (en) 2004-11-03 2015-01-06 Tessera, Inc. Stacked packaging improvements
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
US9153562B2 (en) 2004-11-03 2015-10-06 Tessera, Inc. Stacked packaging improvements
US9218988B2 (en) 2005-12-23 2015-12-22 Tessera, Inc. Microelectronic packages and methods therefor
US8728865B2 (en) 2005-12-23 2014-05-20 Tessera, Inc. Microelectronic packages and methods therefor
US9984901B2 (en) 2005-12-23 2018-05-29 Tessera, Inc. Method for making a microelectronic assembly having conductive elements
US8004370B2 (en) 2006-03-31 2011-08-23 Kyocera Corporation Surface acoustic wave element, surface acoustic wave apparatus, and communication apparatus
US8907466B2 (en) 2010-07-19 2014-12-09 Tessera, Inc. Stackable molded microelectronic packages
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9570382B2 (en) 2010-07-19 2017-02-14 Tessera, Inc. Stackable molded microelectronic packages
US9553076B2 (en) 2010-07-19 2017-01-24 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
US9123664B2 (en) 2010-07-19 2015-09-01 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US9312239B2 (en) 2010-10-19 2016-04-12 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US8941999B2 (en) 2010-10-19 2015-01-27 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US8659164B2 (en) 2010-11-15 2014-02-25 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8637991B2 (en) 2010-11-15 2014-01-28 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8957527B2 (en) 2010-11-15 2015-02-17 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8623706B2 (en) 2010-11-15 2014-01-07 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US9312244B2 (en) 2011-04-21 2016-04-12 Tessera, Inc. Multiple die stacking for two or more die
US9281266B2 (en) 2011-04-21 2016-03-08 Tessera, Inc. Stacked chip-on-board module with edge connector
US9437579B2 (en) 2011-04-21 2016-09-06 Tessera, Inc. Multiple die face-down stacking for two or more die
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US9806017B2 (en) 2011-04-21 2017-10-31 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US9093291B2 (en) 2011-04-21 2015-07-28 Tessera, Inc. Flip-chip, face-up and face-down wirebond combination package
US9640515B2 (en) 2011-04-21 2017-05-02 Tessera, Inc. Multiple die stacking for two or more die
US9281295B2 (en) 2011-04-21 2016-03-08 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US9735093B2 (en) 2011-04-21 2017-08-15 Tessera, Inc. Stacked chip-on-board module with edge connector
US9093435B2 (en) 2011-05-03 2015-07-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9691731B2 (en) 2011-05-03 2017-06-27 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9105483B2 (en) 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
US9252122B2 (en) 2011-10-17 2016-02-02 Invensas Corporation Package-on-package assembly with wire bond vias
US9041227B2 (en) 2011-10-17 2015-05-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US9761558B2 (en) 2011-10-17 2017-09-12 Invensas Corporation Package-on-package assembly with wire bond vias
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US10170412B2 (en) 2012-05-22 2019-01-01 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9917073B2 (en) 2012-07-31 2018-03-13 Invensas Corporation Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US9615456B2 (en) 2012-12-20 2017-04-04 Invensas Corporation Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9095074B2 (en) 2012-12-20 2015-07-28 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9633979B2 (en) 2013-07-15 2017-04-25 Invensas Corporation Microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9893033B2 (en) 2013-11-12 2018-02-13 Invensas Corporation Off substrate kinking of bond wire
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9837330B2 (en) 2014-01-17 2017-12-05 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9356006B2 (en) 2014-03-31 2016-05-31 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9812433B2 (en) 2014-03-31 2017-11-07 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US10032647B2 (en) 2014-05-29 2018-07-24 Invensas Corporation Low CTE component with wire bond interconnects
US9947641B2 (en) 2014-05-30 2018-04-17 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US10115678B2 (en) 2015-10-12 2018-10-30 Invensas Corporation Wire bond wires for interference shielding
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10290613B2 (en) 2018-06-14 2019-05-14 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate

Also Published As

Publication number Publication date
CN1306300A (en) 2001-08-01

Similar Documents

Publication Publication Date Title
US8759970B2 (en) Semiconductor device having copper interconnect for bonding
KR100500919B1 (en) Resin sealed semiconductor device and method for manufacturing the same
US6043564A (en) Semiconductor device having ball-bonded pads
CN100383938C (en) Semiconductor device and manufacturing method thereof
US6441475B2 (en) Chip scale surface mount package for semiconductor device and process of fabricating the same
KR100541827B1 (en) Chip scale package using large ductile solder balls
US8133761B2 (en) Packaged system of semiconductor chips having a semiconductor interposer
US6545347B2 (en) Enhanced leadless chip carrier
US6511901B1 (en) Metal redistribution layer having solderable pads and wire bondable pads
JP4401181B2 (en) Semiconductor device and manufacturing method thereof
JP2792532B2 (en) Manufacturing method and a semiconductor wafer of a semiconductor device
US6818976B2 (en) Bumped chip carrier package using lead frame
JP3780122B2 (en) A method of manufacturing a semiconductor device
JP3491003B2 (en) Chip size package semiconductor
JP4698826B2 (en) Semiconductor device and manufacturing method thereof
JP4126389B2 (en) A method of manufacturing a semiconductor package
US20040140557A1 (en) Wl-bga for MEMS/MOEMS devices
US4750666A (en) Method of fabricating gold bumps on IC's and power chips
JP3142723B2 (en) Semiconductor device and manufacturing method thereof
US20020164840A1 (en) Method for forming a wafer level package incorporating a multiplicity of elastomeric blocks and package formed
US20060192274A1 (en) Semiconductor package having double layer leadframe
US6700187B2 (en) Semiconductor package and method for manufacturing the same
KR940001149B1 (en) Chip bonding method of semiconductor device
JP4212293B2 (en) A method of manufacturing a semiconductor device
US7508012B2 (en) Electronic component and method for its assembly

Legal Events

Date Code Title Description
RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20040302

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060713

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080714

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080722

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20080919