KR100886100B1 - Semiconductor package and method for manufacturing the same - Google Patents

Semiconductor package and method for manufacturing the same Download PDF

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KR100886100B1
KR100886100B1 KR20070122401A KR20070122401A KR100886100B1 KR 100886100 B1 KR100886100 B1 KR 100886100B1 KR 20070122401 A KR20070122401 A KR 20070122401A KR 20070122401 A KR20070122401 A KR 20070122401A KR 100886100 B1 KR100886100 B1 KR 100886100B1
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substrate
semiconductor package
lead
semiconductor
semiconductor chip
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KR20070122401A
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Korean (ko)
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김기정
김재윤
정윤하
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앰코 테크놀로지 코리아 주식회사
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    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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    • H01L2225/1041Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
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    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/107Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

A semiconductor package and a manufacturing method thereof are provided to increase reliability about electric signal exchange by contacting a top semiconductor package with a bottom semiconductor package using a lead frame made of copper material. A semiconductor package includes a lead frame(300) made of copper material. The lead frame is separated to an independent terminal by grinding or sawing, and is mounted inside a first semiconductor package. A pad(306) of each lead(304) of the lead frame exposed outside is positioned on a top surface of the first semiconductor package. A second semiconductor package is laminated on the top surface of the lead frame.

Description

반도체 패키지 및 그 제조 방법{Semiconductor package and method for manufacturing the same} A semiconductor package and its manufacturing method {Semiconductor package and method for manufacturing the same}

본 발명은 반도체 패키지 및 그 제조 방법에 관한 것으로서, 더욱 상세하게는 리드프레임이 탑재된 하부 반도체 패키지와, 이 하부 반도체 패키지내의 리드프레임을 그라인딩 내지 소잉시켜 외부로 노출시킨 패드에 상부 반도체 패키지를 전기적 접속 가능하게 적층 구성시킨 구조의 적층형 반도체 패키지 및 그 제조 방법에 관한 것이다. The invention electrically to, and more particularly with the lower semiconductor package with a lead frame with an upper semiconductor package to a pad that by grinding to sawing a lead frame exposed to the outside in the lower semiconductor package related to a semiconductor package and a method of manufacturing the same connectable to the laminated configuration of the stacked-layer type semiconductor package having the structure and to a method of manufacturing the same.

잘 알려진 바와 같이, 반도체 패키지는 리드프레임, 인쇄회로기판, 회로필름 등의 기판을 이용하여, 기판의 칩부착 영역에 반도체 칩을 부착하는 칩부착 공정, 반도체 칩과 기판간을 전기적 신호 교환을 위하여 골드 와이어 등으로 연결하는 와이어 본딩 공정, 반도체 칩과 와이어 등을 외부로부터 보호하기 위하여 몰딩 컴파운드 수지로 몰딩하는 몰딩 공정 등을 통하여 제조된다. As is well known, a semiconductor package lead frame, a printed circuit board, a circuit using a substrate such as a film, the chip mounting step, the semiconductor chip and the substrate between attaching a semiconductor chip to a chip attachment area of ​​the substrate to an electrical signal exchange for gold wire bonding process for connecting a wire or the like, the semiconductor chip and the wire or the like to protect it from the outside it is made through such a molding step of molding a resin molding compound.

최근에는 고집적화를 위하여 반도체 패키지를 상하로 신호 교환 가능하게 적 층시킨 적층형 패키지가 개발되고 있으며, 이를 감안하여 슬림형의 다기능 휴대폰, PDA, 디지털카메라, MP3플레이어를 위한 메모리 패키징 형태로서, 일종의 적층형 패키지인 PoP(Package-on-Package) 패키징이 이루어지고 있는 바, 첨부한 도 3은 종래의 PoP 패키지에 대한 일례를 설명하기 위한 개략적인 단면도이다. Recently, as a memory package form for a semiconductor package, and up and down are stacked packages have been developed which enable signal exchange lamination to, in view of this, thin multi-function mobile phone, PDA, digital camera, MP3 player, to a highly integrated, a kind of multi-layer package, PoP (package-on-package) packaging that comprises a bar, attached Fig. 3 is a schematic sectional view for explaining one example of a prior art PoP package.

종래의 PoP 패키지는 하부쪽의 제1반도체 패키지와, 상부쪽의 제2반도체 패키지가 상호 적층된 구조로 되어 있다. Conventional PoP package has a first semiconductor package and the second semiconductor package on the upper side of the lower side is in the cross-laminate structure.

상기 제1반도체 패키지(10)는 제1기판(12) 상에 부착된 제1반도체 칩(13)과, 제1반도체 칩(13)과 제1기판(12)상의 전도성회로패턴간을 연결하는 플립 칩(14)과, 제1기판(12)의 저면에 형성된 볼랜드에 융착되어 제1반도체 칩(13)의 입출력단자가 되는 제1솔더볼(15)과, 상기 제1반도체 칩(13)과 플립 칩(14) 등을 포함하는 제1기판(12)상의 몰딩영역에 몰딩된 제1몰딩수지(16)를 포함하여 구성되어 있다. Connecting the first semiconductor package 10 includes a first substrate on which a first semiconductor chip (13) attached to the bed 12, a first semiconductor chip 13 and the conductive circuit pattern between on the first substrate 12, flip chip 14 and the first substrate 12 is welded to the Borland formed on the bottom the the first input or output terminal a first solder ball (15) of the semiconductor chip 13, of the first semiconductor chip 13 and the It is configured to include a first mold resin 16 molded in the molding area on the first substrate 12 including the flip chip 14 and the like.

이때, 상기 제1기판의 전체 면적중 몰딩영역은 대략 중앙부분이 되고, 이 몰딩영역의 바깥쪽 영역에는 제2반도체 패키지의 적층을 위한 접속단자인 또 다른 전도성 회로패턴이 노출되는 상태가 된다. In this case, the total area of ​​the molding region of the first substrate is a state that is about to be a central portion, the outer region has a second connection terminal of another conductive circuit pattern is exposed for deposition of the semiconductor package of the molded region.

상기 제2반도체 패키지(20)는 제2기판(22) 상에 부착된 제2반도체 칩(23)과, 제2반도체 칩(23)과 제2기판(22)상의 전도성회로패턴간을 연결하는 와이어(24)와, 제2기판(22)의 저면에 형성된 볼랜드에 융착되어 제2반도체 칩(23)의 입출력단자가 되는 제2솔더볼(25)과, 상기 제2반도체 칩(23)과 와이어(24)를 포함하는 제2기판(22)상의 몰딩영역에 몰딩된 제2몰딩수지(26)를 포함하여 구성되어 있다. The second semiconductor package 20 has a second semiconductor chip 23 is adhered to the second substrate 22, the connecting the second semiconductor chip 23 and the conductive circuit pattern between on the second substrate 22 wire 24, and a second is fused to Borland formed on the bottom surface of the second substrate 22, a second solder ball to be an input or output terminals of the semiconductor chip 23 (25) and the second semiconductor chip 23 and wire It is configured to include a second mold resin 26 molded in the molding area on the second substrate 22 including the (24).

따라서, 상기 제1반도체 패키지(10)의 제1기판(12)의 상면에서 바깥쪽 영역 에 노출된 전도성 회로패턴에 상기 제2반도체 패키지(20)의 제2솔더볼(25)을 융착시킴으로써, 제1 및 제2반도체 패키지(10,20)의 적층이 이루어진다. Thus, by fusing the second solder ball (25) of the first semiconductor package 10, the first substrate 12 and the second semiconductor package 20 with the conductive circuit pattern is exposed to the outside area in the upper surface of the, the 1 and 2 is made as a laminate of the semiconductor package (10, 20).

그러나, 종래의 PoP 타입 패키지는 다음과 같은 문제점이 있다. However, the conventional PoP type package has the following problems.

상기 제1반도체 패키지(10)와 제2반도체 패키지(20)의 적층 및 전기적 신호 연결을 위한 수단인 제2솔더볼(25: 범프)의 높이가 적어도 상기 제1기판(12)의 상면과 제2기판(22)의 저면 사이의 간격(H), 즉 제1몰딩수지(16)의 높이보다 커야 하므로, 제2솔더볼(25)의 크기가 과대해지는 문제점이 있다. The first semiconductor package 10 and the second semiconductor package 20 stacked and means of a second solder ball (25: bump) for electrical signal connection to the upper surface of the first substrate 12, at least the height of the second distance between a bottom surface of the substrate (22), (H), i.e. it must be greater than the height of the first molding resin 16, the size of the second solder ball (25) has become over-problems.

상기 제2솔더볼의 크기와 관련된 전기적 접속 기술로 인하여, 전체 패키지에서 차지하는 제2솔더볼의 크기를 줄이기 어려우며, 결국 제1 및 제2패키지간의 간격이 커져 전체 패키지의 두께 증가 및 내구성 저하를 초래하는 문제점이 있다. Due to the electrical connection techniques associated with the size of the second solder ball, it is difficult to reduce the size of the second solder ball in the entire package, after the first and the second problem that the interval between the package results in an increase in thickness of the entire package, and reduced durability increases there is.

특히, 상기 제2솔더볼의 크기가 과대해짐에 따라, 제1반도체 패키지와 제2반도체 패키지를 상호 연결할 때, 제2솔더볼에 대한 변형 문제가 발생할 수 있고, 열적 스트레스(thermal stress) 등과 같은 여러가지 요인으로 인하여 제2솔더볼의 탈락되는 내구성 저하 문제가 발생할 수 있으며, 결국 제1 및 제2반도체 패키지간의 접속 단락 등이 발생되는 문제점이 발생할 수 있다. In particular, a number of factors, such as, first to connect mutually a semiconductor package and a second semiconductor package, and can cause deformation problems for a second solder ball, the thermal stress (thermal stress) according to the over-becomes the size of the second solder ball due to the durability, and can cause degradation of the second solder ball to be dropped, the end may cause a problem in that such a first and a second connection between the semiconductor package shorting.

본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, 그라인딩 또는 소잉에 의하여 독립적인 단자로 분리될 수 있는 리드프레임을 구비하여 하부쪽의 제1반 도체 패키지내에 탑재시키고, 이후 제1반도체 패키지의 상면에 독립적인 단자(패드)로 분리되며 외부로 노출된 리드프레임의 각 리드의 패드에 상부쪽의 제2반도체 패키지를 신호 교환 가능하게 적층 구성되도록 함으로써, 상부 및 하부 반도체 패키지간의 간격을 줄일 수 있고, 구리 재질인 리드프레임을 이용하므로 전기 전도도 및 그 전기적 신호 교환에 대한 신뢰성을 증대시킬 수 있는 반도체 패키지 및 그 제조 방법을 제공하는데 그 목적이 있다. The present invention is one made in view of in view of the points described above, and provided with a lead frame that can be separated into the independent terminals by grinding or sawing and mounted in a first semiconductor package on the lower side, since the first semiconductor package, separated as an independent terminal (pad) on the top surface and to reduce the distance between the upper and lower semiconductor package by making the second semiconductor package on the upper side of the pad of each lead of the lead frame exposed to an outside signal replaceable stacked configuration and, using the copper material of the lead frame, because there is provided the electrical conductivity and the semiconductor package and a manufacturing method thereof that can increase the reliability of the electric signal exchange.

상기한 목적을 달성하기 위한 본 발명의 일 구현예는: In one embodiment of the present invention for achieving the above object comprises:

제1기판 상에 부착된 제1반도체 칩, 상기 제1반도체 칩과 제1기판상의 전도성회로패턴간을 연결하는 플립 칩, 상기 제1반도체 칩과 플립 칩을 포함하는 제1기판상의 몰딩영역에 몰딩된 제1몰딩수지, 상단은 상기 제1몰딩수지의 상면과 평행을 이루며 외부로 노출되고 그 하단은 다운셋되어 상기 제1반도체 칩의 바깥쪽으로 연장되면서 상기 제1기판상의 전도성회로패턴에 접속 연결되는 리드프레임, 상기 제1기판의 저면에 형성된 볼랜드에 융착되어 제1반도체 칩의 입출력단자가 되는 제1솔더볼, 을 포함하는 제1반도체 패키지와; The molding region on the first substrate including a first semiconductor chip, said first semiconductor chip and a flip chip, the first semiconductor chip and flip-chip connecting the conducting circuit pattern between on the first substrate attached to the first substrate a molded first mold resin, the top of the first constitutes the upper surface and parallel to the molding resin is exposed to the outside that the bottom is set down while extending to the outside of the first semiconductor chip connected to the conductive circuit pattern on the first substrate connecting the lead frame to be the first semiconductor package including a first solder ball, it is fused to Borland formed on a lower surface of the first substrate on which an input or output terminal of the first semiconductor die; 제2기판 상에 부착된 제2반도체 칩, 상기 제2반도체 칩과 제2기판상의 전도성회로패턴간을 연결하는 와이어, 상기 제2반도체 칩과 와이어를 포함하는 제2기판상의 몰딩영역에 몰딩된 제2몰딩수지, 를 포함하는 제2반도체 패키지; The molded in the molding area on the second substrate including a second semiconductor chip, a wire for connecting the second semiconductor chip and the conductive circuit pattern between on the second substrate, the second semiconductor chip and the wire attached to the second substrate the second semiconductor package including a second molding resin; 를 적층 구성하되, 외부로 노출된 상기 리드프레임의 상단면과, 상기 제2기판의 저면에 형성된 볼랜드간을 전도성 연결수단으로 연결하여서, 상기 제1 및 제2반도체 패키지가 적층 구성되는 것을 특징으로 하는 반도체 패키지를 제공한다. A shall be composed laminated, hayeoseo top surface of said lead frame exposed to the outside and, connected to Borland cross formed on the bottom surface of the second substrate with a conductive connecting means, characterized in that the first and the second semiconductor package stacked configuration It provides a semiconductor package.

바람직한 구현예로서, 상기 리드프레임은: 내부지지틀과, 이 내부지지틀의 외측 사방 모서리로부터 일체로 연장된 복수의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 구성된 것을 특징으로 한다. In a preferred embodiment, the lead frame comprises: characterized by consisting of an internal support frame, and a plurality of leads and an integrally extending from the outer edge of the four-way inside the support frame, projecting pad formed integrally on the lid.

더욱 바람직한 구현예로서, 상기 리드프레임의 내부지지틀은 그라인딩에 의하여 제거되는 동시에 내부지지틀과 인접한 리드의 상단이 상기 제1몰딩수지의 상면과 평행을 이루며 외부로 노출되고, 리드의 하단은 다운셋되어 상기 제1기판상의 전도성회로패턴에 접속 연결되는 것을 특징으로 한다. More a preferred embodiment, the inner support frame is the top of the lead adjacent to the inner support frame at the same time is removed by the grinding of the lead frame and forms the top surface and parallel to the first molding resin exposed to the outside, the lower end of the lead is down is set is characterized in that the connections connected to the conductive circuit pattern on the first substrate.

바람직한 다른 구현예로서, 상기 리드프레임은: 외부지지틀과, 이 외부지지틀의 내측 사방 모서리로부터 안쪽 방향으로 연장되며 일체로 형성된 복수의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 구성된 것을 특징으로 한다. Preferred as the other embodiments, the lead frame comprises: an external support frame, and this extends inward from the inside all around the edge of the outer support frame that consisting of a plurality of leads, and a protrusion formed in the pad integrally on the lid is formed integrally It characterized.

더욱 바람직한 다른 구현예로서, 상기 리드프레임의 외부지지틀은 소잉에 의하여 제거되는 동시에 외부지지틀과 인접한 리드의 하단은 상기 제1기판상의 전도성회로패턴에 접속 연결되고, 리드의 상단은 상기 제1몰딩수지의 상면과 평행을 이루며 외부노 노출되는 것을 특징으로 한다. More preferred as the other embodiments, the lower end of the outer support frame of the lead frame is a lead adjacent to the outer support frame at the same time is removed by sawing is connected to connected to the conductive circuit pattern on the first substrate, the top of the lid is the first forms the upper surface and parallel to the molding resin is characterized in that no external exposure.

이때, 상기 리드의 상단면에는 외부로 노출되어 상기 전도성 연결수단과 접속되는 패드가 일체로 더 형성된 것을 특징으로 한다. At this time, the top surface of the lead is exposed to the outside characterized in that the pad is connected to the conductive connection means further integrally formed.

바람직하게는, 상기 전도성 연결수단은 솔더볼, 플립 칩, 범프중 선택된 어느 하나인 것을 특징으로 한다. Preferably, the conductive connecting means is characterized in that any selected one of a solder ball, the flip-chip bumps.

상기한 목적을 달성하기 위한 본 발명의 다른 구현예는: Another embodiment of the present invention for achieving the above object comprises:

ⅰ) 하부에 위치되는 제1반도체 패키지 제조 공정과, ⅱ) 상부에 위치되는 제2반도체 패키지 제조 공정과, ⅲ) 상기 제1 및 제2반도체 패키지를 적층하는 공정, 으로 이루어지되, Ⅰ) claim that is located below the first semiconductor package and a manufacturing process, ⅱ) a second semiconductor package manufacturing process and, ⅲ is positioned on top) of the first and second step of laminating a second semiconductor package, jidoe made of,

ⅰ) 상기 제1반도체 패키지 제조 공정은: 제1기판 상에 제1반도체 칩을 부착하고, 상기 제1반도체 칩과 제1기판상의 전도성회로패턴간을 플립 칩으로 전기적 신호 교환 가능하게 연결하는 단계와; Ⅰ) of the first semiconductor package manufacturing process comprising the steps of: first mounting a semiconductor chip, wherein the connection enables exchange electrical signals to the first semiconductor chip and the conductive circuit pattern between on the first substrate in a flip-chip on the first substrate Wow; 내부지지틀과, 이 내부지지틀의 외측 사방 모서리로부터 일체로 연장된 복수의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 이루어진 리드프레임을 구비하여, 각 리드의 하단은 제1기판의 전도성패턴에 연결하는 동시에 리드의 상단 및 내부지지틀을 제1반도체 칩의 테두리 위쪽으로 이격 배치하는 단계와; Inside the support frame, and a and a plurality of leads extending integrally from the outside all around the edge of the inner support frame, and comprising a lead frame made of a protrusion formed pad integrally on the lid, the bottom of each lead is the conductivity of the first substrate at the same time to connect to the pattern disposing space the top and the inner support framework of the lid to the top border of the first semiconductor die; 상기 제1반도체 칩과, 플립 칩과, 리드프레임을 내재시키면서 상기 제1기판상의 몰딩영역을 수지로 몰딩하여 제1몰딩수지층을 형성하는 단계와; While underlying the first semiconductor chip and a flip chip and a lead frame comprising the steps of: forming a first number of the molding resin by molding the molding area on the first substrate with a resin; 상기 제1몰딩수지의 상면을 그라인딩 수단으로 그라인딩하되, 그 안쪽의 내부지지틀까지 그라인딩하여, 내부지지틀의 제거와 함께 각 리드가 독립적인 리드로 분리되면서 그 패드가 외부로 노출되는 단계; Phase is grinding, but the upper surface of the first molding resin into the grinding means, and grinding the interior of the support frame in its inside, as each lead is separated by independent lead with the removal of the inner support frame is that the pad exposed to the outside; 로 이루어지고, It is made of,

ⅱ) 상기 제2반도체 패키지 제조 공정은: 제2기판 상에 제2반도체 칩을 부착하고, 상기 제2반도체 칩과 제2기판상의 전도성회로패턴간을 와이어로 연결하는 단계와; Ⅱ) and the second semiconductor package manufacturing process comprising the steps of: connecting a second mounting the semiconductor chip and the second semiconductor chip and a conductive circuit pattern on the second substrate between the second substrate and the wire; 상기 제2반도체 칩과 와이어를 포함하는 제2기판상의 몰딩영역을 수지로 몰딩하여 제2몰딩수지층을 형성하는 단계; Forming a second number of the molding resin by molding the molding area on the second substrate including a second semiconductor chip and the wire of a resin; 로 이루어지며, It consists of,

ⅲ) 상기 제1 및 제2반도체 패키지를 적층하는 공정은: 그라인딩에 의하여 외부로 노출된 상기 리드프레임의 각 리드의 패드와, 상기 제2기판의 저면에 형성된 볼랜드간을 전도성 연결수단으로 연결하여 이루어지는 것을 특징으로 하는 반도체 패키지 제조 방법을 제공한다. By connecting the pads of each lead of the lead frame exposed by grinding the outside, Borland cross formed on the bottom surface of the second substrate with a conductive connecting means: ⅲ) the first and second step of stacking a semiconductor package, It provides a method for producing a semiconductor package which comprises.

상기한 목적을 달성하기 위한 본 발명의 또 다른 구현예는: Yet another embodiment of the present invention for achieving the above object comprises:

ⅰ) 하부에 위치되는 제1반도체 패키지 제조 공정과, ⅱ) 상부에 적층되는 제2반도체 패키지 제조 공정과, ⅲ) 상기 제1 및 제2반도체 패키지를 전기적 신호교환 가능하게 적층하는 공정, 으로 이루어지되, Ⅰ) a first semiconductor package manufacturing process which is located at the lower and, ⅱ) a second semiconductor package-producing laminated on the upper step and, ⅲ) process, which enables the exchange electrical signals stacking the first and second semiconductor package, composed of jidoe,

ⅰ) 상기 제1반도체 패키지 제조 공정은: 제1기판 상에 제1반도체 칩을 부착하고, 상기 제1반도체 칩과 제1기판상의 전도성회로패턴간을 플립 칩으로 전기적 신호 교환 가능하게 연결하는 단계와; Ⅰ) of the first semiconductor package manufacturing process comprising the steps of: first mounting a semiconductor chip, wherein the connection enables exchange electrical signals to the first semiconductor chip and the conductive circuit pattern between on the first substrate in a flip-chip on the first substrate Wow; 외부지지틀과, 이 외부지지틀의 내측 사방 모서리로부터 안쪽 방향으로 연장되며 일체로 형성된 복수의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 이루어진 리드프레임을 구비하는 단계와; The outer support frame, and the four-way extending inwardly from the inner edge of the outer support frame comprising: a lead frame having leads and including a plurality of protruding pad formed integrally on the lid formed integrally with; 상기 리드프레임의 외부지지틀은 제1기판의 끝단 상면상에 지지시키고, 외부지지틀과 인접한 각 리드의 하단은 제1기판의 전도성패턴에 연결시키며, 각 리드의 상단은 제1반도체 칩의 테두리 위쪽으로 이격 배치하는 단계와; The outer support frame of the lead frame and the support at the end upper face of the first substrate, the outer supporting frame and adjacent the lower end of each lead is sikimyeo connected to the conductive pattern of the first substrate, the top of each lead is the border of the first semiconductor chip, comprising: spaced upwardly and; 상기 제1반도체 칩과, 플립 칩과, 리드프레임을 내재시키면서 상기 제1기판상의 몰딩영역을 수지로 몰딩하여 제1몰딩수지층을 형성하는 단계와; While underlying the first semiconductor chip and a flip chip and a lead frame comprising the steps of: forming a first number of the molding resin by molding the molding area on the first substrate with a resin; 상기 제1몰딩수지의 상면을 그라인딩 수단으로 그라인딩하되, 그 내부의 존재하는 리드의 패드가 노출될 때까지 그라인딩하는 단계와; The step of grinding, but the upper surface of the first molding resin into the grinding means, the grinding to the pad of the lead to the presence therein of the exposed and; 상기 제1몰딩수지의 테두리단 및 상기 제1기판의 테두리단을 소잉하는 동시에 상기 기판의 끝단에 지지된 상기 리드프레임의 외부지지틀도 함께 소잉으로 제거되 어, 각 리드가 독립적인 리드로 분리되는 단계; Wherein the rim end of first molding resin, and wherein the separation in the at the same time for sawing the rim end of first substrate of the outer support frame also each lead being poured, remove sawing with the lead frame supporting the edge of the substrate independent of the lead steps; 로 이루어지고, It is made of,

ⅱ) 상기 제2반도체 패키지 제조 공정은: 제2기판 상에 제2반도체 칩을 부착하고, 상기 제2반도체 칩과 제2기판상의 전도성회로패턴간을 와이어로 연결하는 단계와; Ⅱ) and the second semiconductor package manufacturing process comprising the steps of: connecting a second mounting the semiconductor chip and the second semiconductor chip and a conductive circuit pattern on the second substrate between the second substrate and the wire; 상기 제2반도체 칩과 와이어를 포함하는 제2기판상의 몰딩영역을 수지로 몰딩하여 제2몰딩수지층을 형성하는 단계; Forming a second number of the molding resin by molding the molding area on the second substrate including a second semiconductor chip and the wire of a resin; 로 이루어지며, It consists of,

ⅲ) 상기 제1 및 제2반도체 패키지를 적층하는 공정은: 그라인딩에 의하여 외부로 노출된 상기 리드프레임의 각 리드의 패드와, 상기 제2기판의 저면에 형성된 볼랜드간을 전도성 연결수단으로 연결하여 이루어지는 것을 특징으로 하는 반도체 패키지 제조 방법을 제공한다. By connecting the pads of each lead of the lead frame exposed by grinding the outside, Borland cross formed on the bottom surface of the second substrate with a conductive connecting means: ⅲ) the first and second step of stacking a semiconductor package, It provides a method for producing a semiconductor package which comprises.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공할 수 있다. Through the above problem solving means, the present invention can provide the following effects.

그라인딩 또는 소잉에 의하여 독립적인 단자로 분리될 수 있는 리드프레임을 구비하여 하부쪽의 제1반도체 패키지내에 탑재시키고, 이후 리드프레임의 상단이 제1반도체 패키지의 상면에 독립적인 단자(패드)로 분리되며 외부로 노출되도록 한 다음, 리드프레임의 각 리드의 패드에 상부쪽의 제2반도체 패키지를 신호 교환 가능하게 적층 구성되도록 함으로써, 상부 및 하부 반도체 패키지간의 간격을 줄일 수 있고, 전체적으로 두께를 줄일 수 있는 적층형 패키지를 제공할 수 있다. By grinding or sawing by comprising a lead frame that can be separated into the independent terminals and mounted in a first semiconductor package on the lower side, the upper end of the lead frame split into independent terminals (pads) on an upper surface of the first semiconductor package after and can be reduced and then, the distance between the upper and lower semiconductor package by making the second semiconductor package, the signal replaceable stacked configuration of the upper side of the pad of each lead of the lead frame so as to be exposed to the outside, as a whole to reduce the thickness which can provide a stacked package.

또한, 상부 및 하부 반도체 패키지를 전기 전도도가 우수한 구리 재질의 리 드프레임을 이용하여 접속되도록 함으로써, 전기 전도도 및 그 전기적 신호 교환에 대한 신뢰성을 증대시킬 수 있다. Further, by the upper and lower semiconductor packages so as to be connected with the frame of de Lee copper material has excellent electric conductivity, it is possible to increase the reliability of the electrical conductivity, and exchange the electrical signals.

또한, 종래에는 하부쪽 패키지의 몰딩수지 높이 이상의 크기를 갖는 과도한 크기의 솔더볼 내지 범프를 이용하여 상부 및 하부 패키지를 적층 연결하였지만, 이에 반하여, 본 발명은 하부의 제1반도체 패키지의 상면과, 상부의 제2반도체 패키지의 저면이 평평한 형태로 배열되므로, 종래의 몰딩수지의 높이에 따른 갑섭 현상없이 아주 작은 솔더볼 내지 범프 등을 이용하여 상하 패키지를 신호 교환 가능하게 적층할 수 있게 되어, 보다 안정적인 적층형 패키지를 제공할 수 있다. Further, in the prior art, by using a solder ball to bump the excessive size with a molding resin having a height greater than the size of the lower side of the package but stacked connecting the upper and lower packages, on the contrary, the invention is a first upper surface of the semiconductor package and the top of the lower the second since the bottom surface of the semiconductor package arranged in a flat shape, using a gapseop very small solder balls to the bumps without phenomena according to the height of a conventional molding resin to be able to stack enabling the upper and lower package exchange signal, and more reliable multi-layer It can provide a package.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다. Hereinafter in detail with reference to the accompanying drawings a preferred embodiment of the present invention will be described.

본 발명은 상부 및 하부 패키지가 상하로 적층된 형태의 반도체 패키지를 제공하고자 한 것으로서, 상부 및 하부 패키지의 전기적 신호 연결을 리드프레임을 이용한 점, 그리고 리드프레임을 그라인딩 또는 소잉에 의하여 독립적인 단자로 분리시킨 점 등에 주안점이 있다. The present invention is a to provide a semiconductor package of which the upper and lower package stacked up and down type, a point, and an independent terminal by a lead frame for grinding or sawing using a lead frame for electrical signal connection of the upper and lower package there is the point or the like that was separated.

이를 위한, 본 발명에 따른 반도체 패키지 및 그 제조 방법에 대한 제1실시예를 설명하면 다음과 같다. Turning to the first embodiment of a semiconductor package and a manufacturing method therefor according to the present invention as follows.

[제1실시예] [First Embodiment]

첨부한 도 1은 본 발명에 따른 반도체 패키지 및 그 제조 방법의 제1실시예 를 순서대로 설명하는 단면도이다. The attached Figure 1 is a cross-sectional view illustrating a first embodiment of a semiconductor package and a method of manufacturing the same according to the present invention in order.

본 발명의 제1실시예에 따른 반도체 패키지는 하부에 위치되는 제1반도체 패키지 제조 공정과, 상부에 적층되는 제2반도체 패키지 제조 공정과, 상기 제1 및 제2반도체 패키지를 전기적 신호 교환 가능하게 적층하는 공정으로 이루어진다. The semiconductor package according to a first embodiment of the present invention to the first semiconductor package manufacturing process and the manufacturing to be laminated to the upper second semiconductor packages step, the first and the second semiconductor package, which is located at the lower interchangeable electrical signal It formed of a lamination process.

제1반도체 패키지 제조 공정 The first semiconductor package manufacturing process

먼저, 제1기판(102)의 중앙부 영역에 구획된 칩 부착영역에 제1반도체 칩(104)을 부착하고, 이어서 상기 제1반도체 칩(104)의 저면에 형성된 복수의 본딩패드와, 상기 제1기판(102)상에서 칩 부착영역의 바깥쪽에 노출되어 있는 전도성회로패턴간을 플립 칩(106)을 매개로 하여 전기적 신호 교환 가능하게 연결한다. First, attaching a first semiconductor chip 104 on the chip mounting region defined at the center area of ​​the substrate 102, and then the first and the plurality of bonding pads formed on a lower surface of the first semiconductor chip 104, 1 by the conductive circuit pattern is exposed on the outside of the liver of the chip mounting area on the substrate 102, the flip chip 106 is connected to the medium to enable exchange electrical signals.

다음으로, 상기 제1기판(102)에 상하로 적층되는 패키지의 전기적 접속을 위한 연결수단이 되는 리드프레임(300)을 안착시킨다. Next, the mounting a lead frame 300 that is the connection means for the electrical connection of the package to be stacked vertically on the first substrate (102).

상기 리드프레임(300)은 도 1의 우측에 나타낸 평면도에서 보는 바와 같이, 사각틀 형상의 내부지지틀(302)과, 이 내부지지틀(302)의 외측 사방 모서리로부터 외측방향으로 연장되며 일체로 복수의 리드(304)로 구성되고, 특히 상기 각 리드(304)상에는 보다 넓은 면적을 갖는 패드(306)가 일체로 돌출 형성된다. As it can be seen the lead frame 300 in the plan view shown on the right side of Figure 1, and extends in a lateral direction from the outside all around the corners of the rectangular frame shape inside the support frame 302 and, the inner support frame 302, a plurality integrally of it is composed of the leads 304, specifically, the pad 306 having a large area than that formed on each of the leads 304 are formed to project integrally.

또한, 상기 내부지지틀(302)로부터 연장되는 각 리드(304)는 밑쪽으로 다운셋(down-set)되며 연장된다. Each of the leads 304 extending from the inner support frame 302 is extended and set (set-down) down towards the bottom.

이에, 상기 리드프레임(300)의 각 리드(304)의 하단은 제1기판(102)의 전도성회로패턴에 연결하는 동시에 각 리드(304)의 상단 및 내부지지틀(302)은 상기 제1반도체 칩(104)의 테두리 위쪽으로 이격 배치시킨다. Thus, the bottom is the top and the inner support frame in the same time to connect the conductive circuit pattern on the first substrate 102, each lead 304, 302 of each lead 304 of the lead frame 300 is the first semiconductor thereby arranged spaced apart in the top border of the chip (104).

다음으로, 몰딩 단계로서 상기 제1반도체 칩(104)과, 플립 칩(106)과, 리드프레임(300)을 내재시키면서 상기 제1기판(102)상에 구획된 몰딩영역이 수지로 몰딩되어, 제1몰딩수지(108)층이 형성된다. Is Next, the molding as the molding step, the first semiconductor chip 104, while underlying the flip-chip 106 and the lead frame 300, the molding region defined on the first substrate 102. The resin, the molding resin of claim 1 (108) layer is formed.

이 몰딩 단계후, 상기 리드프레임(300)은 제1몰딩수지(108)층의 내부에 존재하는 상태가 된다. After the molding step, the lead frame 300 is the state that exists in the interior of the first mold resin layer (108).

이어서, 상기 제1몰딩수지(108)의 상면을 그라인딩 수단을 이용하여 그라인딩하되, 그 안쪽의 내재된 내부지지틀(302)까지 그라인딩하여, 리드프레임(300)의 내부지지틀(302)이 제거되도록 함으로써, 내부지지틀(302)에 의하여 하나로 연결되어 있던 각 리드(304)들은 독립적인 리드로 분리된다. Then, the first, but the upper surface of the mold resin 108, the grinding using a grinding means, the grinding to the inner support frame (302) embedded in the inside, the inner support frame (302) is removed, the lead frame 300, by ensuring that, inside the support frame, each lead 304 which is connected by 302 to one are separated by independent lead.

특히, 그라인딩은 상기 내부지지틀(302)의 제거와 함께 각 리드(304)의 패드(306)가 외부로 노출될때까지 진행되며, 외부로 노출된 각 리드(304)의 패드(306)는 상부 패키지를 적층함에 있어 실질적인 전기적 연결점 역할을 하게 된다. In particular, grinding the pad 306 of the inner support frame 302, each of the leads 304 with a pad 306 of each of the leads 304 with the removal is conducted until exposed to the outside, exposed to the outside of the upper it as a laminated package is a substantial electrical contact point role.

이상과 같은 단계로 제1실시예에 따른 제1반도체 패키지(100)가 완성된다. The first semiconductor package 100 according to the first embodiment is completed by the above steps.

제2반도체 패키지 제조 공정 The second semiconductor package manufacturing process

제2기판(202) 상의 중앙부 영역에 구획된 칩 부착영역에 제2반도체 칩(204)을 부착하고, 상기 제2반도체 칩(204)의 상면에 형성된 복수의 본딩패드와 상기 제2기판(202)상에서 제2반도체 칩(204)의 바깥쪽에 노출되어 있는 전도성회로패턴간을 와이어(206)로 연결한다. The said second plurality of bonding pads and the second substrate (202 formed on the upper surface of the semiconductor chip 204, a second attaching the semiconductor chip 204 on the chip mounting region defined at the center region on the second substrate 202, and ) a second exposed on the outside of the semiconductor chip 204, a conductive circuit pattern on the liver, which is connected to the wire 206.

이어서, 상기 제2반도체 칩(204)과 와이어(206) 등을 포함하는 제2기판(202) 상의 몰딩영역을 수지로 몰딩하여 제2몰딩수지(208)층을 형성함으로써, 상부 패키지로 적층되어질 제2반도체 패키지(200)가 완성된다. Then, by forming the second semiconductor chip 204 and the wires 206, such as a second molding resin 208 layer by molding the molding area of ​​a resin on the substrate 202, including, be laminated to the upper package the second semiconductor package 200 is completed.

제1 및 제2반도체 패키지를 적층하는 공정 A first and a step of laminating a second semiconductor package,

상기와 같이, 그라인딩에 의하여 외부로 노출된 상기 제1반도체 패키지(100)의 각 리드(304)의 패드(306)와, 상기 제2반도체 패키지(200)의 제2기판(202)의 저면에 형성된 볼랜드간을 전도성 연결수단(308), 예를들어 솔더볼, 플립 칩, 범프중 선택된 어느 하나를 매개로 하여 서로 전기적 신호 교환 가능하게 연결함으로써, 제1반도체 패키지(100)의 위에 제2반도체 패키지(200)가 적층된 적층형 패키지로 완성된다. The bottom surface of the second substrate 202 with the as described above, the pads 306 of each lead 304 of the by grinding exposed to the outside of the first semiconductor package 100, the second semiconductor package 200 a second semiconductor package, the Borland cross formed on the conductive connection means 308, such as solder balls, flip-chip, by the any selected one of a bump-mediated connection enables exchange electrical signals with each other, the first semiconductor package 100 is completed in the multi-layer package 200 is stacked.

이와 같이, 종래에 과도한 크기를 갖는 솔더볼을 매개로 패키지를 적층 연결하는 것과 달리, 본 발명은 제1반도체 패키지내에 내재시킨 리드프레임을 매개로 제2반도체 패키지를 적층 연결함으로써, 전체 패키지의 안정성을 제공함과 더불어 상부 및 하부 반도체 패키지간의 간격을 줄일 수 있고, 전기 전도도가 우수한 구리 재질의 리드프레임을 이용하므로 전기적 신호 교환에 대한 신뢰성을 향상시킬 수 있다. In this way, as opposed to connecting the laminated packages a solder ball as a medium with an excess size to the prior art, the present invention is connected to stack a second semiconductor package, as a medium for which the lead frame embedded in the first semiconductor package, the stability of the entire package in addition to providing it is possible to reduce the distance between the upper and lower semiconductor packages, since the use of a lead frame of copper material excellent electrical conductivity can enhance the reliability of the electrical signal exchange.

여기서, 본 발명에 따른 반도체 패키지 및 그 제조 방법에 대한 제2실시예를 설명하면 다음과 같다. Here will be described a second embodiment of a semiconductor package and a manufacturing method according to the present invention.

[제2실시예] [Second Embodiment]

첨부한 도 2은 본 발명에 따른 반도체 패키지 및 그 제조 방법의 제2실시예를 순서대로 설명하는 단면도이다. The attached Figure 2 is a cross-sectional view illustrating a second embodiment of a semiconductor package and a method of manufacturing the same according to the present invention in order.

본 발명의 제2실시예에 따른 반도체 패키지도 하부에 위치되는 제1반도체 패키지 제조 공정과, 상부에 적층되는 제2반도체 패키지 제조 공정과, 상기 제1 및 제2반도체 패키지를 전기적 신호 교환 가능하게 적층하는 공정으로 이루어진다. Enabling the second embodiment the first semiconductor package manufacturing process, and a second semiconductor package manufacturing process to be laminated on the upper and exchange electrical signals to the first and second semiconductor packages are also located below the semiconductor package according to an example of the invention It formed of a lamination process.

제1반도체 패키지 제조 공정 The first semiconductor package manufacturing process

먼저, 제1기판(102)의 중앙부 영역에 구획된 칩 부착영역에 제1반도체 칩(104)을 부착하고, 이어서 상기 제1반도체 칩(104)의 저면에 형성된 복수의 본딩패드와, 상기 제1기판(102)상에서 칩 부착영역의 바깥쪽에 노출되어 있는 전도성회로패턴간을 플립 칩(106)을 매개로 하여 전기적 신호 교환 가능하게 연결한다. First, attaching a first semiconductor chip 104 on the chip mounting region defined at the center area of ​​the substrate 102, and then the first and the plurality of bonding pads formed on a lower surface of the first semiconductor chip 104, 1 by the conductive circuit pattern is exposed on the outside of the liver of the chip mounting area on the substrate 102, the flip chip 106 is connected to the medium to enable exchange electrical signals.

다음으로, 상기 제1기판(102)에 상하로 적층되는 패키지의 전기적 접속을 위한 연결수단이 되는 리드프레임(400)을 안착시킨다. Next, the mounting a lead frame 400 that is connected to the means for electrical connection of the package to be stacked vertically on the first substrate (102).

제2실시예에 따른 리드프레임(400)은 도 2의 우측에 도시된 평면도에서 보는 바와 같이, 사각틀 형상의 외부지지틀(402)과, 이 외부지지틀(402)의 내측 사방 모서리로부터 안쪽 방향으로 연장되며 일체로 형성된 복수의 리드(404)로 구성되고, 마찬가지로 각 리드(404)상에 보다 큰 면적을 갖는 패드(406)가 일체로 형성된다. Second embodiment, the inside from the inside all around the edge of the outer support frame 402 and the outer support frame 402 of a rectangular frame-like direction, as for example, a lead frame 400 according to the is shown in the plan view shown on the right side of Figure 2 extends in and is configured integrally with a plurality of leads 404 formed of, as each lead 404, the pad 406 has a larger surface area on the formed integrally.

또한, 상기 외부지지틀(402)로부터 연장되는 각 리드(404)는 위쪽으로 다운셋(down-set)되며 연장된다. In addition, each lead 404 extending from the outer support frame 402 is extended and set (set-down) to the top-down.

이에, 상기 리드프레임(400)의 외부지지틀(402)은 상기 제1기판(102)의 끝단 상면상에 안착시키고, 외부지지틀(402)과 평행하게 인접한 각 리드(404)의 하단은 상기 제1기판(102)의 전도성회로패턴에 전기적 접속 가능하게 연결시키며, 또한 각 리드(404)의 상단은 상기 제1반도체 칩(104)의 테두리 위쪽으로 이격 배치시킨다. Thus, the bottom of the lead frame 400, the outer support frame 402 has the first substrate 102, each lead 404 is secured to the end of the upper face and the adjacent parallel to the outer support frame (402) of the said the sikimyeo electrical connection can be connected to the conductive circuit pattern on the first substrate 102, and also the top of each lead 404 is spaced apart by the top border of the first semiconductor chip (104).

다음으로, 몰딩 단계로서 상기 제1반도체 칩(104)과, 플립 칩(106)과, 리드프레임(400)을 내재시키면서 상기 제1기판(102)상에 구획된 몰딩영역이 수지로 몰딩되어, 제1몰딩수지(108)층이 형성되며, 이 몰딩 단계후 리드프레임(400)은 제1몰딩수지(108)의 내부에 존재하는 상태가 된다. Is Next, the molding as the molding step, the first semiconductor chip 104, while underlying the flip-chip 106 and the lead frame 400, the molding region defined on the first substrate 102, a resin, a first mold resin (108) layer is formed, the lead frame 400 after the molding step is a condition that exists inside of a first molding resin 108.

이어서, 상기 제1몰딩수지(108)의 상면을 그라인딩 수단으로 그라인딩하되, 그 내부의 존재하는 각 리드(404)의 패드가 노출될 때까지 그라인딩함으로써, 제1반도체 패키지(100)의 상면 즉, 제1몰딩수지(108)의 상면에 각 리드(404)의 패드(406)가 노출되는 상태가 된다. Then, the upper surface of the first, but grinding the top surface of the molded resin 108 in the grinding means, by grinding until the pads of the lead 404 to the internal presence of the exposed first semiconductor package 100, that is, claim 1 is the state in which an exposed pad (406) of each lead 404, the upper surface of the molding resin 108.

연이어, 상기 리드프레임(400)의 각 리드(404)를 독립적인 리드로 분리하기 위한 소잉(sawing) 단계가 진행되는 바, 상기 제1몰딩수지(108)의 테두리단 및 상기 제1기판(102)의 테두리단을 동시에 소잉함으로써, 그 안쪽에 내재되어 있던 상기 리드프레임(400)의 외부지지틀(402)도 함께 소잉으로 제거되어, 각 리드(404)가 독립적인 리드로 분리되어진다. Subsequently, the border-stage and the first substrate (102 of sawing bar, which is (sawing) step is in progress the first molded resin 108 for the separation of each lead 404 of the leadframe 400 by independent lead ) by sawing the rim end of the same time, the outer support frame 402 of the lead frame 400 which has been embedded in the inside is also included removing the sawing, it is the respective leads 404 are separated as independent leads.

이상과 같은 단계로 제2실시예에 따른 제1반도체 패키지(100)가 완성된다. The first semiconductor package 100 according to the second embodiment is thus completed by the above steps.

제2반도체 패키지 제조 공정 The second semiconductor package manufacturing process

제2실시예에 따른 제2반도체 패키지(200) 제조 공정은 제1실시예와 마찬가지로, 제2기판(202) 상에 칩 부착영역에 제2반도체 칩(204)을 부착하고, 상기 제2반도체 칩(204)의 상면에 형성된 각 본딩패드와 상기 제2기판(202)상의 전도성회로패턴간을 와이어(206)로 연결하며, 상기 제2반도체 칩(204)과 와이어(206) 등을 포함하는 제2기판(202)상의 몰딩영역을 수지로 몰딩하여 제2몰딩수지(208)층을 형성함 으로써, 제2반도체 패키지(200)로 완성된다. The second embodiment The second semiconductor package 200, the manufacturing process according to the example is similar to the first embodiment, the second attachment to the semiconductor chip 204 to chip attach region on a second substrate 202, and the second semiconductor and the second substrate 202, a conductive circuit pattern between on and each of the bonding pads formed on the upper surface of the chip 204 is connected to a wire 206, that includes the second semiconductor chip 204 and the wires 206, such as as the box by molding the molding area on the second substrate 202 with a resin to form a second mold resin 208 layers, it is completed in a second semiconductor package 200.

제1 및 제2반도체 패키지를 적층하는 공정 A first and a step of laminating a second semiconductor package,

소잉에 의하여 독립적인 리드가 되면서, 그라인딩에 의하여 외부로 노출된 각 리드(404)의 패드(406)와, 상기 제2기판(202)의 저면에 형성된 볼랜드간을 전도성 연결수단(408) 예를들어 솔더볼, 플립 칩, 범프중 선택된 어느 하나를 매개로 하여 서로 전기적 신호 교환 가능하게 연결함으로써, 제1반도체 패키지(100)의 위에 제2반도체 패키지(200)가 적층된 적층형 패키지로 완성된다. As an independent lead by sawing, and the pads 406 of each lead 404 is exposed by grinding the outside, the first to Borland cross formed on the bottom surface of the second substrate 202, the conductive connecting means 408, for example, g., by a solder ball, a flip-chip connection enables the exchange electrical signals with each other to any selected one of a bump in the medium of claim 1 is completed in which the second semiconductor package 200 on the semiconductor package 100 stacked multi-layer package.

이와 같이, 제2실시예에 따른 반도체 패키지도 제1실시예의 리드프레임과 그 구조만 다를 뿐, 제1반도체 패키지내에 내재시킨 리드프레임을 매개로 제2반도체 패키지를 적층 연결함으로써, 전체 패키지의 안정성을 제공함과 더불어 상부 및 하부 반도체 패키지간의 간격을 줄일 수 있고, 전기 전도도가 우수한 구리 재질의 리드프레임을 이용하므로 전기적 신호 교환에 대한 신뢰성을 향상시킬 수 있다. In this way, the second embodiment as the semiconductor package according to the example diagram of a first embodiment of a lead frame and differ only in their structure, first by laminating connecting the second semiconductor package in the which the lead frame embedded parameters in a semiconductor package, the stability of the entire package in addition to providing a can reduce the distance between the upper and lower semiconductor packages, since the use of a lead frame of copper material excellent electrical conductivity can enhance the reliability of the electrical signal exchange.

도 1은 본 발명에 따른 반도체 패키지 및 그 제조 방법의 제1실시예를 순서대로 설명하는 단면도, Figure 1 is a cross-sectional view illustrating a first embodiment of a semiconductor package and a manufacturing method according to the invention in order,

도 2는 본 발명에 따른 반도체 패키지 및 그 제조 방법의 제2실시예를 순서대로 설명하는 단면도, Figure 2 is a cross section illustrating, as a second embodiment of a semiconductor package and a manufacturing method according to the invention in order,

도 3은 종래의 PoP 패키지에 대한 일례를 설명하는 개략적 단면도. Figure 3 is a schematic cross-sectional view illustrating an example of a prior art PoP package.

<도면의 주요 부분에 대한 부호의 설명> <Description of the Related Art>

100 : 제1반도체 패키지 102 : 제1기판 100: a first semiconductor package 102: first substrate

104 : 제1반도체 칩 106 : 플립 칩 104: first semiconductor chip, 106: flip-chip

108 : 제1몰딩수지 200 : 제2반도체 패키지 108: a first molding resin 200: a second semiconductor package,

202 : 제2기판 204 : 제2반도체 칩 202: The second substrate 204: second semiconductor chip,

206 : 와이어 208 : 제2몰딩수지 206: wire 208: second molding resin

300 : 리드프레임 302 : 내부지지틀 300: lead frames 302: inner support frame

304 : 리드 306 : 패드 304: reed 306: pad

308 : 전도성 연결수단 400 : 리드프레임 308: conductive connecting means 400: the lead frame

402 : 외부지지틀 404 : 리드 402: an external support frame 404: lead

406 : 패드 408 : 전도성 연결수단 406: pad, 408: conductive connecting means

Claims (9)

  1. 제1기판 상에 부착된 제1반도체 칩, 상기 제1반도체 칩과 제1기판상의 전도성회로패턴간을 연결하는 플립 칩, 상기 제1반도체 칩과 플립 칩을 포함하는 제1기판상의 몰딩영역에 몰딩된 제1몰딩수지, 상단은 상기 제1몰딩수지의 상면과 평행을 이루며 외부로 노출되고 그 하단은 다운셋되어 상기 제1반도체 칩의 바깥쪽으로 연장되면서 상기 제1기판상의 전도성회로패턴에 접속 연결되는 리드프레임, 상기 제1기판의 저면에 형성된 볼랜드에 융착되어 제1반도체 칩의 입출력단자가 되는 제1솔더볼, 을 포함하는 제1반도체 패키지와; The molding region on the first substrate including a first semiconductor chip, said first semiconductor chip and a flip chip, the first semiconductor chip and flip-chip connecting the conducting circuit pattern between on the first substrate attached to the first substrate a molded first mold resin, the top of the first constitutes the upper surface and parallel to the molding resin is exposed to the outside that the bottom is set down while extending to the outside of the first semiconductor chip connected to the conductive circuit pattern on the first substrate connecting the lead frame to be the first semiconductor package including a first solder ball, it is fused to Borland formed on a lower surface of the first substrate on which an input or output terminal of the first semiconductor die;
    제2기판 상에 부착된 제2반도체 칩, 상기 제2반도체 칩과 제2기판상의 전도성회로패턴간을 연결하는 와이어, 상기 제2반도체 칩과 와이어를 포함하는 제2기판상의 몰딩영역에 몰딩된 제2몰딩수지, 를 포함하는 제2반도체 패키지; The molded in the molding area on the second substrate including a second semiconductor chip, a wire for connecting the second semiconductor chip and the conductive circuit pattern between on the second substrate, the second semiconductor chip and the wire attached to the second substrate the second semiconductor package including a second molding resin;
    를 적층 구성하되, But a multilayer configuration,
    외부로 노출된 상기 리드프레임의 상단면과, 상기 제2기판의 저면에 형성된 볼랜드간을 전도성 연결수단으로 연결하여서, 상기 제1 및 제2반도체 패키지가 적층 구성된 것을 특징으로 하는 반도체 패키지. The top surface of said lead frame exposed to the outside and, hayeoseo connection between the Borland formed on a lower surface of the second substrate with a conductive connection means, the semiconductor package characterized in that the first and the second semiconductor package of stacked.
  2. 청구항 1에 있어서, 상기 리드프레임은: The method according to claim 1, wherein the lead frame comprises:
    내부지지틀과, 이 내부지지틀의 외측 사방 모서리로부터 일체로 연장된 복수 의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 구성된 것을 특징으로 하는 반도체 패키지. Inside the support frame and the inner support a semiconductor package, characterized in that all sides are configured from the outer edge of the frame to the plurality of leads, and a protrusion formed integrally on the pad lead extending integrally.
  3. 청구항 1 또는 청구항 2에 있어서, 상기 리드프레임의 내부지지틀은 그라인딩에 의하여 제거되는 동시에 내부지지틀과 인접한 리드의 상단이 상기 제1몰딩수지의 상면과 평행을 이루며 외부로 노출되고, 리드의 하단은 다운셋되어 상기 제1기판상의 전도성회로패턴에 접속 연결되는 것을 특징으로 하는 반도체 패키지. The method according to claim 1 or claim 2, the inner support frame is the top of the lead adjacent to the inner support frame at the same time is removed by the grinding of the lead frame of the first constitutes the upper surface and parallel to the molding resin is exposed to the outside, the lower end of the lead a semiconductor package, characterized in that the set-down connection is connected to the conductive circuit pattern on the first substrate.
  4. 청구항 1에 있어서, 상기 리드프레임은: The method according to claim 1, wherein the lead frame comprises:
    외부지지틀과, 이 외부지지틀의 내측 사방 모서리로부터 안쪽 방향으로 연장되며 일체로 형성된 복수의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 구성된 것을 특징으로 하는 반도체 패키지. The outer support frame and the outer support frame, characterized in that the semiconductor package and extends inward from the inner edge comprised of a plurality of four-way lead, and a protruding pad formed integrally on the lid is formed integrally with the.
  5. 청구항 1 또는 청구항 4에 있어서, 상기 리드프레임의 외부지지틀은 소잉에 의하여 제거되는 동시에 외부지지틀과 인접한 리드의 하단은 상기 제1기판상의 전도성회로패턴에 접속 연결되고, 리드의 상단은 상기 제1몰딩수지의 상면과 평행을 이루며 외부노 노출되는 것을 특징으로 하는 반도체 패키지. The method according to claim 1 or claim 4, the lower end of the outer support frame of the lead frame is a lead adjacent to the outer support frame at the same time is removed by sawing is connected to connected to the conductive circuit pattern on the first substrate, the top of the lid is the first 1 forms the upper surface and parallel to the molding resin, the semiconductor package characterized in that the outside of the furnace exposed.
  6. 청구항 2 또는 청구항 4에 있어서, 상기 리드프레임의 각 리드의 상단면에는 외부로 노출되어 상기 전도성 연결수단과 접속되는 패드가 일체로 더 돌출 형성된 것을 특징으로 하는 반도체 패키지. The method according to claim 2 or claim 4, the semiconductor package characterized in that the top surface of each lead of the lead frame is exposed to the exterior, the pad that is connected to the conductive connecting member is formed more projected in one piece.
  7. 청구항 1에 있어서, 상기 전도성 연결수단은 솔더볼, 플립 칩, 범프중 선택된 어느 하나인 것을 특징으로 하는 반도체 패키지. The method according to claim 1, wherein the conductive connection means is a semiconductor package, characterized in that any selected one of a solder ball, a flip chip bump one.
  8. ⅰ) 하부에 위치되는 제1반도체 패키지 제조 공정과, ⅱ) 상부에 적층되는 제2반도체 패키지 제조 공정과, ⅲ) 상기 제1 및 제2반도체 패키지를 적층하는 공정, 으로 이루어지되, Ⅰ) claim that is located below the first semiconductor package and a manufacturing process, ⅱ) above the second semiconductor package manufacturing process and, ⅲ laminated on) the first and the step of laminating a second semiconductor package, jidoe made of,
    ⅰ) 상기 제1반도체 패키지 제조 공정은: Ⅰ) of the first semiconductor package manufacturing process:
    제1기판 상에 제1반도체 칩을 부착하고, 상기 제1반도체 칩과 제1기판상의 전도성회로패턴간을 플립 칩으로 전기적 신호 교환 가능하게 연결하는 단계와; The method comprising: mounting a first semiconductor chip on the first substrate, and connecting the first semiconductor chip and a conductive circuit pattern on the first substrate between interchangeably electrical signal and the flip chip;
    내부지지틀과, 이 내부지지틀의 외측 사방 모서리로부터 일체로 연장된 복수의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 이루어진 리드프레임을 구비하여, 각 리드의 하단은 제1기판의 전도성패턴에 연결하는 동시에 리드의 상단 및 내 부지지틀을 제1반도체 칩의 테두리 위쪽으로 이격 배치하는 단계와; Inside the support frame, and a and a plurality of leads extending integrally from the outside all around the edge of the inner support frame, and comprising a lead frame made of a protrusion formed pad integrally on the lid, the bottom of each lead is the conductivity of the first substrate connecting to the pattern at the same time disposing space the top and the internal support frame of a lead in the upper border of the first semiconductor die;
    상기 제1반도체 칩과, 플립 칩과, 리드프레임을 내재시키면서 상기 제1기판상의 몰딩영역을 수지로 몰딩하여 제1몰딩수지층을 형성하는 단계와; While underlying the first semiconductor chip and a flip chip and a lead frame comprising the steps of: forming a first number of the molding resin by molding the molding area on the first substrate with a resin;
    상기 제1몰딩수지의 상면을 그라인딩 수단으로 그라인딩하되, 그 안쪽의 내부지지틀까지 그라인딩하여, 내부지지틀의 제거와 함께 각 리드가 독립적인 리드로 분리되면서 그 패드가 외부로 노출되는 단계; Phase is grinding, but the upper surface of the first molding resin into the grinding means, and grinding the interior of the support frame in its inside, as each lead is separated by independent lead with the removal of the inner support frame is that the pad exposed to the outside; 로 이루어지고, It is made of,
    ⅱ) 상기 제2반도체 패키지 제조 공정은: Ⅱ) and the second semiconductor package manufacturing process:
    제2기판 상에 제2반도체 칩을 부착하고, 상기 제2반도체 칩과 제2기판상의 전도성회로패턴간을 와이어로 연결하는 단계와; The method comprising: mounting a second semiconductor chip on the second substrate, and connecting the second semiconductor chip and a conductive circuit pattern on the second substrate between the wire and;
    상기 제2반도체 칩과 와이어를 포함하는 제2기판상의 몰딩영역을 수지로 몰딩하여 제2몰딩수지층을 형성하는 단계; Forming a second number of the molding resin by molding the molding area on the second substrate including a second semiconductor chip and the wire of a resin; 로 이루어지며, It consists of,
    ⅲ) 상기 제1 및 제2반도체 패키지를 적층하는 공정은: Ⅲ) a step of laminating the first and the second semiconductor package comprising:
    그라인딩에 의하여 외부로 노출된 상기 리드프레임의 각 리드의 패드와, 상기 제2기판의 저면에 형성된 볼랜드간을 전도성 연결수단으로 연결하여 이루어지는 것을 특징으로 하는 반도체 패키지 제조 방법. By grinding the pads and of each lead of the lead frame, wherein the semiconductor package-producing method which comprises the connection between the Borland formed on the bottom surface of the second substrate with a conductive connecting member exposed to the outside.
  9. ⅰ) 하부에 위치되는 제1반도체 패키지 제조 공정과, ⅱ) 상부에 적층되는 제2반도체 패키지 제조 공정과, ⅲ) 상기 제1 및 제2반도체 패키지를 적층하는 공정, 으로 이루어지되, Ⅰ) claim that is located below the first semiconductor package and a manufacturing process, ⅱ) above the second semiconductor package manufacturing process and, ⅲ laminated on) the first and the step of laminating a second semiconductor package, jidoe made of,
    ⅰ) 상기 제1반도체 패키지 제조 공정은: Ⅰ) of the first semiconductor package manufacturing process:
    제1기판 상에 제1반도체 칩을 부착하고, 상기 제1반도체 칩과 제1기판상의 전도성회로패턴간을 플립 칩으로 전기적 신호 교환 가능하게 연결하는 단계와; The method comprising: mounting a first semiconductor chip on the first substrate, and connecting the first semiconductor chip and a conductive circuit pattern on the first substrate between interchangeably electrical signal and the flip chip;
    외부지지틀과, 이 외부지지틀의 내측 사방 모서리로부터 안쪽 방향으로 연장되며 일체로 형성된 복수의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 이루어진 리드프레임을 구비하는 단계와; The outer support frame, and the four-way extending inwardly from the inner edge of the outer support frame comprising: a lead frame having leads and including a plurality of protruding pad formed integrally on the lid formed integrally with;
    상기 리드프레임의 외부지지틀은 제1기판의 끝단 상면상에 지지시키고, 외부지지틀과 인접한 각 리드의 하단은 제1기판의 전도성패턴에 연결시키며, 각 리드의 상단은 제1반도체 칩의 테두리 위쪽으로 이격 배치하는 단계와; The outer support frame of the lead frame and the support at the end upper face of the first substrate, the outer supporting frame and adjacent the lower end of each lead is sikimyeo connected to the conductive pattern of the first substrate, the top of each lead is the border of the first semiconductor chip, comprising: spaced upwardly and;
    상기 제1반도체 칩과, 플립 칩과, 리드프레임을 내재시키면서 상기 제1기판상의 몰딩영역을 수지로 몰딩하여 제1몰딩수지층을 형성하는 단계와; While underlying the first semiconductor chip and a flip chip and a lead frame comprising the steps of: forming a first number of the molding resin by molding the molding area on the first substrate with a resin;
    상기 제1몰딩수지의 상면을 그라인딩 수단으로 그라인딩하되, 그 내부의 존재하는 각 리드의 패드가 노출될 때까지 그라인딩하는 단계와; The step of grinding, but the upper surface of the first molding resin into the grinding means, the grinding to the pad of each lead to the presence therein of the exposed and;
    상기 제1몰딩수지의 테두리단 및 상기 제1기판의 테두리단을 소잉하는 동시에 상기 기판의 끝단에 지지된 상기 리드프레임의 외부지지틀도 함께 소잉으로 제거되어, 각 리드가 독립적인 리드로 분리되는 단계; The first is to remove the rim end and the outer support frame also with sawing of the lead frame support, while sawing the rim edge of the first substrate to the end of the substrate of the molding resin, in which each lead is separated by independent lead step; 로 이루어지고, It is made of,
    ⅱ) 상기 제2반도체 패키지 제조 공정은: Ⅱ) and the second semiconductor package manufacturing process:
    제2기판 상에 제2반도체 칩을 부착하고, 상기 제2반도체 칩과 제2기판상의 전도성회로패턴간을 와이어로 연결하는 단계와; The method comprising: mounting a second semiconductor chip on the second substrate, and connecting the second semiconductor chip and a conductive circuit pattern on the second substrate between the wire and;
    상기 제2반도체 칩과 와이어를 포함하는 제2기판상의 몰딩영역을 수지로 몰 딩하여 제2몰딩수지층을 형성하는 단계; A step of coding the molar the molding area on the second substrate with a resin comprising the second semiconductor chip and the wire form a second molding resin; 로 이루어지며, It consists of,
    ⅲ) 상기 제1 및 제2반도체 패키지를 적층하는 공정은: Ⅲ) a step of laminating the first and the second semiconductor package comprising:
    그라인딩에 의하여 외부로 노출된 상기 리드프레임의 각 리드의 패드와, 상기 제2기판의 저면에 형성된 볼랜드간을 전도성 연결수단으로 연결하여 이루어지는 것을 특징으로 하는 반도체 패키지 제조 방법. By grinding the pads and of each lead of the lead frame, wherein the semiconductor package-producing method which comprises the connection between the Borland formed on the bottom surface of the second substrate with a conductive connecting member exposed to the outside.
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