KR100886100B1 - Semiconductor package and method for manufacturing the same - Google Patents

Semiconductor package and method for manufacturing the same Download PDF

Info

Publication number
KR100886100B1
KR100886100B1 KR1020070122401A KR20070122401A KR100886100B1 KR 100886100 B1 KR100886100 B1 KR 100886100B1 KR 1020070122401 A KR1020070122401 A KR 1020070122401A KR 20070122401 A KR20070122401 A KR 20070122401A KR 100886100 B1 KR100886100 B1 KR 100886100B1
Authority
KR
South Korea
Prior art keywords
substrate
lead
semiconductor package
semiconductor chip
semiconductor
Prior art date
Application number
KR1020070122401A
Other languages
Korean (ko)
Inventor
정윤하
김기정
김재윤
Original Assignee
앰코 테크놀로지 코리아 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 앰코 테크놀로지 코리아 주식회사 filed Critical 앰코 테크놀로지 코리아 주식회사
Priority to KR1020070122401A priority Critical patent/KR100886100B1/en
Application granted granted Critical
Publication of KR100886100B1 publication Critical patent/KR100886100B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A semiconductor package and a manufacturing method thereof are provided to increase reliability about electric signal exchange by contacting a top semiconductor package with a bottom semiconductor package using a lead frame made of copper material. A semiconductor package includes a lead frame(300) made of copper material. The lead frame is separated to an independent terminal by grinding or sawing, and is mounted inside a first semiconductor package. A pad(306) of each lead(304) of the lead frame exposed outside is positioned on a top surface of the first semiconductor package. A second semiconductor package is laminated on the top surface of the lead frame.

Description

반도체 패키지 및 그 제조 방법{Semiconductor package and method for manufacturing the same}Semiconductor package and method for manufacturing the same

본 발명은 반도체 패키지 및 그 제조 방법에 관한 것으로서, 더욱 상세하게는 리드프레임이 탑재된 하부 반도체 패키지와, 이 하부 반도체 패키지내의 리드프레임을 그라인딩 내지 소잉시켜 외부로 노출시킨 패드에 상부 반도체 패키지를 전기적 접속 가능하게 적층 구성시킨 구조의 적층형 반도체 패키지 및 그 제조 방법에 관한 것이다.The present invention relates to a semiconductor package and a method of manufacturing the same. More particularly, the upper semiconductor package is electrically connected to a lower semiconductor package having a lead frame and a pad exposed to the outside by grinding or sawing the lead frame in the lower semiconductor package. The present invention relates to a laminated semiconductor package having a structure in which a laminate is connectable and a method of manufacturing the same.

잘 알려진 바와 같이, 반도체 패키지는 리드프레임, 인쇄회로기판, 회로필름 등의 기판을 이용하여, 기판의 칩부착 영역에 반도체 칩을 부착하는 칩부착 공정, 반도체 칩과 기판간을 전기적 신호 교환을 위하여 골드 와이어 등으로 연결하는 와이어 본딩 공정, 반도체 칩과 와이어 등을 외부로부터 보호하기 위하여 몰딩 컴파운드 수지로 몰딩하는 몰딩 공정 등을 통하여 제조된다.As is well known, a semiconductor package uses a substrate such as a lead frame, a printed circuit board, a circuit film, and the like to attach a semiconductor chip to a chip attaching region of the substrate, and to exchange electrical signals between the semiconductor chip and the substrate. It is manufactured through a wire bonding process for connecting with a gold wire or the like, and a molding process for molding with a molding compound resin in order to protect semiconductor chips and wires from the outside.

최근에는 고집적화를 위하여 반도체 패키지를 상하로 신호 교환 가능하게 적 층시킨 적층형 패키지가 개발되고 있으며, 이를 감안하여 슬림형의 다기능 휴대폰, PDA, 디지털카메라, MP3플레이어를 위한 메모리 패키징 형태로서, 일종의 적층형 패키지인 PoP(Package-on-Package) 패키징이 이루어지고 있는 바, 첨부한 도 3은 종래의 PoP 패키지에 대한 일례를 설명하기 위한 개략적인 단면도이다.Recently, in order to achieve high integration, a stacked package in which a semiconductor package is stacked up and down to exchange signals has been developed.In view of this, a memory packaging form for a slim multifunctional mobile phone, a PDA, a digital camera, and an MP3 player has been developed. Package-on-Package (PoP) packaging is performed, and FIG. 3 is a schematic cross-sectional view for explaining an example of a conventional PoP package.

종래의 PoP 패키지는 하부쪽의 제1반도체 패키지와, 상부쪽의 제2반도체 패키지가 상호 적층된 구조로 되어 있다.The conventional PoP package has a structure in which a first semiconductor package on a lower side and a second semiconductor package on an upper side are stacked on each other.

상기 제1반도체 패키지(10)는 제1기판(12) 상에 부착된 제1반도체 칩(13)과, 제1반도체 칩(13)과 제1기판(12)상의 전도성회로패턴간을 연결하는 플립 칩(14)과, 제1기판(12)의 저면에 형성된 볼랜드에 융착되어 제1반도체 칩(13)의 입출력단자가 되는 제1솔더볼(15)과, 상기 제1반도체 칩(13)과 플립 칩(14) 등을 포함하는 제1기판(12)상의 몰딩영역에 몰딩된 제1몰딩수지(16)를 포함하여 구성되어 있다.The first semiconductor package 10 connects a first semiconductor chip 13 attached to the first substrate 12 and a conductive circuit pattern on the first semiconductor chip 13 and the first substrate 12. A first solder ball 15 fused to a flip chip 14, a ball land formed on a bottom surface of the first substrate 12 to become an input / output terminal of the first semiconductor chip 13, and the first semiconductor chip 13; And a first molding resin 16 molded in a molding region on the first substrate 12 including the flip chip 14 and the like.

이때, 상기 제1기판의 전체 면적중 몰딩영역은 대략 중앙부분이 되고, 이 몰딩영역의 바깥쪽 영역에는 제2반도체 패키지의 적층을 위한 접속단자인 또 다른 전도성 회로패턴이 노출되는 상태가 된다.At this time, the molding region of the entire area of the first substrate is approximately the center portion, and another conductive circuit pattern, which is a connection terminal for stacking the second semiconductor package, is exposed to the outer region of the molding region.

상기 제2반도체 패키지(20)는 제2기판(22) 상에 부착된 제2반도체 칩(23)과, 제2반도체 칩(23)과 제2기판(22)상의 전도성회로패턴간을 연결하는 와이어(24)와, 제2기판(22)의 저면에 형성된 볼랜드에 융착되어 제2반도체 칩(23)의 입출력단자가 되는 제2솔더볼(25)과, 상기 제2반도체 칩(23)과 와이어(24)를 포함하는 제2기판(22)상의 몰딩영역에 몰딩된 제2몰딩수지(26)를 포함하여 구성되어 있다.The second semiconductor package 20 connects a second semiconductor chip 23 attached to the second substrate 22 and a conductive circuit pattern on the second semiconductor chip 23 and the second substrate 22. A second solder ball 25 fused to a wire 24 and a ball land formed on a bottom surface of the second substrate 22 to become an input / output terminal of the second semiconductor chip 23, and the second semiconductor chip 23 and the wire. And a second molding resin 26 molded in a molding region on the second substrate 22 including 24.

따라서, 상기 제1반도체 패키지(10)의 제1기판(12)의 상면에서 바깥쪽 영역 에 노출된 전도성 회로패턴에 상기 제2반도체 패키지(20)의 제2솔더볼(25)을 융착시킴으로써, 제1 및 제2반도체 패키지(10,20)의 적층이 이루어진다.Accordingly, the second solder ball 25 of the second semiconductor package 20 is fused to the conductive circuit pattern exposed to the outer region on the upper surface of the first substrate 12 of the first semiconductor package 10. The first and second semiconductor packages 10 and 20 are stacked.

그러나, 종래의 PoP 타입 패키지는 다음과 같은 문제점이 있다.However, the conventional PoP type package has the following problems.

상기 제1반도체 패키지(10)와 제2반도체 패키지(20)의 적층 및 전기적 신호 연결을 위한 수단인 제2솔더볼(25: 범프)의 높이가 적어도 상기 제1기판(12)의 상면과 제2기판(22)의 저면 사이의 간격(H), 즉 제1몰딩수지(16)의 높이보다 커야 하므로, 제2솔더볼(25)의 크기가 과대해지는 문제점이 있다.The height of the second solder ball 25 (bump), which is a means for stacking the first semiconductor package 10 and the second semiconductor package 20 and for connecting electrical signals, is at least a top surface and a second surface of the first substrate 12. Since the distance H between the bottom surfaces of the substrate 22, that is, the height of the first molding resin 16, must be greater than that, the size of the second solder ball 25 may be excessive.

상기 제2솔더볼의 크기와 관련된 전기적 접속 기술로 인하여, 전체 패키지에서 차지하는 제2솔더볼의 크기를 줄이기 어려우며, 결국 제1 및 제2패키지간의 간격이 커져 전체 패키지의 두께 증가 및 내구성 저하를 초래하는 문제점이 있다.Due to the electrical connection technology related to the size of the second solder ball, it is difficult to reduce the size of the second solder ball occupies the entire package, resulting in a large gap between the first and second packages resulting in an increase in the thickness and durability of the entire package. There is this.

특히, 상기 제2솔더볼의 크기가 과대해짐에 따라, 제1반도체 패키지와 제2반도체 패키지를 상호 연결할 때, 제2솔더볼에 대한 변형 문제가 발생할 수 있고, 열적 스트레스(thermal stress) 등과 같은 여러가지 요인으로 인하여 제2솔더볼의 탈락되는 내구성 저하 문제가 발생할 수 있으며, 결국 제1 및 제2반도체 패키지간의 접속 단락 등이 발생되는 문제점이 발생할 수 있다.In particular, as the size of the second solder ball is excessive, deformation of the second solder ball may occur when the first semiconductor package and the second semiconductor package are interconnected, and various factors, such as thermal stress, may occur. As a result, a problem of deterioration in durability in which the second solder ball is dropped may occur, and a problem may occur in that a connection short circuit between the first and second semiconductor packages occurs.

본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, 그라인딩 또는 소잉에 의하여 독립적인 단자로 분리될 수 있는 리드프레임을 구비하여 하부쪽의 제1반 도체 패키지내에 탑재시키고, 이후 제1반도체 패키지의 상면에 독립적인 단자(패드)로 분리되며 외부로 노출된 리드프레임의 각 리드의 패드에 상부쪽의 제2반도체 패키지를 신호 교환 가능하게 적층 구성되도록 함으로써, 상부 및 하부 반도체 패키지간의 간격을 줄일 수 있고, 구리 재질인 리드프레임을 이용하므로 전기 전도도 및 그 전기적 신호 교환에 대한 신뢰성을 증대시킬 수 있는 반도체 패키지 및 그 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made in view of the above, and provided with a lead frame that can be separated into independent terminals by grinding or sawing, mounted in the first semiconductor package on the lower side, and then of the first semiconductor package. The gap between the upper and lower semiconductor packages can be reduced by separating the upper and lower semiconductor packages on the pads of each lead of the lead frame, which are separated by independent terminals (pads) on the upper surface, so as to exchange signals. In addition, since a lead frame made of copper is used, an object of the present invention is to provide a semiconductor package and a method of manufacturing the same, which can increase electrical conductivity and reliability of electrical signal exchange.

상기한 목적을 달성하기 위한 본 발명의 일 구현예는:One embodiment of the present invention for achieving the above object is:

제1기판 상에 부착된 제1반도체 칩, 상기 제1반도체 칩과 제1기판상의 전도성회로패턴간을 연결하는 플립 칩, 상기 제1반도체 칩과 플립 칩을 포함하는 제1기판상의 몰딩영역에 몰딩된 제1몰딩수지, 상단은 상기 제1몰딩수지의 상면과 평행을 이루며 외부로 노출되고 그 하단은 다운셋되어 상기 제1반도체 칩의 바깥쪽으로 연장되면서 상기 제1기판상의 전도성회로패턴에 접속 연결되는 리드프레임, 상기 제1기판의 저면에 형성된 볼랜드에 융착되어 제1반도체 칩의 입출력단자가 되는 제1솔더볼, 을 포함하는 제1반도체 패키지와; 제2기판 상에 부착된 제2반도체 칩, 상기 제2반도체 칩과 제2기판상의 전도성회로패턴간을 연결하는 와이어, 상기 제2반도체 칩과 와이어를 포함하는 제2기판상의 몰딩영역에 몰딩된 제2몰딩수지, 를 포함하는 제2반도체 패키지; 를 적층 구성하되, 외부로 노출된 상기 리드프레임의 상단면과, 상기 제2기판의 저면에 형성된 볼랜드간을 전도성 연결수단으로 연결하여서, 상기 제1 및 제2반도체 패키지가 적층 구성되는 것을 특징으로 하는 반도체 패키지를 제공한다.A first semiconductor chip attached to a first substrate, a flip chip connecting between the first semiconductor chip and a conductive circuit pattern on the first substrate, and a molding region on the first substrate including the first semiconductor chip and the flip chip. Molded first molding resin, the upper end is parallel to the upper surface of the first molding resin exposed to the outside and the lower end is downset to extend to the outside of the first semiconductor chip connected to the conductive circuit pattern on the first substrate A first semiconductor package including a lead frame connected to each other, a first solder ball fused to a ball land formed on a bottom surface of the first substrate to become an input / output terminal of a first semiconductor chip; A second semiconductor chip attached to the second substrate, a wire connecting the second semiconductor chip and the conductive circuit pattern on the second substrate, and molded in a molding region on the second substrate including the second semiconductor chip and the wire. A second semiconductor package comprising a second molding resin; Although the laminated structure, the first and second semiconductor package is laminated by connecting between the upper surface of the lead frame exposed to the outside and the ball land formed on the bottom surface of the second substrate by a conductive connection means A semiconductor package is provided.

바람직한 구현예로서, 상기 리드프레임은: 내부지지틀과, 이 내부지지틀의 외측 사방 모서리로부터 일체로 연장된 복수의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 구성된 것을 특징으로 한다.In a preferred embodiment, the lead frame comprises: an inner support frame, a plurality of leads integrally extending from the outer four corners of the inner support frame, and pads integrally protruding on the leads.

더욱 바람직한 구현예로서, 상기 리드프레임의 내부지지틀은 그라인딩에 의하여 제거되는 동시에 내부지지틀과 인접한 리드의 상단이 상기 제1몰딩수지의 상면과 평행을 이루며 외부로 노출되고, 리드의 하단은 다운셋되어 상기 제1기판상의 전도성회로패턴에 접속 연결되는 것을 특징으로 한다.In a more preferred embodiment, the inner support frame of the lead frame is removed by grinding and at the same time the upper end of the lead adjacent to the inner support frame is exposed to the outside in parallel with the upper surface of the first molding resin, the lower end of the lead Set to be connected to the conductive circuit pattern on the first substrate.

바람직한 다른 구현예로서, 상기 리드프레임은: 외부지지틀과, 이 외부지지틀의 내측 사방 모서리로부터 안쪽 방향으로 연장되며 일체로 형성된 복수의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 구성된 것을 특징으로 한다.In another preferred embodiment, the lead frame comprises: an outer support frame, a plurality of leads integrally formed in one direction extending inwardly from the inner four corners of the outer support frame, and pads protruding integrally on the leads; It features.

더욱 바람직한 다른 구현예로서, 상기 리드프레임의 외부지지틀은 소잉에 의하여 제거되는 동시에 외부지지틀과 인접한 리드의 하단은 상기 제1기판상의 전도성회로패턴에 접속 연결되고, 리드의 상단은 상기 제1몰딩수지의 상면과 평행을 이루며 외부노 노출되는 것을 특징으로 한다.In another preferred embodiment, the outer support frame of the lead frame is removed by sawing, while the lower end of the lead adjacent to the outer support frame is connected to the conductive circuit pattern on the first substrate, and the upper end of the lead is connected to the first frame. Parallel to the upper surface of the molding resin is characterized in that the external furnace exposed.

이때, 상기 리드의 상단면에는 외부로 노출되어 상기 전도성 연결수단과 접속되는 패드가 일체로 더 형성된 것을 특징으로 한다.At this time, the upper surface of the lead is characterized in that the pad is further exposed to the outside and integrally connected to the conductive connecting means.

바람직하게는, 상기 전도성 연결수단은 솔더볼, 플립 칩, 범프중 선택된 어느 하나인 것을 특징으로 한다.Preferably, the conductive connecting means is any one selected from a solder ball, flip chip, bump.

상기한 목적을 달성하기 위한 본 발명의 다른 구현예는:Another embodiment of the present invention for achieving the above object is:

ⅰ) 하부에 위치되는 제1반도체 패키지 제조 공정과, ⅱ) 상부에 위치되는 제2반도체 패키지 제조 공정과, ⅲ) 상기 제1 및 제2반도체 패키지를 적층하는 공정, 으로 이루어지되,Iii) a process of manufacturing the first semiconductor package located at the bottom, ii) a process of manufacturing the second semiconductor package located at the top, and iii) laminating the first and second semiconductor packages,

ⅰ) 상기 제1반도체 패키지 제조 공정은: 제1기판 상에 제1반도체 칩을 부착하고, 상기 제1반도체 칩과 제1기판상의 전도성회로패턴간을 플립 칩으로 전기적 신호 교환 가능하게 연결하는 단계와; 내부지지틀과, 이 내부지지틀의 외측 사방 모서리로부터 일체로 연장된 복수의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 이루어진 리드프레임을 구비하여, 각 리드의 하단은 제1기판의 전도성패턴에 연결하는 동시에 리드의 상단 및 내부지지틀을 제1반도체 칩의 테두리 위쪽으로 이격 배치하는 단계와; 상기 제1반도체 칩과, 플립 칩과, 리드프레임을 내재시키면서 상기 제1기판상의 몰딩영역을 수지로 몰딩하여 제1몰딩수지층을 형성하는 단계와; 상기 제1몰딩수지의 상면을 그라인딩 수단으로 그라인딩하되, 그 안쪽의 내부지지틀까지 그라인딩하여, 내부지지틀의 제거와 함께 각 리드가 독립적인 리드로 분리되면서 그 패드가 외부로 노출되는 단계; 로 이루어지고,Iii) The first semiconductor package manufacturing process comprises the steps of: attaching a first semiconductor chip on a first substrate, and electrically connecting the first semiconductor chip to a conductive circuit pattern on the first substrate so as to be exchangeable with flip chips. Wow; A lead frame comprising an inner support frame, a plurality of leads integrally extending from the outer four corners of the inner support frame, and a pad integrally protruding on the leads, the lower ends of each lead being conductive to the first substrate. Disposing the upper end and the inner support frame of the lead above the edge of the first semiconductor chip while connecting to the pattern; Forming a first molding resin layer by molding a molding region on the first substrate with a resin while embedding the first semiconductor chip, the flip chip, and the lead frame; Grinding the upper surface of the first molding resin with grinding means, and grinding the inner support frame therein to expose the pad to the outside while removing the inner support frame and separating each lead into independent leads; Made up of

ⅱ) 상기 제2반도체 패키지 제조 공정은: 제2기판 상에 제2반도체 칩을 부착하고, 상기 제2반도체 칩과 제2기판상의 전도성회로패턴간을 와이어로 연결하는 단계와; 상기 제2반도체 칩과 와이어를 포함하는 제2기판상의 몰딩영역을 수지로 몰딩하여 제2몰딩수지층을 형성하는 단계; 로 이루어지며,Ii) the process of manufacturing the second semiconductor package comprises: attaching a second semiconductor chip on a second substrate, and connecting the second semiconductor chip with a conductive circuit pattern on the second substrate with a wire; Molding a molding region on a second substrate including the second semiconductor chip and wire with a resin to form a second molding resin layer; It consists of

ⅲ) 상기 제1 및 제2반도체 패키지를 적층하는 공정은: 그라인딩에 의하여 외부로 노출된 상기 리드프레임의 각 리드의 패드와, 상기 제2기판의 저면에 형성된 볼랜드간을 전도성 연결수단으로 연결하여 이루어지는 것을 특징으로 하는 반도체 패키지 제조 방법을 제공한다.Iii) laminating the first and second semiconductor packages by connecting the pads of the leads of the lead frame exposed to the outside by grinding and the ball lands formed on the bottom of the second substrate by conductive connecting means. It provides a semiconductor package manufacturing method characterized in that.

상기한 목적을 달성하기 위한 본 발명의 또 다른 구현예는:Another embodiment of the present invention for achieving the above object is:

ⅰ) 하부에 위치되는 제1반도체 패키지 제조 공정과, ⅱ) 상부에 적층되는 제2반도체 패키지 제조 공정과, ⅲ) 상기 제1 및 제2반도체 패키지를 전기적 신호교환 가능하게 적층하는 공정, 으로 이루어지되,Iii) a step of manufacturing the first semiconductor package located at the bottom, ii) a step of manufacturing the second semiconductor package stacked at the top, and iii) laminating the first and second semiconductor packages so as to be capable of electrical signal exchange. Understand,

ⅰ) 상기 제1반도체 패키지 제조 공정은: 제1기판 상에 제1반도체 칩을 부착하고, 상기 제1반도체 칩과 제1기판상의 전도성회로패턴간을 플립 칩으로 전기적 신호 교환 가능하게 연결하는 단계와; 외부지지틀과, 이 외부지지틀의 내측 사방 모서리로부터 안쪽 방향으로 연장되며 일체로 형성된 복수의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 이루어진 리드프레임을 구비하는 단계와; 상기 리드프레임의 외부지지틀은 제1기판의 끝단 상면상에 지지시키고, 외부지지틀과 인접한 각 리드의 하단은 제1기판의 전도성패턴에 연결시키며, 각 리드의 상단은 제1반도체 칩의 테두리 위쪽으로 이격 배치하는 단계와; 상기 제1반도체 칩과, 플립 칩과, 리드프레임을 내재시키면서 상기 제1기판상의 몰딩영역을 수지로 몰딩하여 제1몰딩수지층을 형성하는 단계와; 상기 제1몰딩수지의 상면을 그라인딩 수단으로 그라인딩하되, 그 내부의 존재하는 리드의 패드가 노출될 때까지 그라인딩하는 단계와; 상기 제1몰딩수지의 테두리단 및 상기 제1기판의 테두리단을 소잉하는 동시에 상기 기판의 끝단에 지지된 상기 리드프레임의 외부지지틀도 함께 소잉으로 제거되 어, 각 리드가 독립적인 리드로 분리되는 단계; 로 이루어지고,Iii) The first semiconductor package manufacturing process comprises the steps of: attaching a first semiconductor chip on a first substrate, and electrically connecting the first semiconductor chip to a conductive circuit pattern on the first substrate so as to be exchangeable with flip chips. Wow; Providing an outer support frame, a plurality of leads integrally formed in one direction and extending inwardly from inner corners of the outer support frame, and a lead frame comprising pads integrally formed on the leads; The outer support frame of the lead frame is supported on the upper end of the first substrate, the lower end of each lead adjacent to the outer support frame is connected to the conductive pattern of the first substrate, the upper end of each lead is the edge of the first semiconductor chip Spacing upwardly; Forming a first molding resin layer by molding a molding region on the first substrate with a resin while embedding the first semiconductor chip, the flip chip, and the lead frame; Grinding the upper surface of the first molding resin by grinding means, but grinding the pads of the reeds existing therein; The edge of the first molding resin and the edge of the first substrate are sawed, and the outer support frame of the lead frame supported at the end of the substrate is also sawed off, so that each lead is separated into an independent lead. Becoming; Made up of

ⅱ) 상기 제2반도체 패키지 제조 공정은: 제2기판 상에 제2반도체 칩을 부착하고, 상기 제2반도체 칩과 제2기판상의 전도성회로패턴간을 와이어로 연결하는 단계와; 상기 제2반도체 칩과 와이어를 포함하는 제2기판상의 몰딩영역을 수지로 몰딩하여 제2몰딩수지층을 형성하는 단계; 로 이루어지며,Ii) the process of manufacturing the second semiconductor package comprises: attaching a second semiconductor chip on a second substrate, and connecting the second semiconductor chip with a conductive circuit pattern on the second substrate with a wire; Molding a molding region on a second substrate including the second semiconductor chip and wire with a resin to form a second molding resin layer; It consists of

ⅲ) 상기 제1 및 제2반도체 패키지를 적층하는 공정은: 그라인딩에 의하여 외부로 노출된 상기 리드프레임의 각 리드의 패드와, 상기 제2기판의 저면에 형성된 볼랜드간을 전도성 연결수단으로 연결하여 이루어지는 것을 특징으로 하는 반도체 패키지 제조 방법을 제공한다.Iii) laminating the first and second semiconductor packages by connecting the pads of the leads of the lead frame exposed to the outside by grinding and the ball lands formed on the bottom of the second substrate by conductive connecting means. It provides a semiconductor package manufacturing method characterized in that.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공할 수 있다.Through the above problem solving means, the present invention can provide the following effects.

그라인딩 또는 소잉에 의하여 독립적인 단자로 분리될 수 있는 리드프레임을 구비하여 하부쪽의 제1반도체 패키지내에 탑재시키고, 이후 리드프레임의 상단이 제1반도체 패키지의 상면에 독립적인 단자(패드)로 분리되며 외부로 노출되도록 한 다음, 리드프레임의 각 리드의 패드에 상부쪽의 제2반도체 패키지를 신호 교환 가능하게 적층 구성되도록 함으로써, 상부 및 하부 반도체 패키지간의 간격을 줄일 수 있고, 전체적으로 두께를 줄일 수 있는 적층형 패키지를 제공할 수 있다.A lead frame which can be separated into independent terminals by grinding or sawing is mounted in the lower first semiconductor package, and then the upper end of the lead frame is separated into independent terminals (pads) on the upper surface of the first semiconductor package. The second semiconductor package of the upper side is laminated on the pad of each lead of the lead frame so as to be interchangeable with each other. Thus, the gap between the upper and lower semiconductor packages can be reduced, and the overall thickness can be reduced. A stacked package can be provided.

또한, 상부 및 하부 반도체 패키지를 전기 전도도가 우수한 구리 재질의 리 드프레임을 이용하여 접속되도록 함으로써, 전기 전도도 및 그 전기적 신호 교환에 대한 신뢰성을 증대시킬 수 있다.In addition, by connecting the upper and lower semiconductor packages using a copper lead frame having excellent electrical conductivity, it is possible to increase the electrical conductivity and the reliability of the electrical signal exchange.

또한, 종래에는 하부쪽 패키지의 몰딩수지 높이 이상의 크기를 갖는 과도한 크기의 솔더볼 내지 범프를 이용하여 상부 및 하부 패키지를 적층 연결하였지만, 이에 반하여, 본 발명은 하부의 제1반도체 패키지의 상면과, 상부의 제2반도체 패키지의 저면이 평평한 형태로 배열되므로, 종래의 몰딩수지의 높이에 따른 갑섭 현상없이 아주 작은 솔더볼 내지 범프 등을 이용하여 상하 패키지를 신호 교환 가능하게 적층할 수 있게 되어, 보다 안정적인 적층형 패키지를 제공할 수 있다.In addition, in the related art, the upper and lower packages are laminated and connected by using solder balls or bumps of excessive size having a size greater than or equal to the molding resin height of the lower package. Since the bottom surface of the second semiconductor package is arranged in a flat shape, it is possible to stack the upper and lower packages so as to be able to exchange signals using very small solder balls or bumps without any interference caused by the height of the conventional molding resin. Package can be provided.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 상부 및 하부 패키지가 상하로 적층된 형태의 반도체 패키지를 제공하고자 한 것으로서, 상부 및 하부 패키지의 전기적 신호 연결을 리드프레임을 이용한 점, 그리고 리드프레임을 그라인딩 또는 소잉에 의하여 독립적인 단자로 분리시킨 점 등에 주안점이 있다.The present invention is to provide a semiconductor package in which the upper and lower packages are stacked up and down, the electrical signal connection of the upper and lower packages using a lead frame, and the lead frame to an independent terminal by grinding or sawing The main point is the separation point.

이를 위한, 본 발명에 따른 반도체 패키지 및 그 제조 방법에 대한 제1실시예를 설명하면 다음과 같다.To this end, a first embodiment of a semiconductor package and a method of manufacturing the same according to the present invention will be described.

[제1실시예][First Embodiment]

첨부한 도 1은 본 발명에 따른 반도체 패키지 및 그 제조 방법의 제1실시예 를 순서대로 설명하는 단면도이다.1 is a cross-sectional view sequentially illustrating a first embodiment of a semiconductor package and a method of manufacturing the same according to the present invention.

본 발명의 제1실시예에 따른 반도체 패키지는 하부에 위치되는 제1반도체 패키지 제조 공정과, 상부에 적층되는 제2반도체 패키지 제조 공정과, 상기 제1 및 제2반도체 패키지를 전기적 신호 교환 가능하게 적층하는 공정으로 이루어진다.The semiconductor package according to the first embodiment of the present invention provides a process for manufacturing a first semiconductor package positioned at a lower portion, a process for manufacturing a second semiconductor package stacked at an upper portion, and an electrical signal exchange between the first and second semiconductor packages. It consists of a process of laminating.

제1반도체 패키지 제조 공정First Semiconductor Package Manufacturing Process

먼저, 제1기판(102)의 중앙부 영역에 구획된 칩 부착영역에 제1반도체 칩(104)을 부착하고, 이어서 상기 제1반도체 칩(104)의 저면에 형성된 복수의 본딩패드와, 상기 제1기판(102)상에서 칩 부착영역의 바깥쪽에 노출되어 있는 전도성회로패턴간을 플립 칩(106)을 매개로 하여 전기적 신호 교환 가능하게 연결한다.First, the first semiconductor chip 104 is attached to a chip attaching region partitioned in the central region of the first substrate 102, and then, a plurality of bonding pads formed on the bottom surface of the first semiconductor chip 104, The conductive circuit patterns exposed on the outside of the chip attaching region on the first substrate 102 are connected to each other so that electrical signals can be exchanged via the flip chip 106.

다음으로, 상기 제1기판(102)에 상하로 적층되는 패키지의 전기적 접속을 위한 연결수단이 되는 리드프레임(300)을 안착시킨다.Next, the lead frame 300, which is a connecting means for electrical connection of a package stacked up and down on the first substrate 102, is seated.

상기 리드프레임(300)은 도 1의 우측에 나타낸 평면도에서 보는 바와 같이, 사각틀 형상의 내부지지틀(302)과, 이 내부지지틀(302)의 외측 사방 모서리로부터 외측방향으로 연장되며 일체로 복수의 리드(304)로 구성되고, 특히 상기 각 리드(304)상에는 보다 넓은 면적을 갖는 패드(306)가 일체로 돌출 형성된다.As shown in the plan view on the right side of FIG. 1, the lead frame 300 extends outwardly from the outer four corners of the rectangular frame shape and the outer four corners of the inner support frame 302. And a pad 306 having a larger area is integrally formed on each of the leads 304.

또한, 상기 내부지지틀(302)로부터 연장되는 각 리드(304)는 밑쪽으로 다운셋(down-set)되며 연장된다.In addition, each lead 304 extending from the inner support frame 302 is down-set and extended downward.

이에, 상기 리드프레임(300)의 각 리드(304)의 하단은 제1기판(102)의 전도성회로패턴에 연결하는 동시에 각 리드(304)의 상단 및 내부지지틀(302)은 상기 제1반도체 칩(104)의 테두리 위쪽으로 이격 배치시킨다.Accordingly, the lower end of each lead 304 of the lead frame 300 is connected to the conductive circuit pattern of the first substrate 102 while the upper end and the inner support frame 302 of each lead 304 are formed of the first semiconductor. Spaced apart from the edge of the chip 104.

다음으로, 몰딩 단계로서 상기 제1반도체 칩(104)과, 플립 칩(106)과, 리드프레임(300)을 내재시키면서 상기 제1기판(102)상에 구획된 몰딩영역이 수지로 몰딩되어, 제1몰딩수지(108)층이 형성된다.Next, as a molding step, a molding region partitioned on the first substrate 102 with the first semiconductor chip 104, the flip chip 106, and the lead frame 300 is molded with resin, The first molding resin 108 layer is formed.

이 몰딩 단계후, 상기 리드프레임(300)은 제1몰딩수지(108)층의 내부에 존재하는 상태가 된다.After this molding step, the lead frame 300 is in a state existing inside the first molding resin 108 layer.

이어서, 상기 제1몰딩수지(108)의 상면을 그라인딩 수단을 이용하여 그라인딩하되, 그 안쪽의 내재된 내부지지틀(302)까지 그라인딩하여, 리드프레임(300)의 내부지지틀(302)이 제거되도록 함으로써, 내부지지틀(302)에 의하여 하나로 연결되어 있던 각 리드(304)들은 독립적인 리드로 분리된다.Subsequently, the upper surface of the first molding resin 108 is ground using grinding means, but the inner support frame 302 of the lead frame 300 is removed by grinding up to the internal support frame 302 therein. By doing so, each lead 304, which has been connected as one by the inner support frame 302, is separated into independent leads.

특히, 그라인딩은 상기 내부지지틀(302)의 제거와 함께 각 리드(304)의 패드(306)가 외부로 노출될때까지 진행되며, 외부로 노출된 각 리드(304)의 패드(306)는 상부 패키지를 적층함에 있어 실질적인 전기적 연결점 역할을 하게 된다.In particular, grinding is performed until the pad 306 of each lid 304 is exposed to the outside with the removal of the inner support frame 302, and the pad 306 of each lid 304 exposed to the outside is upper part. In stacking the packages, they serve as the actual electrical connections.

이상과 같은 단계로 제1실시예에 따른 제1반도체 패키지(100)가 완성된다.As described above, the first semiconductor package 100 according to the first embodiment is completed.

제2반도체 패키지 제조 공정Second Semiconductor Package Manufacturing Process

제2기판(202) 상의 중앙부 영역에 구획된 칩 부착영역에 제2반도체 칩(204)을 부착하고, 상기 제2반도체 칩(204)의 상면에 형성된 복수의 본딩패드와 상기 제2기판(202)상에서 제2반도체 칩(204)의 바깥쪽에 노출되어 있는 전도성회로패턴간을 와이어(206)로 연결한다.The second semiconductor chip 204 is attached to the chip attaching region partitioned in the central region on the second substrate 202, and the plurality of bonding pads and the second substrate 202 formed on the upper surface of the second semiconductor chip 204. ) Between the conductive circuit patterns exposed on the outside of the second semiconductor chip 204 by the wire 206.

이어서, 상기 제2반도체 칩(204)과 와이어(206) 등을 포함하는 제2기판(202) 상의 몰딩영역을 수지로 몰딩하여 제2몰딩수지(208)층을 형성함으로써, 상부 패키지로 적층되어질 제2반도체 패키지(200)가 완성된다.Subsequently, the molding region on the second substrate 202 including the second semiconductor chip 204 and the wire 206 and the like is molded with a resin to form a second molding resin 208 layer, thereby stacking the upper package. The second semiconductor package 200 is completed.

제1 및 제2반도체 패키지를 적층하는 공정Laminating the first and second semiconductor packages

상기와 같이, 그라인딩에 의하여 외부로 노출된 상기 제1반도체 패키지(100)의 각 리드(304)의 패드(306)와, 상기 제2반도체 패키지(200)의 제2기판(202)의 저면에 형성된 볼랜드간을 전도성 연결수단(308), 예를들어 솔더볼, 플립 칩, 범프중 선택된 어느 하나를 매개로 하여 서로 전기적 신호 교환 가능하게 연결함으로써, 제1반도체 패키지(100)의 위에 제2반도체 패키지(200)가 적층된 적층형 패키지로 완성된다.As described above, the pad 306 of each lead 304 of the first semiconductor package 100 exposed to the outside by grinding, and the bottom surface of the second substrate 202 of the second semiconductor package 200. The second semiconductor package is formed on the first semiconductor package 100 by electrically connecting the borlands formed therein with a conductive connecting means 308 such as solder balls, flip chips, or bumps. 200 is completed with a stacked package.

이와 같이, 종래에 과도한 크기를 갖는 솔더볼을 매개로 패키지를 적층 연결하는 것과 달리, 본 발명은 제1반도체 패키지내에 내재시킨 리드프레임을 매개로 제2반도체 패키지를 적층 연결함으로써, 전체 패키지의 안정성을 제공함과 더불어 상부 및 하부 반도체 패키지간의 간격을 줄일 수 있고, 전기 전도도가 우수한 구리 재질의 리드프레임을 이용하므로 전기적 신호 교환에 대한 신뢰성을 향상시킬 수 있다.As described above, unlike the conventional stacking of the package through the solder ball having an excessive size, the present invention stacks the second semiconductor package through the lead frame embedded in the first semiconductor package, thereby improving stability of the entire package. In addition, the gap between the upper and lower semiconductor packages can be reduced, and a copper lead frame having excellent electrical conductivity can be used to improve reliability of electrical signal exchange.

여기서, 본 발명에 따른 반도체 패키지 및 그 제조 방법에 대한 제2실시예를 설명하면 다음과 같다.Here, a second embodiment of a semiconductor package and a method of manufacturing the same according to the present invention will be described.

[제2실시예]Second Embodiment

첨부한 도 2은 본 발명에 따른 반도체 패키지 및 그 제조 방법의 제2실시예를 순서대로 설명하는 단면도이다.2 is a cross-sectional view sequentially illustrating a second embodiment of a semiconductor package and a method of manufacturing the same according to the present invention.

본 발명의 제2실시예에 따른 반도체 패키지도 하부에 위치되는 제1반도체 패키지 제조 공정과, 상부에 적층되는 제2반도체 패키지 제조 공정과, 상기 제1 및 제2반도체 패키지를 전기적 신호 교환 가능하게 적층하는 공정으로 이루어진다.In the semiconductor package according to the second embodiment of the present invention, a process of manufacturing a first semiconductor package disposed at a lower portion, a process of manufacturing a second semiconductor package stacked on the upper surface, and an electrical signal exchange between the first and second semiconductor packages are performed. It consists of a process of laminating.

제1반도체 패키지 제조 공정First Semiconductor Package Manufacturing Process

먼저, 제1기판(102)의 중앙부 영역에 구획된 칩 부착영역에 제1반도체 칩(104)을 부착하고, 이어서 상기 제1반도체 칩(104)의 저면에 형성된 복수의 본딩패드와, 상기 제1기판(102)상에서 칩 부착영역의 바깥쪽에 노출되어 있는 전도성회로패턴간을 플립 칩(106)을 매개로 하여 전기적 신호 교환 가능하게 연결한다.First, the first semiconductor chip 104 is attached to a chip attaching region partitioned in the central region of the first substrate 102, and then, a plurality of bonding pads formed on the bottom surface of the first semiconductor chip 104, The conductive circuit patterns exposed on the outside of the chip attaching region on the first substrate 102 are connected to each other so that electrical signals can be exchanged via the flip chip 106.

다음으로, 상기 제1기판(102)에 상하로 적층되는 패키지의 전기적 접속을 위한 연결수단이 되는 리드프레임(400)을 안착시킨다.Next, the lead frame 400, which is a connecting means for electrical connection of a package stacked up and down on the first substrate 102, is seated.

제2실시예에 따른 리드프레임(400)은 도 2의 우측에 도시된 평면도에서 보는 바와 같이, 사각틀 형상의 외부지지틀(402)과, 이 외부지지틀(402)의 내측 사방 모서리로부터 안쪽 방향으로 연장되며 일체로 형성된 복수의 리드(404)로 구성되고, 마찬가지로 각 리드(404)상에 보다 큰 면적을 갖는 패드(406)가 일체로 형성된다.As shown in the plan view of the right side of FIG. 2, the lead frame 400 according to the second embodiment has an outer support frame 402 having a rectangular frame shape and an inward direction from the inner four corners of the outer support frame 402. And a pad 406 having a larger area on each lead 404 is formed integrally.

또한, 상기 외부지지틀(402)로부터 연장되는 각 리드(404)는 위쪽으로 다운셋(down-set)되며 연장된다.In addition, each lead 404 extending from the outer support frame 402 extends down-set upwards.

이에, 상기 리드프레임(400)의 외부지지틀(402)은 상기 제1기판(102)의 끝단 상면상에 안착시키고, 외부지지틀(402)과 평행하게 인접한 각 리드(404)의 하단은 상기 제1기판(102)의 전도성회로패턴에 전기적 접속 가능하게 연결시키며, 또한 각 리드(404)의 상단은 상기 제1반도체 칩(104)의 테두리 위쪽으로 이격 배치시킨다.Accordingly, the outer support frame 402 of the lead frame 400 is seated on the upper end surface of the first substrate 102, the lower end of each lead 404 adjacent to the outer support frame 402 is the The conductive circuit pattern of the first substrate 102 is electrically connected to each other, and an upper end of each lead 404 is spaced apart from an edge of the first semiconductor chip 104.

다음으로, 몰딩 단계로서 상기 제1반도체 칩(104)과, 플립 칩(106)과, 리드프레임(400)을 내재시키면서 상기 제1기판(102)상에 구획된 몰딩영역이 수지로 몰딩되어, 제1몰딩수지(108)층이 형성되며, 이 몰딩 단계후 리드프레임(400)은 제1몰딩수지(108)의 내부에 존재하는 상태가 된다.Next, a molding region partitioned on the first substrate 102 with the first semiconductor chip 104, the flip chip 106, and the lead frame 400 as a molding step is molded with resin. A first molding resin layer 108 is formed, and after this molding step, the lead frame 400 is in a state existing inside the first molding resin 108.

이어서, 상기 제1몰딩수지(108)의 상면을 그라인딩 수단으로 그라인딩하되, 그 내부의 존재하는 각 리드(404)의 패드가 노출될 때까지 그라인딩함으로써, 제1반도체 패키지(100)의 상면 즉, 제1몰딩수지(108)의 상면에 각 리드(404)의 패드(406)가 노출되는 상태가 된다.Subsequently, the upper surface of the first molding resin 108 is ground by grinding means, and the upper surface of the first semiconductor package 100 is ground by grinding until the pad of each lead 404 existing therein is exposed. The pad 406 of each lead 404 is exposed to an upper surface of the first molding resin 108.

연이어, 상기 리드프레임(400)의 각 리드(404)를 독립적인 리드로 분리하기 위한 소잉(sawing) 단계가 진행되는 바, 상기 제1몰딩수지(108)의 테두리단 및 상기 제1기판(102)의 테두리단을 동시에 소잉함으로써, 그 안쪽에 내재되어 있던 상기 리드프레임(400)의 외부지지틀(402)도 함께 소잉으로 제거되어, 각 리드(404)가 독립적인 리드로 분리되어진다.Subsequently, a sawing step for separating each lead 404 of the lead frame 400 into independent leads is performed. The edge of the first molding resin 108 and the first substrate 102 are separated. By simultaneously sawing the edges of the edges), the outer support frame 402 of the lead frame 400 embedded therein is also removed by sawing, and each lead 404 is separated into an independent lead.

이상과 같은 단계로 제2실시예에 따른 제1반도체 패키지(100)가 완성된다.As described above, the first semiconductor package 100 according to the second embodiment is completed.

제2반도체 패키지 제조 공정Second Semiconductor Package Manufacturing Process

제2실시예에 따른 제2반도체 패키지(200) 제조 공정은 제1실시예와 마찬가지로, 제2기판(202) 상에 칩 부착영역에 제2반도체 칩(204)을 부착하고, 상기 제2반도체 칩(204)의 상면에 형성된 각 본딩패드와 상기 제2기판(202)상의 전도성회로패턴간을 와이어(206)로 연결하며, 상기 제2반도체 칩(204)과 와이어(206) 등을 포함하는 제2기판(202)상의 몰딩영역을 수지로 몰딩하여 제2몰딩수지(208)층을 형성함 으로써, 제2반도체 패키지(200)로 완성된다.In the manufacturing process of the second semiconductor package 200 according to the second embodiment, the second semiconductor chip 204 is attached to the chip attaching region on the second substrate 202 as in the first embodiment, and the second semiconductor A wire 206 is connected between each bonding pad formed on the upper surface of the chip 204 and the conductive circuit pattern on the second substrate 202, and includes the second semiconductor chip 204 and the wire 206. The molding region on the second substrate 202 is molded with a resin to form a second molding resin 208 layer, thereby completing the second semiconductor package 200.

제1 및 제2반도체 패키지를 적층하는 공정Laminating the first and second semiconductor packages

소잉에 의하여 독립적인 리드가 되면서, 그라인딩에 의하여 외부로 노출된 각 리드(404)의 패드(406)와, 상기 제2기판(202)의 저면에 형성된 볼랜드간을 전도성 연결수단(408) 예를들어 솔더볼, 플립 칩, 범프중 선택된 어느 하나를 매개로 하여 서로 전기적 신호 교환 가능하게 연결함으로써, 제1반도체 패키지(100)의 위에 제2반도체 패키지(200)가 적층된 적층형 패키지로 완성된다.As an independent lead by sawing, between the pad 406 of each lead 404 exposed to the outside by grinding and the ball land formed on the bottom surface of the second substrate 202, the conductive connecting means 408 For example, a solder ball, a flip chip, and bumps may be connected to each other through an electrical signal exchange method, thereby completing a stacked package in which the second semiconductor package 200 is stacked on the first semiconductor package 100.

이와 같이, 제2실시예에 따른 반도체 패키지도 제1실시예의 리드프레임과 그 구조만 다를 뿐, 제1반도체 패키지내에 내재시킨 리드프레임을 매개로 제2반도체 패키지를 적층 연결함으로써, 전체 패키지의 안정성을 제공함과 더불어 상부 및 하부 반도체 패키지간의 간격을 줄일 수 있고, 전기 전도도가 우수한 구리 재질의 리드프레임을 이용하므로 전기적 신호 교환에 대한 신뢰성을 향상시킬 수 있다.As described above, the semiconductor package according to the second embodiment differs only from the structure of the lead frame of the first embodiment, and the second semiconductor package is stacked and connected through the lead frame embedded in the first semiconductor package, thereby ensuring stability of the entire package. In addition, the gap between the upper and lower semiconductor packages may be reduced, and a lead frame made of copper having excellent electrical conductivity may be used to improve reliability of electrical signal exchange.

도 1은 본 발명에 따른 반도체 패키지 및 그 제조 방법의 제1실시예를 순서대로 설명하는 단면도,1 is a cross-sectional view sequentially illustrating a first embodiment of a semiconductor package and a method of manufacturing the same according to the present invention;

도 2는 본 발명에 따른 반도체 패키지 및 그 제조 방법의 제2실시예를 순서대로 설명하는 단면도,2 is a cross-sectional view sequentially illustrating a second embodiment of a semiconductor package and a method of manufacturing the same according to the present invention;

도 3은 종래의 PoP 패키지에 대한 일례를 설명하는 개략적 단면도.3 is a schematic cross-sectional view illustrating an example of a conventional PoP package.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

100 : 제1반도체 패키지 102 : 제1기판100: first semiconductor package 102: first substrate

104 : 제1반도체 칩 106 : 플립 칩104: first semiconductor chip 106: flip chip

108 : 제1몰딩수지 200 : 제2반도체 패키지108: first molding resin 200: second semiconductor package

202 : 제2기판 204 : 제2반도체 칩202: second substrate 204: second semiconductor chip

206 : 와이어 208 : 제2몰딩수지206: wire 208: second molding resin

300 : 리드프레임 302 : 내부지지틀300: lead frame 302: inner support frame

304 : 리드 306 : 패드304: Lead 306: Pad

308 : 전도성 연결수단 400 : 리드프레임308: conductive connecting means 400: lead frame

402 : 외부지지틀 404 : 리드402: outer support frame 404: lead

406 : 패드 408 : 전도성 연결수단406: pad 408: conductive connecting means

Claims (9)

제1기판 상에 부착된 제1반도체 칩, 상기 제1반도체 칩과 제1기판상의 전도성회로패턴간을 연결하는 플립 칩, 상기 제1반도체 칩과 플립 칩을 포함하는 제1기판상의 몰딩영역에 몰딩된 제1몰딩수지, 상단은 상기 제1몰딩수지의 상면과 평행을 이루며 외부로 노출되고 그 하단은 다운셋되어 상기 제1반도체 칩의 바깥쪽으로 연장되면서 상기 제1기판상의 전도성회로패턴에 접속 연결되는 리드프레임, 상기 제1기판의 저면에 형성된 볼랜드에 융착되어 제1반도체 칩의 입출력단자가 되는 제1솔더볼, 을 포함하는 제1반도체 패키지와;A first semiconductor chip attached to a first substrate, a flip chip connecting between the first semiconductor chip and a conductive circuit pattern on the first substrate, and a molding region on the first substrate including the first semiconductor chip and the flip chip. Molded first molding resin, the upper end is parallel to the upper surface of the first molding resin exposed to the outside and the lower end is downset to extend to the outside of the first semiconductor chip connected to the conductive circuit pattern on the first substrate A first semiconductor package including a lead frame connected to each other, a first solder ball fused to a ball land formed on a bottom surface of the first substrate to become an input / output terminal of a first semiconductor chip; 제2기판 상에 부착된 제2반도체 칩, 상기 제2반도체 칩과 제2기판상의 전도성회로패턴간을 연결하는 와이어, 상기 제2반도체 칩과 와이어를 포함하는 제2기판상의 몰딩영역에 몰딩된 제2몰딩수지, 를 포함하는 제2반도체 패키지;A second semiconductor chip attached to the second substrate, a wire connecting the second semiconductor chip and the conductive circuit pattern on the second substrate, and molded in a molding region on the second substrate including the second semiconductor chip and the wire. A second semiconductor package comprising a second molding resin; 를 적층 구성하되,To be laminated, 외부로 노출된 상기 리드프레임의 상단면과, 상기 제2기판의 저면에 형성된 볼랜드간을 전도성 연결수단으로 연결하여서, 상기 제1 및 제2반도체 패키지가 적층 구성된 것을 특징으로 하는 반도체 패키지.The first and second semiconductor packages are laminated by connecting between the upper surface of the lead frame exposed to the outside and the ball land formed on the bottom surface of the second substrate by conductive connecting means. 청구항 1에 있어서, 상기 리드프레임은:The method of claim 1, wherein the leadframe is: 내부지지틀과, 이 내부지지틀의 외측 사방 모서리로부터 일체로 연장된 복수 의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 구성된 것을 특징으로 하는 반도체 패키지.A semiconductor package comprising an inner support frame, a plurality of leads integrally extending from the outer four corners of the inner support frame, and pads protruding integrally on the leads. 청구항 1 또는 청구항 2에 있어서, 상기 리드프레임의 내부지지틀은 그라인딩에 의하여 제거되는 동시에 내부지지틀과 인접한 리드의 상단이 상기 제1몰딩수지의 상면과 평행을 이루며 외부로 노출되고, 리드의 하단은 다운셋되어 상기 제1기판상의 전도성회로패턴에 접속 연결되는 것을 특징으로 하는 반도체 패키지.The inner support frame of the lead frame is removed by grinding, and the upper end of the lead adjacent to the inner support frame is exposed to the outside in parallel with the upper surface of the first molding resin, and the lower end of the lead frame. Is downset and connected to the conductive circuit pattern on the first substrate. 청구항 1에 있어서, 상기 리드프레임은: The method of claim 1, wherein the leadframe is: 외부지지틀과, 이 외부지지틀의 내측 사방 모서리로부터 안쪽 방향으로 연장되며 일체로 형성된 복수의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 구성된 것을 특징으로 하는 반도체 패키지.A semiconductor package, comprising: an outer support frame, a plurality of leads integrally formed in an inward direction from inner corners of the outer support frame, and pads integrally protruding on the leads. 청구항 1 또는 청구항 4에 있어서, 상기 리드프레임의 외부지지틀은 소잉에 의하여 제거되는 동시에 외부지지틀과 인접한 리드의 하단은 상기 제1기판상의 전도성회로패턴에 접속 연결되고, 리드의 상단은 상기 제1몰딩수지의 상면과 평행을 이루며 외부노 노출되는 것을 특징으로 하는 반도체 패키지.The method according to claim 1 or 4, wherein the outer support frame of the lead frame is removed by sawing, the lower end of the lead adjacent to the outer support frame is connected to the conductive circuit pattern on the first substrate, the upper end of the lead The semiconductor package, characterized in that the external furnace exposed in parallel with the upper surface of the one molding resin. 청구항 2 또는 청구항 4에 있어서, 상기 리드프레임의 각 리드의 상단면에는 외부로 노출되어 상기 전도성 연결수단과 접속되는 패드가 일체로 더 돌출 형성된 것을 특징으로 하는 반도체 패키지.The semiconductor package according to claim 2 or 4, wherein a pad connected to the conductive connecting means is further protruded integrally from the top surface of each lead of the lead frame. 청구항 1에 있어서, 상기 전도성 연결수단은 솔더볼, 플립 칩, 범프중 선택된 어느 하나인 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the conductive connecting means is any one selected from solder balls, flip chips, and bumps. ⅰ) 하부에 위치되는 제1반도체 패키지 제조 공정과, ⅱ) 상부에 적층되는 제2반도체 패키지 제조 공정과, ⅲ) 상기 제1 및 제2반도체 패키지를 적층하는 공정, 으로 이루어지되,Iii) a process of manufacturing the first semiconductor package located at the bottom, ii) a process of manufacturing the second semiconductor package stacked at the top, and iii) laminating the first and second semiconductor packages, ⅰ) 상기 제1반도체 패키지 제조 공정은:Iii) The first semiconductor package manufacturing process is: 제1기판 상에 제1반도체 칩을 부착하고, 상기 제1반도체 칩과 제1기판상의 전도성회로패턴간을 플립 칩으로 전기적 신호 교환 가능하게 연결하는 단계와; Attaching a first semiconductor chip on a first substrate, and electrically connecting the first semiconductor chip to a conductive circuit pattern on the first substrate so as to be electrically exchanged with a flip chip; 내부지지틀과, 이 내부지지틀의 외측 사방 모서리로부터 일체로 연장된 복수의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 이루어진 리드프레임을 구비하여, 각 리드의 하단은 제1기판의 전도성패턴에 연결하는 동시에 리드의 상단 및 내 부지지틀을 제1반도체 칩의 테두리 위쪽으로 이격 배치하는 단계와;A lead frame comprising an inner support frame, a plurality of leads integrally extending from the outer four corners of the inner support frame, and a pad integrally protruding on the leads, the lower ends of each lead being conductive to the first substrate. Disposing the top and the inner support frame of the lead spaced above the edge of the first semiconductor chip while connecting to the pattern; 상기 제1반도체 칩과, 플립 칩과, 리드프레임을 내재시키면서 상기 제1기판상의 몰딩영역을 수지로 몰딩하여 제1몰딩수지층을 형성하는 단계와; Forming a first molding resin layer by molding a molding region on the first substrate with a resin while embedding the first semiconductor chip, the flip chip, and the lead frame; 상기 제1몰딩수지의 상면을 그라인딩 수단으로 그라인딩하되, 그 안쪽의 내부지지틀까지 그라인딩하여, 내부지지틀의 제거와 함께 각 리드가 독립적인 리드로 분리되면서 그 패드가 외부로 노출되는 단계; 로 이루어지고,Grinding the upper surface of the first molding resin with grinding means, and grinding the inner support frame therein to expose the pad to the outside while removing the inner support frame and separating each lead into independent leads; Made up of ⅱ) 상기 제2반도체 패키지 제조 공정은: Ii) The second semiconductor package manufacturing process is: 제2기판 상에 제2반도체 칩을 부착하고, 상기 제2반도체 칩과 제2기판상의 전도성회로패턴간을 와이어로 연결하는 단계와; Attaching a second semiconductor chip on a second substrate and connecting the second semiconductor chip with a conductive circuit pattern on the second substrate with a wire; 상기 제2반도체 칩과 와이어를 포함하는 제2기판상의 몰딩영역을 수지로 몰딩하여 제2몰딩수지층을 형성하는 단계; 로 이루어지며,Molding a molding region on a second substrate including the second semiconductor chip and wire with a resin to form a second molding resin layer; It consists of ⅲ) 상기 제1 및 제2반도체 패키지를 적층하는 공정은:Iii) laminating the first and second semiconductor packages: 그라인딩에 의하여 외부로 노출된 상기 리드프레임의 각 리드의 패드와, 상기 제2기판의 저면에 형성된 볼랜드간을 전도성 연결수단으로 연결하여 이루어지는 것을 특징으로 하는 반도체 패키지 제조 방법.The method of manufacturing a semiconductor package, characterized in that the connection between the pad of each lead of the lead frame exposed to the outside by the grinding and the borland formed on the bottom surface of the second substrate by a conductive connecting means. ⅰ) 하부에 위치되는 제1반도체 패키지 제조 공정과, ⅱ) 상부에 적층되는 제2반도체 패키지 제조 공정과, ⅲ) 상기 제1 및 제2반도체 패키지를 적층하는 공정, 으로 이루어지되,Iii) a process of manufacturing the first semiconductor package located at the bottom, ii) a process of manufacturing the second semiconductor package stacked at the top, and iii) laminating the first and second semiconductor packages, ⅰ) 상기 제1반도체 패키지 제조 공정은:Iii) The first semiconductor package manufacturing process is: 제1기판 상에 제1반도체 칩을 부착하고, 상기 제1반도체 칩과 제1기판상의 전도성회로패턴간을 플립 칩으로 전기적 신호 교환 가능하게 연결하는 단계와; Attaching a first semiconductor chip on a first substrate, and electrically connecting the first semiconductor chip to a conductive circuit pattern on the first substrate so as to be electrically exchanged with a flip chip; 외부지지틀과, 이 외부지지틀의 내측 사방 모서리로부터 안쪽 방향으로 연장되며 일체로 형성된 복수의 리드와, 이 리드상에 일체로 돌출 형성된 패드로 이루어진 리드프레임을 구비하는 단계와;Providing an outer support frame, a plurality of leads integrally formed in one direction and extending inwardly from inner corners of the outer support frame, and a lead frame comprising pads integrally formed on the leads; 상기 리드프레임의 외부지지틀은 제1기판의 끝단 상면상에 지지시키고, 외부지지틀과 인접한 각 리드의 하단은 제1기판의 전도성패턴에 연결시키며, 각 리드의 상단은 제1반도체 칩의 테두리 위쪽으로 이격 배치하는 단계와;The outer support frame of the lead frame is supported on the upper end of the first substrate, the lower end of each lead adjacent to the outer support frame is connected to the conductive pattern of the first substrate, the upper end of each lead is the edge of the first semiconductor chip Spacing upwardly; 상기 제1반도체 칩과, 플립 칩과, 리드프레임을 내재시키면서 상기 제1기판상의 몰딩영역을 수지로 몰딩하여 제1몰딩수지층을 형성하는 단계와;Forming a first molding resin layer by molding a molding region on the first substrate with a resin while embedding the first semiconductor chip, the flip chip, and the lead frame; 상기 제1몰딩수지의 상면을 그라인딩 수단으로 그라인딩하되, 그 내부의 존재하는 각 리드의 패드가 노출될 때까지 그라인딩하는 단계와;Grinding the upper surface of the first molding resin by grinding means, but grinding the pads of the respective leads existing therein to be exposed; 상기 제1몰딩수지의 테두리단 및 상기 제1기판의 테두리단을 소잉하는 동시에 상기 기판의 끝단에 지지된 상기 리드프레임의 외부지지틀도 함께 소잉으로 제거되어, 각 리드가 독립적인 리드로 분리되는 단계; 로 이루어지고,At the same time, the edge of the first molding resin and the edge of the first substrate are sawed, and the outer support frame of the lead frame supported at the end of the substrate is also sawed off so that each lead is separated into an independent lead. step; Made up of ⅱ) 상기 제2반도체 패키지 제조 공정은:Ii) The second semiconductor package manufacturing process is: 제2기판 상에 제2반도체 칩을 부착하고, 상기 제2반도체 칩과 제2기판상의 전도성회로패턴간을 와이어로 연결하는 단계와;Attaching a second semiconductor chip on a second substrate and connecting the second semiconductor chip with a conductive circuit pattern on the second substrate with a wire; 상기 제2반도체 칩과 와이어를 포함하는 제2기판상의 몰딩영역을 수지로 몰 딩하여 제2몰딩수지층을 형성하는 단계; 로 이루어지며,Molding a molding region on a second substrate including the second semiconductor chip and a wire with a resin to form a second molding resin layer; It consists of ⅲ) 상기 제1 및 제2반도체 패키지를 적층하는 공정은:Iii) laminating the first and second semiconductor packages: 그라인딩에 의하여 외부로 노출된 상기 리드프레임의 각 리드의 패드와, 상기 제2기판의 저면에 형성된 볼랜드간을 전도성 연결수단으로 연결하여 이루어지는 것을 특징으로 하는 반도체 패키지 제조 방법.The method of manufacturing a semiconductor package, characterized in that the connection between the pad of each lead of the lead frame exposed to the outside by the grinding and the borland formed on the bottom surface of the second substrate by a conductive connecting means.
KR1020070122401A 2007-11-29 2007-11-29 Semiconductor package and method for manufacturing the same KR100886100B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070122401A KR100886100B1 (en) 2007-11-29 2007-11-29 Semiconductor package and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070122401A KR100886100B1 (en) 2007-11-29 2007-11-29 Semiconductor package and method for manufacturing the same

Publications (1)

Publication Number Publication Date
KR100886100B1 true KR100886100B1 (en) 2009-02-27

Family

ID=40682208

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070122401A KR100886100B1 (en) 2007-11-29 2007-11-29 Semiconductor package and method for manufacturing the same

Country Status (1)

Country Link
KR (1) KR100886100B1 (en)

Cited By (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101219086B1 (en) * 2011-03-07 2013-01-11 (주) 윈팩 Package module
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8623706B2 (en) 2010-11-15 2014-01-07 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8728865B2 (en) 2005-12-23 2014-05-20 Tessera, Inc. Microelectronic packages and methods therefor
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9299631B2 (en) 2013-09-27 2016-03-29 Samsung Electronics Co., Ltd. Stack-type semiconductor package
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9553076B2 (en) 2010-07-19 2017-01-24 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030055834A (en) * 2001-12-27 2003-07-04 삼성전자주식회사 Ball grid array type semiconductor chip package using leadframe and stack package
JP2007221118A (en) 2006-02-16 2007-08-30 Samsung Electro-Mechanics Co Ltd Package-on-package with cavity formed and its manufacturing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030055834A (en) * 2001-12-27 2003-07-04 삼성전자주식회사 Ball grid array type semiconductor chip package using leadframe and stack package
JP2007221118A (en) 2006-02-16 2007-08-30 Samsung Electro-Mechanics Co Ltd Package-on-package with cavity formed and its manufacturing method

Cited By (102)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8927337B2 (en) 2004-11-03 2015-01-06 Tessera, Inc. Stacked packaging improvements
US9570416B2 (en) 2004-11-03 2017-02-14 Tessera, Inc. Stacked packaging improvements
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
US8531020B2 (en) 2004-11-03 2013-09-10 Tessera, Inc. Stacked packaging improvements
US9153562B2 (en) 2004-11-03 2015-10-06 Tessera, Inc. Stacked packaging improvements
US9218988B2 (en) 2005-12-23 2015-12-22 Tessera, Inc. Microelectronic packages and methods therefor
US9984901B2 (en) 2005-12-23 2018-05-29 Tessera, Inc. Method for making a microelectronic assembly having conductive elements
US8728865B2 (en) 2005-12-23 2014-05-20 Tessera, Inc. Microelectronic packages and methods therefor
US9123664B2 (en) 2010-07-19 2015-09-01 Tessera, Inc. Stackable molded microelectronic packages
US9553076B2 (en) 2010-07-19 2017-01-24 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
US9570382B2 (en) 2010-07-19 2017-02-14 Tessera, Inc. Stackable molded microelectronic packages
US8907466B2 (en) 2010-07-19 2014-12-09 Tessera, Inc. Stackable molded microelectronic packages
US8637991B2 (en) 2010-11-15 2014-01-28 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8957527B2 (en) 2010-11-15 2015-02-17 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8659164B2 (en) 2010-11-15 2014-02-25 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8623706B2 (en) 2010-11-15 2014-01-07 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
KR101219086B1 (en) * 2011-03-07 2013-01-11 (주) 윈팩 Package module
US9691731B2 (en) 2011-05-03 2017-06-27 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10593643B2 (en) 2011-05-03 2020-03-17 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US11424211B2 (en) 2011-05-03 2022-08-23 Tessera Llc Package-on-package assembly with wire bonds to encapsulation surface
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9093435B2 (en) 2011-05-03 2015-07-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US9105483B2 (en) 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
US9252122B2 (en) 2011-10-17 2016-02-02 Invensas Corporation Package-on-package assembly with wire bond vias
US9761558B2 (en) 2011-10-17 2017-09-12 Invensas Corporation Package-on-package assembly with wire bond vias
US9041227B2 (en) 2011-10-17 2015-05-26 Invensas Corporation Package-on-package assembly with wire bond vias
US10756049B2 (en) 2011-10-17 2020-08-25 Invensas Corporation Package-on-package assembly with wire bond vias
US11189595B2 (en) 2011-10-17 2021-11-30 Invensas Corporation Package-on-package assembly with wire bond vias
US11735563B2 (en) 2011-10-17 2023-08-22 Invensas Llc Package-on-package assembly with wire bond vias
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US10170412B2 (en) 2012-05-22 2019-01-01 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US10510659B2 (en) 2012-05-22 2019-12-17 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9917073B2 (en) 2012-07-31 2018-03-13 Invensas Corporation Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package
US10297582B2 (en) 2012-08-03 2019-05-21 Invensas Corporation BVA interposer
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US9615456B2 (en) 2012-12-20 2017-04-04 Invensas Corporation Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9095074B2 (en) 2012-12-20 2015-07-28 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9633979B2 (en) 2013-07-15 2017-04-25 Invensas Corporation Microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9299631B2 (en) 2013-09-27 2016-03-29 Samsung Electronics Co., Ltd. Stack-type semiconductor package
US9893033B2 (en) 2013-11-12 2018-02-13 Invensas Corporation Off substrate kinking of bond wire
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10629567B2 (en) 2013-11-22 2020-04-21 Invensas Corporation Multiple plated via arrays of different wire heights on same substrate
US10290613B2 (en) 2013-11-22 2019-05-14 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
USRE49987E1 (en) 2013-11-22 2024-05-28 Invensas Llc Multiple plated via arrays of different wire heights on a same substrate
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US11404338B2 (en) 2014-01-17 2022-08-02 Invensas Corporation Fine pitch bva using reconstituted wafer with area array accessible for testing
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US11990382B2 (en) 2014-01-17 2024-05-21 Adeia Semiconductor Technologies Llc Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10529636B2 (en) 2014-01-17 2020-01-07 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9837330B2 (en) 2014-01-17 2017-12-05 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9356006B2 (en) 2014-03-31 2016-05-31 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9812433B2 (en) 2014-03-31 2017-11-07 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US10032647B2 (en) 2014-05-29 2018-07-24 Invensas Corporation Low CTE component with wire bond interconnects
US10475726B2 (en) 2014-05-29 2019-11-12 Invensas Corporation Low CTE component with wire bond interconnects
US9947641B2 (en) 2014-05-30 2018-04-17 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US10806036B2 (en) 2015-03-05 2020-10-13 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US10559537B2 (en) 2015-10-12 2020-02-11 Invensas Corporation Wire bond wires for interference shielding
US10115678B2 (en) 2015-10-12 2018-10-30 Invensas Corporation Wire bond wires for interference shielding
US11462483B2 (en) 2015-10-12 2022-10-04 Invensas Llc Wire bond wires for interference shielding
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US10325877B2 (en) 2015-12-30 2019-06-18 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10658302B2 (en) 2016-07-29 2020-05-19 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor

Similar Documents

Publication Publication Date Title
KR100886100B1 (en) Semiconductor package and method for manufacturing the same
JP5447904B2 (en) Multi-chip package system and manufacturing method thereof
KR101814081B1 (en) Integrated circuit packaging system with package-on-package and method of manufacture thereof
US7429798B2 (en) Integrated circuit package-in-package system
KR100415279B1 (en) Chip stack package and manufacturing method thereof
US7829990B1 (en) Stackable semiconductor package including laminate interposer
US7615859B2 (en) Thin semiconductor package having stackable lead frame and method of manufacturing the same
US7105919B2 (en) Semiconductor package having ultra-thin thickness and method of manufacturing the same
KR20100050750A (en) Wafer level chip on chip package, package on package improving solder joint reliability but reducing mounting height and manufacturing method thereof
CN102194805A (en) Semiconductor package with stacked chips and method for manufacturing the same
US8294251B2 (en) Stacked semiconductor package with localized cavities for wire bonding
US8470640B2 (en) Method of fabricating stacked semiconductor package with localized cavities for wire bonding
US7687920B2 (en) Integrated circuit package-on-package system with central bond wires
JP2003318360A (en) Semiconductor device and method of manufacturing the same
KR20110055985A (en) Stack package
KR20090043945A (en) Stack package
KR20090036948A (en) Bga package and method for fabricating of the same
KR101141707B1 (en) Semiconductor package and method of manufacturing the same
TWI416699B (en) Stacked semiconductor package with localized cavities for wire bonding and fabricating method thereof
KR20110030089A (en) Semiconductor package and method for fabricating thereof
KR20090121011A (en) Stacked semiconductor package having film substrate and fabrication method thereof
KR20060005713A (en) Up-down type chip stack package
KR101019705B1 (en) Substrate for fabricating semiconductor package and semiconductor package using the same
KR20110030088A (en) Semiconductor package and method for fabricating thereof
KR101001207B1 (en) Lead Frame, and chip stack package and method for manufacturing the same

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130204

Year of fee payment: 5

FPAY Annual fee payment

Payment date: 20140204

Year of fee payment: 6

FPAY Annual fee payment

Payment date: 20150203

Year of fee payment: 7

FPAY Annual fee payment

Payment date: 20160202

Year of fee payment: 8

FPAY Annual fee payment

Payment date: 20170210

Year of fee payment: 9

FPAY Annual fee payment

Payment date: 20180207

Year of fee payment: 10

FPAY Annual fee payment

Payment date: 20190212

Year of fee payment: 11

FPAY Annual fee payment

Payment date: 20200224

Year of fee payment: 12