JP5471605B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device incorporating a semiconductor element and a method for manufacturing the same.

  As electronic devices continue to become lighter, thinner, and smaller, semiconductor devices themselves are becoming smaller and more integrated, and high-density mounting technology for semiconductor packages is advancing more and more. For the connection between the semiconductor element and the wiring board of the package, wire bonding connection using a gold wire or the like, or flip chip connection using a solder ball or the like is used.

  The wire bonding connection can be packaged at a low cost when the number of pads of the semiconductor element is small. However, it is necessary to reduce the wire diameter as the pitch of the pads of the semiconductor element is narrowed, and the yield reduction in the assembly process such as wire breakage is a problem.

  The flip-chip connection has an advantage that high-speed signal transmission between the semiconductor element and the wiring board is possible compared to the wire bonding connection. However, as the number of pads of the semiconductor element increases and the pitch is narrowed, the connection strength of the solder bumps is weakened, and defects such as the occurrence of cracks at the connection locations frequently occur.

  Therefore, in recent years, a package technology incorporating a semiconductor element, a so-called semiconductor element incorporation technology has been proposed (for example, Patent Documents 1 and 2). This technology is expected as a high-density packaging technology that realizes further high integration and high functionality of semiconductor devices, and realizes package thinning, low cost, high frequency response, low stress connection, improved electromigration characteristics, etc. ing.

  Patent Document 1 discloses a configuration in which a semiconductor chip built in an insulating substrate is electrically connected to wiring formed on the insulating substrate through bumps embedded in the insulating substrate.

  Patent Document 2 proposes a configuration in which a reinforcing structure is embedded in an outer peripheral region of a semiconductor chip in an insulating layer in which the semiconductor chip is embedded in order to suppress warping of the wiring board.

JP 2007-134568 A JP 2006-261246 A

  In Patent Document 1, a semiconductor element is flip-chip mounted on a thin rolled copper wiring layer to produce a built-in substrate. For this reason, there has been a problem that large warpage and undulation occur in the entire substrate during the flip chip mounting and in the subsequent built-in process using the insulating resin for the substrate.

  In Patent Document 2, as described above, a structure that suppresses the warpage of the entire substrate by embedding a reinforcing structure in an insulating layer around a built-in semiconductor element is disclosed. However, it is necessary to secure a space for arranging the reinforcing structure on the outer periphery of the semiconductor element. Therefore, it cannot be said that it is advantageous for miniaturization and high density of the semiconductor device. In addition, there was no suppression effect on the warp of the semiconductor element placement region where the reinforcing structure is not placed and the vicinity thereof (hereinafter referred to as “semiconductor element neighborhood”). Therefore, the effect on the warpage in the vicinity of the semiconductor element is not sufficient.

  The present invention has been made in view of the above problems, and an object of the present invention is to suppress warpage in the vicinity of a semiconductor element in a semiconductor device in which the semiconductor element is built in a substrate.

  A semiconductor device according to the present invention includes a semiconductor element including a semiconductor substrate, an insulating layer in which the semiconductor element is embedded, and a wiring structure at least partially connected to the semiconductor element. In the semiconductor substrate, one or a plurality of openings are formed on at least one main surface side of the semiconductor substrate as means for reducing the warpage amount of the semiconductor element.

  According to the semiconductor device of the present invention, in the semiconductor device in which the semiconductor element is built in the substrate, there is an excellent effect that warpage in the vicinity of the semiconductor element can be suppressed.

1 is a schematic cross-sectional view illustrating an example of a structure of a semiconductor device according to the present invention. FIG. 3 is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment. (A) The top view of the semiconductor substrate which concerns on Embodiment 1. FIG. (B) IIIB-IIIB cutting part sectional drawing in Fig.3 (a). The figure which plotted the amount of curvature of the semiconductor device concerning Embodiment 1 and comparative example 1. FIG. (A)-(f) The typical top view of the semiconductor substrate which concerns on a modification, and an opening part (board | substrate penetration part). (A)-(c) The typical top view of the semiconductor substrate which concerns on a modification, and an opening part (board | substrate penetration part). (A) The top view of the semiconductor substrate which concerns on a modification. (B) Sectional view taken along the line VIIB-VIIB in FIG. (A) The top view of the semiconductor substrate which concerns on a modification. (B) VIIIB-VIIIB cutting part sectional drawing in Fig.8 (a). FIG. 6 is a schematic cross-sectional view illustrating an example of a structure of a semiconductor device according to a second embodiment. (A) The top view of the semiconductor substrate which concerns on Embodiment 2. FIG. (B) XB-XB cutting part sectional drawing in Fig.10 (a). (A), (b) The typical cross section of the semiconductor substrate which concerns on a modification, and an opening part (board | substrate counterbore part). FIG. 6 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to a third embodiment. (A)-(e) Manufacturing process sectional drawing of the semiconductor device which concerns on Embodiment 3. FIG. FIG. 9 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to Modification 3-1. FIG. 14 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to Modification 3-2. FIG. 6 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to a fourth embodiment. FIG. 6 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to a fifth embodiment. 9 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to Embodiment 6. FIG. FIG. 10 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to a seventh embodiment. FIG. 10 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to an eighth embodiment. (A)-(e) Manufacturing process sectional drawing of the semiconductor device which concerns on Embodiment 8. FIG. (F)-(h) Manufacturing process sectional drawing of the semiconductor device which concerns on Embodiment 8. FIG. 10 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to Embodiment 9. FIG. (A)-(c) Manufacturing process sectional drawing of the semiconductor device which concerns on Embodiment 9. FIG. (D), (e) Manufacturing process sectional drawing of the semiconductor device which concerns on Embodiment 9. FIG. (F), (g) Manufacturing process sectional drawing of the semiconductor device which concerns on Embodiment 9. FIG. 6 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to Comparative Example 1. FIG. 10 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to Comparative Example 2. FIG.

  FIG. 1 shows a schematic cross-sectional view of a main part of a semiconductor device 50A according to the present invention. A semiconductor device 50 </ b> A according to the present invention includes a semiconductor element 1, an insulating layer 10, and a wiring structure 20. The semiconductor element 1 includes a semiconductor substrate 2. Electronic circuits (not shown) and pads (not shown) are formed on the element formation surface of the semiconductor substrate 2. Further, one or a plurality of openings 3A are formed in the semiconductor substrate 2 so as to reduce the warp of the semiconductor element 1 in the semiconductor device 50A. Although the opening 3 </ b> A in FIG. 1 is illustrated as penetrating the semiconductor substrate 2, it may not be penetrating.

  The insulating layer 10 is formed so as to embed the semiconductor element 1. The wiring structure 20 is formed so as to be at least partially connected to the semiconductor element 1.

  Hereinafter, more specific embodiments of the present invention will be described with reference to the drawings. Note that, in a plurality of embodiments, the same element member is denoted by the same reference numeral, and repeated description is appropriately omitted. Moreover, the size and ratio of each member are for convenience of explanation and do not necessarily match the actual ones.

[Embodiment 1]
FIG. 2 is a schematic cross-sectional view of the semiconductor device 50 according to the first embodiment of the present invention. As shown in the figure, the semiconductor device 50 includes a semiconductor element 1, an insulating layer 10, and a wiring structure 20. The semiconductor element 1 is embedded in the insulating layer 10. The semiconductor element 1 includes a semiconductor substrate 2 that is thinly ground. Elements such as electronic circuits (not shown) and pads (not shown) are formed on the first main surface 2A side of the semiconductor substrate 2.

  The semiconductor substrate 2 is provided with a plurality of substrate through portions 3 as openings. The substrate penetration part 3 plays a role of reducing the warpage amount of the semiconductor element 1 that warps in the direction opposite to the warping direction of the entire semiconductor device (insulating layer). In FIG. 2, an example in which a plurality of substrate through-holes 3 are provided will be described, but one substrate through-hole 3 may be formed on the semiconductor substrate 2.

  For example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), gallium arsenide phosphorus (GaAsP), gallium nitride (GaN), silicon carbide (SiC), or zinc oxide (ZnO) is applied to the semiconductor substrate 2. be able to. In addition, II-VI group compounds, III-V group compounds, diamond, or the like exhibiting semiconductor characteristics may be used. Of course, it is not limited to these. In the first embodiment, silicon is used as the semiconductor substrate 2.

  The thickness of the semiconductor substrate 2 can be appropriately adjusted according to the thickness required for the semiconductor device 50. In the first embodiment, the thickness of the semiconductor substrate 2 is 50 μm, and the chip size is 10 mm square. The overall size of the semiconductor device 50 was 30 mm square. The number of semiconductor elements 1 incorporated in the semiconductor device 50 is not limited to one, and a plurality of semiconductor elements 1 can be provided. As a method of arranging a plurality of semiconductor elements, a plurality of semiconductor elements 1 may be stacked in the Y direction in FIG. 2 in addition to an aspect in which a plurality of semiconductor elements are arranged in the X direction in FIG.

  FIG. 3A is a schematic plan view when viewed from the first main surface 2A side of the semiconductor substrate 2. FIG. 3B is a cross-sectional view taken along the line IIIB-IIIB in FIG.

  As shown in FIG. 3A, the substrate penetrating part 3 according to the first embodiment has a square shape in plan view, and is arranged in the semiconductor substrate 2. Specifically, one through-substrate portion 3 is disposed in the vicinity of the corner portion of the semiconductor substrate 2, and one is disposed in the central portion of the semiconductor substrate 2.

  The position where the substrate penetration part 3 is disposed is not particularly limited. However, from the viewpoint of more effectively reducing the warpage of the semiconductor element in the semiconductor device, it is preferable to provide the substrate through portion 3 in the vicinity of the outer peripheral portion of the semiconductor substrate 2 that is the stress concentration position. Further, from the viewpoint of dispersing the partial stress concentration in the semiconductor substrate 2, it is preferable that the semiconductor substrate 2 be arranged point-symmetrically or line-symmetrically in plan view. More preferably, it is point-symmetric and line-symmetric as in the substrate penetration part 3 of the first embodiment. However, the above-described point symmetry and line symmetry may be arranged in consideration of the arrangement of electronic circuits formed in the semiconductor element 1, and are not limited to exact arrangement.

  The individual shape of the substrate penetration part 3 is not particularly limited, and may be, for example, a circular shape, a polygonal shape such as a rectangle, a shape surrounded by a curve, or a combination thereof. Although the diameter of the substrate penetration part 3 is not specifically limited, For example, it can be set as about 10 micrometers-100 micrometers. The substrate penetrating portion 3 may be formed in advance in the semiconductor substrate 2 or may be formed after the semiconductor element 1 is formed.

  The shape of the substrate through-holes 3 arranged in one semiconductor element 1 is not limited to the same shape, and a plurality of substrate through-holes 3 having a plurality of shapes may be mixed. The diameter of the substrate penetrating portion 3 is not particularly limited, and may be determined from the viewpoint of reducing the amount of warp while considering the thickness, area, etc. of the semiconductor substrate. In the first embodiment, the rectangular substrate penetrating portion 3 having an outer diameter of 50 μm is used.

  The substrate penetrating part 3 may be a gap, or a part or all of the substrate penetrating part 3 may be filled with the filler 6. As the filler 6, an insulating material can be suitably applied. From the viewpoint of increasing the mechanical strength, a structure filled with the filler 6 is preferable. When the semiconductor substrate 2 is, for example, silicon, it is preferable to use a filler 6 having an elastic modulus of 5 MPa or more and 5 GPa or less. Thereby, the curvature of a semiconductor element can be reduced effectively. More preferable fillers 6 have an elastic modulus of 10 MPa or more and 2 GPa or less.

  Although the filler 6 is not specifically limited, As a suitable example, the following resin group A which shows the low elasticity characteristic can be mentioned. That is, as the resin group A, epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole), polynorbornene resin, and the like can be listed. Further, the resin group A or a silicon resin obtained by adding an inorganic filler or an organic filler may be used as the filler 6. Further, a composite material in which metal fine particles are added in the resin matrix of the resin group A or silicon resin may be used. Of course, it is not limited to these, and inorganic materials can also be suitably applied.

  The substrate penetration part 3 can be formed by, for example, a D-RIE (Deep-Reactive Ion Etching) method or a laser method. Of course, it is not limited to this. In the first embodiment, the substrate penetrating part 3 is formed by the D-RIE method, and an epoxy resin having an elastic modulus of 1.9 GPa is filled in these.

  The insulating layer 10 includes a first insulating layer 11 and an adhesive layer 19. In other words, the semiconductor element 1 is embedded in the first insulating layer 11 and the adhesive layer 19. Specifically, the second main surface 2 </ b> B side of the semiconductor substrate 2 is in contact with the adhesive layer 19, and other regions are covered with the first insulating layer 11. In the first embodiment, the adhesive layer 19 is substantially the same as the semiconductor substrate 2 in plan view.

  The first insulating layer 11 can be formed using, for example, a photosensitive or non-photosensitive organic material. As the organic material, for example, the resin group A can be applied. Alternatively, a material obtained by impregnating a woven fabric or a non-woven fabric formed of glass cloth, aramid fiber, or the like with a resin selected from the resin group A may be used. Alternatively, a resin selected from the resin group A or a silicon resin containing an inorganic filler or an organic filler may be used. Of course, the present invention is not limited to these, and various materials including inorganic materials can be applied without departing from the spirit of the present invention. In the first embodiment, an epoxy resin having a thickness of 90 μm is used as the first insulating layer 11.

  For example, the adhesive layer 19 is preferably a semi-cured resin called a die attachment film (DAF), a resin paste such as epoxy resin, polyimide resin, BCB (benzocyclobutene), PBO (polybenzoxazole), or silver paste. It is. Of course, it is not limited to these. In the first embodiment, DAF mainly composed of epoxy resin is used.

  The wiring structure 20 includes a first wiring layer 21 and an element connection plug 30 in the first embodiment. The first wiring layer 21 is provided on the first main surface 11 </ b> A of the first insulating layer 11. The element connection plug 30 plays a role of connecting the first wiring layer 21 and a pad (not shown) formed in the semiconductor element 1.

  The element connection plug 30 is obtained by filling a conductor into a via 41 penetrating from the surface of the first insulating layer 11 to a pad (not shown) of the semiconductor element 1. The element connection plug 30 can be formed simultaneously with the formation of the first wiring layer 21 by forming a via in the first insulating layer 11 by laser, for example. Moreover, what formed the metal bump etc. previously in the semiconductor element 1 can be applied suitably as the element connection plug 30. FIG. In the first embodiment, the via 41 is opened using a laser, and the via 41 is filled with copper by plating.

  The first wiring layer 21 is, for example, at least one metal selected from the group consisting of copper, silver, gold, nickel, aluminum, titanium, molybdenum, tungsten, and palladium, or an alloy containing these as a main component, or A conductive resin made of a resin containing a conductive filler is suitable, but is not limited thereto. From the viewpoint of electrical resistance value and cost, it is desirable to form with copper. In the first embodiment, copper is used as the first wiring layer 21.

<Comparative Example 1>
Here, in order to explain the effect of the present invention, a semiconductor device according to a comparative example will be described. FIG. 27 is a cross-sectional view of a main part of the semiconductor device 150 according to Comparative Example 1. The semiconductor device 150 according to the comparative example 1 includes the semiconductor element 101. The semiconductor element 101 includes a semiconductor substrate 102. The semiconductor device 150 has the same configuration as that of the first embodiment, except that an opening (substrate through-hole) is not provided in the thickness direction of the semiconductor substrate 102. That is, the semiconductor element 101 is built in the insulating layer 110. A pad (not shown) provided on the first main surface 102A of the semiconductor substrate 102 is connected to the first wiring 121 of the wiring structure 120 via the element connection plug 130.

  The present inventors have made extensive studies and found that the semiconductor device 150 according to Comparative Example 1 has the following problems. That is, by incorporating the semiconductor element 101 in the insulating layer 110, the entire semiconductor device 150 has a downwardly convex warp shape, while the region where the semiconductor element 1 is disposed and its vicinity (hereinafter referred to as “semiconductor element 1 vicinity”). It has been found that this is a convex warpage.

  In the semiconductor device 150, the insulating layer 110 contracts during curing due to a large thermal expansion coefficient of the insulating layer 110, and generates a convex warp downward. However, a reverse warp occurs around the semiconductor element 101 due to a small thermal expansion coefficient of the semiconductor substrate. Accordingly, the entire semiconductor device has a downward convex warp, and an upward convex warp in the vicinity of the semiconductor element.

  Since the warpage of the entire semiconductor device 150 and the local warpage in the vicinity of the semiconductor element 101 are in opposite directions, internal stress is concentrated in the vicinity of the outer peripheral portion of the semiconductor element 101. As a result, in a reliability evaluation test such as a temperature cycle test, cracks occurred in the insulating layer 110 around the outer peripheral portion of the semiconductor element 101 when the number of cycles was less than a predetermined number, and an open failure of the first wiring layer 121 occurred. .

<Comparative example 2>
FIG. 28 is a cross-sectional view of a semiconductor device 150a according to Comparative Example 2. The basic configuration of the semiconductor device 150a according to the comparative example 2 is the same as that of the comparative example 1 except for the following points. That is, the semiconductor device 150a according to Comparative Example 2, the thickness _{d 2} of the semiconductor substrate 102a is different in that a thin compared to the thickness _{d 1} of the semiconductor substrate 102 of Comparative Example 1.

According to Comparative Example 2, since the thinner than the thickness d ₁ of the semiconductor substrate 102 of Comparative Example 1 the thickness d ₂ of the semiconductor substrate 102a, slightly reducing bent upwardly convex near the semiconductor element 101 It becomes possible to do. This is because the volume of the semiconductor substrate 102a having the smallest thermal expansion coefficient in the entire system is reduced. However, since the semiconductor substrate 102a is thinned as a whole, the handling property in the manufacturing process is inevitably deteriorated. For this reason, cracking defects and chipping defects occurred frequently in the peripheral portion of the semiconductor element 101a.

  FIG. 4 shows the position dependency of the warpage amount of the semiconductor device according to the first embodiment and the comparative example 1. The dotted line in the figure is the warp profile of the semiconductor device according to Comparative Example 1, and the solid line in the figure is the warp profile of the semiconductor device according to the first embodiment.

  As shown in FIG. 4, according to the semiconductor device 50 of the first embodiment, it can be seen that the warpage can be effectively reduced as compared with the first comparative example. Specifically, compared to Comparative Example 1, a warpage amount of approximately ½ or less can be realized. In the first embodiment, it is found that by providing the substrate through portion 3 in the semiconductor substrate 2, the warpage in the vicinity of the semiconductor element 1 can be effectively reduced and the warpage amount of the entire semiconductor device 50 can be reduced. It was.

  About the semiconductor device which concerns on Embodiment 1 and the comparative example 1, the temperature cycle test was implemented. Specifically, a temperature cycle test of −55 ° C. to + 125 ° C. was performed. The temperature was held at −55 ° C. and 125 ° C. for 10 minutes.

  In the semiconductor device according to Comparative Example 1, an open defect occurred in the vicinity of 500 cycles. On the other hand, in the semiconductor device of Embodiment 1, it was confirmed that no defect occurred even after 2000 cycles. It is considered that this is because the internal stress of the semiconductor element 1 is reduced by the substrate penetration part 3 of the semiconductor substrate 2 and the warpage of the entire semiconductor device (insulating layer) is reduced.

  According to the semiconductor device 50 according to the first embodiment, since the warpage and undulation of the semiconductor element built-in substrate incorporating the semiconductor element can be suppressed, the reliability can be improved. In particular, the temperature cycle test characteristics can be improved. Furthermore, since the wiring yield of the built-in substrate is improved due to the low warpage, the loss of discard of non-defective semiconductor elements due to wiring defects is reduced, and the manufacturing cost can be reduced. Furthermore, the low warpage makes it possible to further miniaturize the wiring of the built-in substrate, and to reduce the cost by reducing the number of wiring layers. Further, even if the semiconductor element is thinned, the strength of the semiconductor element is not deteriorated, and the entire thickness of the semiconductor element-embedded substrate can be reduced. Moreover, the handling property when the semiconductor element is thinned can be improved, and the manufacturing yield can be improved.

  Moreover, since the board | substrate penetration part 3 which concerns on this Embodiment 1 is filled with low elastic resin, the internal stress of the semiconductor element 1 can be reduced more effectively. Moreover, unlike Patent Document 2, it is not necessary to embed a reinforcing structure, which is advantageous for downsizing and increasing the density of a semiconductor device.

  The shape and arrangement of the substrate penetration part 3 can be variously modified without departing from the spirit of the present invention. FIG. 5A to FIG. 5F, FIG. 6A to FIG. 7C, FIG. 7A and FIG. 7B, and FIG. 8A and FIG. Indicates.

  The semiconductor substrate 2a shown in FIG. 5A has four rectangular substrate through portions 3a. The substrate penetrating portion 3a is disposed in the vicinity of the outer periphery of the semiconductor substrate 2a so as to be substantially parallel to the outer periphery. And these four board | substrate penetration parts 3a are arrange | positioned so that it may become substantially point symmetrical with respect to the center position of the semiconductor substrate 2a. Further, the semiconductor substrate 2a is arranged so as to be substantially line symmetric with respect to the bisector passing through the center point of the semiconductor substrate 2a.

  A semiconductor substrate 2b shown in FIG. 5B has a substrate penetrating portion 3b obtained by connecting two sides parallel to the corner portion of the semiconductor substrate 2b at the four corner portions of the semiconductor substrate 2b and the end points thereof by curves. Have And these four board | substrate penetration parts 3b are arrange | positioned so that it may become substantially point symmetrical with respect to the center position of the semiconductor substrate 2b. Further, the semiconductor substrate 2a is arranged so as to be substantially line symmetric with respect to the bisector passing through the center point of the semiconductor substrate 2a.

  The semiconductor substrate 2c shown in FIG. 5C has five circular substrate through-holes 3c. The substrate penetrating portion 3c is disposed at a corner portion of the semiconductor substrate 2c and a substantially central portion of the semiconductor substrate 2c. These five semiconductor substrate through-holes 3c are arranged so as to be substantially point-symmetric with respect to the center position of the semiconductor substrate 2c. Further, the semiconductor substrate 2c is arranged so as to be substantially line symmetric with respect to the bisector passing through the center point of the semiconductor substrate 2c.

  A semiconductor substrate 2d shown in FIG. 5D has twelve square substrate through portions 3d. The substrate penetration part 3d is provided at an arbitrary position of the semiconductor substrate 2d. Even if the arrangement is not line symmetric or does not satisfy line symmetry as in the substrate penetration part 3d, the effect of reducing stress can be sufficiently obtained. As described above, according to the method of forming the substrate through-hole (opening) at an arbitrary position, it is possible to appropriately adjust according to the circuit formation position and the pad formation position on the element formation surface. It has the advantage of a high degree of freedom.

  The semiconductor substrate 2e shown in FIG. 5E has four circular substrate through portions 3e and one square substrate through portion 3e '. As described above, a plurality of different shapes may be mixed as the substrate penetrating portion.

  A semiconductor substrate 2f shown in FIG. 5 (f) has one circular substrate through-hole 3f at a substantially central portion of the semiconductor substrate 2f. Thus, even if it is an example which provides one board penetration part 3f, the effect of stress reduction can be acquired. In addition, although the example provided in the substantially center part of the semiconductor substrate 2f was demonstrated as the board | substrate penetration part 3f, it is not limited to this position, It can provide in arbitrary positions.

  The semiconductor substrate 2g shown in FIG. 6A has a rectangular shape in plan view as shown in FIG. The semiconductor substrate 2g has six elliptical substrate through portions 3g. Three substrate penetrating portions 3g are arranged in the vicinity of the long side, and these six substrate penetrating portions 3g are arranged to be line-symmetric.

  The semiconductor substrate 2h shown in FIG. 6B has five elliptical substrate through portions 3h. Three substrate through-holes 3h are arranged in the vicinity of one long side of the semiconductor substrate 2h, and two substrate through-holes 3h are evenly arranged in the vertical direction with respect to the middle substrate through-hole 3h. Yes. These five substrate through-holes 3h are arranged so as to be generally line symmetric.

  The semiconductor substrate 2i shown in FIG. 6C has three circular substrate through portions 3i. The substrate penetrating portions 3 i are equally arranged on one diagonal line of the semiconductor substrate 2. That is, they are arranged so as to be substantially point-symmetric.

  The semiconductor substrate 2j shown in FIGS. 7A and 7B has a substrate through-hole 3j similar in shape to the substrate through-hole 3c in FIG. 5C in plan view. However, as shown in FIG. 7 (b), the difference is that the opening diameter of the substrate penetrating portion 3j increases from the first main surface 2A toward the second main surface 2B. Thus, even if the opening diameter is different in the thickness direction of the semiconductor substrate, the effect of reducing the stress can be obtained. Moreover, it is good also as a level | step difference structure which has several opening diameters in the thickness direction. By reducing the opening diameter on the first main surface side, which is the element formation surface side, it is possible to easily adjust the formation position of the electronic circuit, the pad, etc. and the position of the substrate penetrating portion while realizing stress reduction. .

  FIG. 8A is a plan view seen from the second main surface 2B side of the semiconductor substrate 2k, and FIG. 8B is a sectional view taken along the line VIIIB-VIIIB in FIG. 8A. As shown in FIGS. 8A and 8B, the semiconductor substrate 2k has a rectangular groove formed on the second main surface 2B side and a through hole penetrating from the groove portion to the first main surface 2A side. It has the board | substrate penetration part 3k of the shape which combined the hole. In this way, a plurality of different shapes may be combined in the thickness direction of the semiconductor substrate.

[Embodiment 2]
Next, an example of a semiconductor device different from the first embodiment will be described. The basic configuration of the semiconductor device according to the second embodiment is the same as that of the first embodiment except for the following points. That is, in the first embodiment, the substrate through-hole 3 is provided as an opening in the semiconductor substrate 2 of the semiconductor element 1, whereas in the second embodiment, a substrate spot is formed as an opening in the semiconductor substrate of the semiconductor element. The difference is that the portion 3n is provided.

  FIG. 9 is a schematic cross-sectional view of a semiconductor device 50n according to Embodiment 2 of the present invention. As shown in the figure, the semiconductor device 50n includes a semiconductor element 1n, an insulating layer 10, and a wiring structure 20. The semiconductor element 1n includes a semiconductor substrate 2n that is thinly ground.

  The semiconductor substrate 2n is provided with a plurality of counterbore portions 3n as openings. The substrate counterbore 3n plays a role of reducing the amount of warpage of the semiconductor element 1n. The substrate counterbore 3n according to the second embodiment is provided on the second main surface 2B side of the semiconductor substrate 2n.

  As a suitable material for the semiconductor substrate 2n, the same materials as those in the first embodiment can be exemplified. The thickness of the semiconductor substrate 2n can be appropriately adjusted according to the thickness required for the semiconductor device 50n. In the second embodiment, the thickness of the semiconductor substrate 2n of the semiconductor element 1n is 30 μm, and the chip size of the semiconductor element 1n is 10 mm square. The overall size of the semiconductor device 50n was 30 mm square. The number of built-in semiconductor elements 1n may be one or plural. Moreover, although the example in which the number of the substrate spot portions 3n is plural has been described, the number may be one.

  FIG. 10A is a schematic plan view of the semiconductor substrate 2n when viewed from the second main surface 2B side, and FIG. 10B is a cross-sectional view taken along the line XB-XB in FIG. is there.

  As shown in FIGS. 10A and 10B, the substrate counterbore 3n according to the second embodiment has a square shape in plan view and a concave shape in side view. Five counterbore portions 3n are arranged on the second main surface 2B side. Specifically, the counterbore 3n is disposed one by one near the corner of the semiconductor substrate 2n, and one is disposed at the center of the semiconductor substrate 2n. The position at which the substrate spot 3n is disposed is not particularly limited, but it is preferable to provide the substrate spot 3n in the vicinity of the outer peripheral portion of the semiconductor substrate which is the stress concentration position. Further, from the viewpoint of dispersing the partial stress concentration in the semiconductor substrate 2n, it is preferable that the semiconductor substrate 2n be arranged in a point symmetry or a line symmetry in plan view. More preferably, it is point-symmetric and line-symmetric as in the substrate penetration part 3 of the first embodiment. The individual shape of the counterbore 3n is not particularly limited, and may be, for example, a circular shape, a polygonal shape such as a rectangle, a shape surrounded by a curve, or a combination thereof. Furthermore, the shape of the substrate spot portion 3n disposed on the semiconductor substrate 2n is not limited to the same shape, and a plurality of substrate spot portions 3n having a plurality of shapes may be mixed.

  The depth of the concave portion (substrate counterbore portion 3n) is not particularly limited, but is preferably set to 1/2 or more with respect to the thickness of the semiconductor substrate 2n from the viewpoint of more effectively reducing stress. In the second embodiment, the substrate counterbore 3n has an outer diameter of 50 μm and a depth of 15 μm.

  As a modification of the counterbore portion 3n, the shape in the side view in the shape arrangement in the plan view of FIGS. 5A to 7B described as the modification of the first embodiment is changed to a concave portion. Things can be mentioned as an example.

  The substrate counterbore 3n forms a concave opening (substrate counterbore) in the thickness direction of the semiconductor element 1n by, for example, a D-RIE method or a laser method. The inside of the opening may be a gap, but a part or all of the opening may be filled with a filler. Although it does not specifically limit as the filler 6, The example described in Embodiment 1 can be applied suitably. In the second embodiment, the substrate spot portion is formed by the D-RIE method, and the substrate spot portion is filled with a low-elastic epoxy resin.

  When the warpage amount of the semiconductor device 50n according to the second embodiment was examined, it was confirmed that the same profile as the solid line (first embodiment) in FIG. 4 was obtained and the warpage amount could be reduced. By providing the substrate counterbore 3n, it is possible to provide a semiconductor device capable of reducing the warpage in the vicinity of the semiconductor element while reducing the amount of warpage of the entire semiconductor device 50n. Further, the internal stress that causes the warp can be reduced without deteriorating the mechanical strength of the semiconductor element 1n by the filler filled in the counterbore portion 3n. By applying a low elastic material (elastic modulus is 5 MPa or more and 5 GPa or less, preferably 10 MPa or more and 2 GPa or less) as the filler, the internal stress of the semiconductor element can be more effectively reduced. This also makes it possible to reduce the overall thickness of the semiconductor device 50n. In addition, by providing the substrate spot 3n on the second main surface 2B of the semiconductor substrate 2n, the influence of the design on the element formation surface can be eliminated or minimized.

  A temperature cycle test (-55 ° C. to + 125 ° C., 10 minutes hold) was performed on the semiconductor device 50n of the second embodiment, and it was confirmed that no defect occurred until 2000 cycles. This is considered to be due to the effect of reducing the warpage amount of the semiconductor element 1 that is warped in the opposite direction to the warpage amount of the entire semiconductor device (insulating layer) by the substrate counterbore 3n.

  According to the semiconductor device according to the second embodiment, since the substrate counterbore 3n is provided as an opening in the semiconductor substrate, the same effect as in the first embodiment can be obtained.

  The substrate counterbore 3n may be a V-groove substrate counterbore 3p as shown in FIG. 11A, a U-groove substrate counterbore 3q as shown in FIG. Various modifications are possible without departing from the spirit of the present invention. In the second embodiment, the configuration in which the counterbore portion is provided on the second main surface 2B side opposite to the element formation surface is described, but the present invention is not limited to this. Depending on the manufacturing method and the material used, the warpage of the entire semiconductor device (insulating layer 10) may be upward in FIG. 9, and the warpage of the semiconductor element may be downward. In such a case, a counterbore portion may be provided on the first main surface 2A side. Further, the warpage direction of the semiconductor device as a whole and the semiconductor element is the same, but the warpage amount of the semiconductor element may be larger than that of the insulating layer. Even in such a case, it is only necessary to provide a recess that opens in a direction that reduces the amount of warpage of the semiconductor element. That is, it is only necessary to have a recess that reduces warpage of the semiconductor element, and an embodiment in which a recess that opens on both the first main surface 2A and the second main surface 2B side may be provided.

[Embodiment 3]
FIG. 12 is a schematic cross-sectional view of a semiconductor device 50r according to Embodiment 3 of the present invention. As shown in the figure, the semiconductor device 50r includes a semiconductor element 1, an insulating layer 10r, and a wiring structure 20r. The semiconductor element 1 according to the third embodiment has the same configuration as that of the first embodiment. That is, the semiconductor element 1 includes a semiconductor substrate 2 that is thinly ground. Then, in order to reduce the amount of warping of the semiconductor element 1, the substrate through portion 3 is formed as an opening in the semiconductor substrate 2.

  The insulating layer 10 r includes a first insulating layer 11 r and an adhesive layer 19. These materials can be selected in the same manner as in the first embodiment. The semiconductor element 1 is embedded in the insulating layer 10r. Specifically, the second principal surface 2B side of the semiconductor substrate 2 of the semiconductor element 1 is in contact with the adhesive layer 19, and the other region is in contact with the first insulating layer 11r. In the third embodiment, the adhesive layer 19 has substantially the same shape as the semiconductor substrate 2 in plan view.

  The wiring structure 20 r includes a first wiring layer 21, an element connection plug 30, a second wiring layer 22, and a first through plug 31. The first wiring layer 21 is provided on the first main surface 11A of the first insulating layer 11r. The element connection plug 30 plays a role of connecting the first wiring layer 21 and a pad (not shown) formed in the semiconductor element 1. In the element connection plug 30, a conductor is filled in a via 41 provided in the first insulating layer 11r.

  The second wiring layer 22 is provided on the second main surface 11B side of the first insulating layer 11r. A part of the second wiring layer 22 is electrically connected to the first wiring layer 21 via the first through plug 31. A part of the second wiring layer 22 is in contact with the adhesive layer 19. In the third embodiment, the size of the second wiring layer 22 in contact with the adhesive layer 19 is slightly larger than the area of the adhesive layer 19 in plan view. Thereby, reliability, such as moisture resistance, improves.

  The first through plug 31 plays a role of electrically connecting the first wiring layer 21 and the second wiring layer 22. The first through plug 31 is configured by a conductor disposed in a via 42 that penetrates from the first main surface 11A of the first insulating layer 11r to the surface of the second wiring layer 22.

  The first wiring layer 21 can be selected from the same material as in the first embodiment. The second wiring layer 22 can be selected from the same material as the first wiring layer 21. In the third embodiment, copper is used for the first wiring layer 21 and the second wiring layer 22.

  Next, an example of a method for manufacturing the semiconductor device 50r according to the third embodiment will be described using the manufacturing process cross-sectional views of FIGS. 13 (a) to 13 (e).

  First, the second wiring layer 22 is formed on the main surface of the support body 45 (see FIG. 13A). As the support 45, any one of resin, metal, glass, semiconductor, ceramic, or a combination thereof can be used. Further, in order to clarify the position where the semiconductor element 1 is mounted, a position mark (not shown) may be appropriately provided on the support body 45. In the third embodiment, a copper alloy is used as the support body 45. In addition, as a position mark for mounting the semiconductor element 1, nickel having a thickness of 5 μm was provided by electroplating.

  The second wiring layer 22 can be formed by a method such as a subtractive method, a semi-additive method, or a full additive method. The subtractive method is a method in which a resist having a desired pattern is formed on a metal layer (copper foil) provided on a substrate, an unnecessary copper foil is etched, and then the resist is removed to obtain a desired pattern. . In the semi-additive method, a power supply layer is formed by an electroless plating method, a sputtering method, a CVD method, etc., a resist having an opening in a desired pattern is formed, and a metal is deposited in the resist opening by an electrolytic plating method. This is a method of obtaining a desired wiring pattern by etching the power feeding layer after removing the wire. In the full additive method, after an electroless plating catalyst is adsorbed on a substrate, a pattern is formed with a resist, and the catalyst is activated while leaving the resist as an insulating film. In this method, a desired wiring pattern is obtained by depositing metal.

  As the second wiring layer 22, for example, one or more metals selected from the group consisting of copper, silver, gold, nickel, aluminum, titanium, molybdenum, tungsten, and palladium can be used. . From the viewpoint of electrical resistance value and cost, it is preferable to form with copper. In the third embodiment, the second wiring layer 22 is formed using copper by a semi-additive method.

  Next, the semiconductor element 1 having the semiconductor substrate 2 on which the substrate penetration part 3 is formed is prepared. As the substrate material of the semiconductor element, for example, the materials described in the first embodiment can be suitably applied. In the third embodiment, a silicon substrate is used as the semiconductor substrate 2. The thickness of the semiconductor substrate 2 was 30 μm, and the size of the semiconductor element was 10 mm square. The board penetration part 3 can be provided in an arbitrary place. The number of semiconductor elements to be mounted may be one or plural. A stacked semiconductor element may be mounted.

  The substrate penetrating portion 3 can be provided at a predetermined position on the semiconductor substrate 2 before forming various elements such as electronic circuits and pads. Further, the through portion may be formed in the semiconductor substrate 2 after forming various elements on the semiconductor substrate. The diameter of the substrate penetrating portion 3 is not particularly limited, but in the third embodiment, the outer diameter is 50 μm.

  The semiconductor element 1 is mounted on the upper layer of the predetermined second wiring layer 22 of the support body 45 through the adhesive layer 19 (see FIG. 13B). The semiconductor element 1 was mounted on the support 45 using a semiconductor mounting machine in a face-up state.

  Next, a first insulating layer 11r is formed so as to embed the semiconductor element 1 (see FIG. 13C). As the material of the first insulating layer 11r, for example, the material described in the first embodiment can be suitably applied. For example, a transfer molding method, a compression molding mold method, a printing method, a vacuum pressing method, a vacuum laminating method, a spin coating method, a die coating method, a curtain coating method, or a photolithography method is applied to the semiconductor element 1. Can do. In the third embodiment, the first insulating layer 11r is formed by vacuum lamination using an epoxy resin. When forming the first insulating layer 11r, a concave portion may be formed in advance at a location corresponding to the semiconductor element 1, and the first insulating layer 11r and the support body 45 may be joined.

  Subsequently, a via 41 penetrating from the surface of the first insulating layer 11r to the surface of the pad (not shown) of the semiconductor element 1 is provided. In addition, a via 42 penetrating from the surface of the first insulating layer 11r to the surface of the second wiring layer 22 is formed (see FIG. 13D). These vias 41 and 42 can be directly patterned by photolithography when a photosensitive material is used as the first insulating layer 11r. Further, when a non-photosensitive resin is used as the first insulating layer 11r, or when the resolution is low even with a photosensitive material, the vias 41 and 42 are formed by, for example, a laser processing method, a dry etching method, or a blast method. . In the third embodiment, the vias 41 and 42 are formed using a laser processing method.

  Next, the element connection plug 30 is formed by forming a conductor inside the via 41, and the first through plug 31 is formed by forming a conductor inside the via 42. Then, the first wiring layer 21 is formed on the first insulating layer 11r (see FIG. 13E). The element connection plug 30 is formed by filling the via 41 with a conductor, and the first through plug 31 is formed by filling the via 42 with the conductor. These conductors are not particularly limited, but, for example, one or more metals selected from the group consisting of copper, silver, gold, nickel, aluminum, titanium, molybdenum, tungsten, and palladium as main components. Can be used. The conductor can be filled by a method such as electroplating, electroless plating, a printing method or a molten metal suction method.

  It should be noted that energization posts such as metal bumps are formed in advance at desired positions of the element connection plug 30 and the first through plug 31, and then the first insulating layer 11r is formed, and the surface of the first insulating layer 11r is polished. The element connection plug 30 and the first through plug 31 may be formed by shaving to expose the energization post. According to this method, the process of providing a via in the first insulating layer 11r can be cut.

  The first wiring layer 21 can be manufactured, for example, by a method similar to the method for forming the second wiring layer 22 described above. Although the example of the 1st wiring layer 21 is not specifically limited, What was mentioned by the 2nd wiring layer 22 can be mentioned as a suitable example. In the third embodiment, the first wiring layer 21 is formed by using a semi-additive method using copper.

  Thereafter, the support 45 was removed to obtain a semiconductor device 50r as shown in FIG. For removing the support 45, a wet etching method using a chemical solution, a grinding method using mechanical polishing, a physical peeling method, and the like are suitable, but not limited thereto. In this Embodiment 3, the support body 45 which is a copper alloy was removed using alkaline wet etching liquid.

  The thermal expansion coefficient of the semiconductor substrate 2 (silicon) applied in the third embodiment is about 3.5 ppm / K, the thermal expansion coefficient of the insulating layer (epoxy resin) is about 60 ppm / K, and the heat of the support (copper). The expansion coefficient is about 17 ppm / K. Therefore, the thermal expansion coefficient of the semiconductor element 1 is the smallest.

  When the semiconductor substrate 2 is not provided with an opening such as a substrate through-hole or a counterbore, which is a means for reducing the warpage of the semiconductor element, the support 45, the adhesive layer, the semiconductor element, and the embedded layer are cured when the insulating layer 10 is cured Internal stress accumulates due to the difference in thermal expansion coefficient of each insulating layer. After that, when the support body 45 is removed, the entire built-in substrate becomes a warped shape that protrudes greatly downward. On the other hand, in the semiconductor element mounting region, on the contrary, a warped shape that is convex upward is locally generated. Since the warpage of the entire semiconductor device (insulating layer) and the local warpage of the semiconductor element are in opposite directions, internal stress concentrates on the outer periphery of the semiconductor element. In a reliability evaluation test such as a temperature cycle test, cracks occur in the insulating resin around the outer peripheral portion when the number of cycles is less than the specified number, and an open defect of the wiring occurs. Such characteristic warpage is caused by a difference in thermal expansion coefficient between the semiconductor element and the insulating layer, and further, the support 45 applied in the manufacturing process of the semiconductor element. In particular, it has been found that this is remarkable when a metal such as copper is used as the support.

  As a result of repeated studies by the present inventors, as a means for reducing the warpage amount of the semiconductor element, a warp as shown in the comparative example of FIG. It has been found that the shape can be suppressed. In other words, by providing the substrate through-hole portion or the substrate counterbore portion, the entire built-in substrate has a large downward convex warp shape, whereas only the semiconductor element mounting region has a convex upward convex shape locally. It was found that it can be suppressed.

  In the semiconductor device 50r according to the third embodiment, it was confirmed that a profile similar to the warp profile of the solid line (first embodiment) in FIG. 4 was obtained. That is, it was confirmed that the warpage amount of the semiconductor device 50r can be effectively reduced. This employs a structure in which the substrate through-hole 3 is provided in the semiconductor element 1 and the inside of the substrate through-hole 3 is filled with a gap or a low elastic material, so that the mechanical strength of the semiconductor element 1 is deteriorated. However, it is considered that the internal stress that causes the warp could be reduced.

  When a temperature cycle test (-55 ° C. to + 125 ° C., held for 10 minutes) was performed on the semiconductor device according to the third embodiment, it was confirmed that no defect occurred even after 2000 cycles. This is presumably because the internal stress of the semiconductor element is reduced by the substrate penetration part 3 of the semiconductor substrate 2 and the warpage of the entire semiconductor device (insulating layer) is reduced.

  According to the semiconductor device 50r according to the third embodiment, by providing the substrate through portion 3, it is possible to provide a semiconductor device capable of reducing the warpage in the vicinity of the semiconductor element while reducing the warpage amount of the entire semiconductor device 50. it can. In addition, since the semiconductor device 50r according to the third embodiment has the second wiring layer 22, it has an advantage that it is possible to incorporate a higher-functionality semiconductor element with more pins. In addition, since the first wiring layer 21 on the upper layer side and the second wiring layer 22 on the lower layer side are connected by the first through plug 31, the connection using both surfaces of the semiconductor device 50r is possible. Accordingly, for example, a module having a complicated structure such as a package-on-package system-in-package can be manufactured.

  Furthermore, in the semiconductor device according to the third embodiment, the second wiring layer 22 having a larger area than that of the semiconductor element 1 is provided at the place where the semiconductor element 1 is mounted. Thereby, it can prevent that the contact bonding layer 19 is exposed to the surface. As a result, reliability such as moisture resistance is improved.

<Modification 3-1>
Next, an example of a modification of the third embodiment will be described. FIG. 14 is a schematic cross-sectional view of a main part of a semiconductor device 50s according to Modification 3-1. In the semiconductor device 50s, solder resists 46 are provided on both main surfaces of the semiconductor device. The material of the solder resist 46 is not particularly limited, but an epoxy-based, acrylic-based, urethane-based, or polyimide-based organic material can be suitably used. Moreover, you may add the filler of an inorganic material or an organic material as needed. A photosensitive resist ink may be used as the solder resist 46. In this modified example 3-1, a photosensitive resist ink was used. According to the modified example 3-1, a low warpage effect can be obtained as in the third embodiment. In addition, the environmental resistance can be improved by providing the solder resist 46.

<Modification 3-2>
FIG. 15 is a schematic cross-sectional view of a semiconductor device 50t according to Modification 3-2. An external terminal 47 is provided on one side of the semiconductor device 50t. The semiconductor device 50 t has a structure that can be mounted on a board of a device (not shown) via the external terminal 47. The material of the external terminal 47 is not particularly limited, but can be selected from the same material as the first wiring layer 21 and the second wiring layer 22. One or a plurality of metals selected from the group consisting of gold, silver, copper, tin, solder material, and the like may be formed on the surface. In Modification 3-2, an alloy of tin, silver, and copper was used as the external terminal 47. According to the modification 3-2, the low warping effect can be obtained as in the third embodiment.

[Embodiment 4]
The basic configuration of the semiconductor device according to the fourth embodiment is the same as that of the third embodiment except for the following points. That is, in the third embodiment, the substrate penetrating portion 3 is provided so as to penetrate the semiconductor substrate 2, whereas in the fourth embodiment, the substrate penetrating portion is arranged not only in the semiconductor substrate but also in the lower layer. The difference is that the adhesive layer is formed so as to penetrate the adhesive layer.

  FIG. 16 is a schematic cross-sectional view of a semiconductor device 50u according to Embodiment 4 of the present invention. As shown in the figure, the semiconductor device 50u includes a semiconductor element 1, an insulating layer 10u, and a wiring structure 20u. The semiconductor element 1 according to the fourth embodiment includes a semiconductor substrate 2 that is thinly ground. The semiconductor substrate 2 is provided with a substrate through portion 3u as an opening for reducing the warp of the semiconductor element 1.

  As shown in FIG. 16, the substrate penetration 3u is formed not only to penetrate the semiconductor substrate 2, but also to penetrate the adhesive layer 19u. In other words, the substrate through-hole 3u is formed integrally with the semiconductor substrate 2 and the adhesive layer 19u so as to reach the surface of the second wiring layer 22 disposed immediately below the adhesive layer 19u. One or a plurality of the substrate penetrating portions 3u can be formed. The filler 6u is not particularly limited, but preferably a filler-containing low-elasticity resin is applied. Thereby, the heat generated in the semiconductor element 1 can be released to the second wiring layer 22 via the substrate penetration part 3u. That is, a heat dissipation effect can be imparted.

  The insulating layer 10u includes a first insulating layer 11r and an adhesive layer 19u. These materials can be selected in the same manner as in the first embodiment.

  The material, thickness, and size of the semiconductor element of the semiconductor substrate 2 were the same as those in the third embodiment.

  As materials for the insulating layer 10, the first wiring layer 21, the second wiring layer 22, the adhesive layer 19 u and the like, those described in the above embodiment can be suitably applied. As the adhesive layer 19u, in the fourth embodiment, DAF mainly composed of an epoxy resin is applied.

  Also for the manufacturing method, the method described in the third embodiment can be preferably applied. In the fourth embodiment, the substrate penetrating portion 3u has a structure in which a via is opened by a D-RIE method and the inside of the via is filled with a low elasticity epoxy resin. The element connection plug 30 was obtained by filling copper in a via opened by a laser.

  According to the semiconductor device 50u according to the fourth embodiment, a profile similar to the warp profile of the solid line (first embodiment) in FIG. 4 could be obtained. That is, it was confirmed that the warpage amount of the semiconductor device 50u can be effectively reduced. This is because the semiconductor element 1 is provided with the substrate penetrating portion 3, so that the internal stress causing the warp can be reduced by the low elastic resin of the substrate penetrating portion 3 without deteriorating the mechanical strength of the semiconductor element 1. It is considered to be due to this.

  When a temperature cycle test (-55 ° C. to + 125 ° C., 10 minutes hold) was performed on the semiconductor device of the fourth embodiment, it was confirmed that no defect occurred after 2000 cycles. It is considered that this is because the internal stress of the semiconductor element is reduced by the substrate penetration part 3 of the semiconductor substrate 2 and the warpage of the entire semiconductor device (insulating layer) is reduced.

  According to the semiconductor device of the fourth embodiment, the same effects as those of the third embodiment can be obtained. In addition, in the semiconductor device 50 u according to the fourth embodiment, the substrate penetrating portion 3 u penetrates the semiconductor element 1 and the adhesive layer 19 u and is connected to the second wiring layer 22. Thereby, it is possible to efficiently dissipate heat in the semiconductor element 1. Further, by connecting the substrate penetration 3u to the ground layer of the semiconductor element 1, EMC characteristics such as electromagnetic radiation can be improved. In addition, these effects can be obtained by providing a substrate counterbore in place of the substrate penetration 3u.

[Embodiment 5]
The basic configuration of the semiconductor device according to the fifth embodiment is the same as that of the third embodiment except for the following points. That is, in the third embodiment, the second wiring layer 22 is provided so as to contact the adhesive layer 19 and the second wiring layer 22 is provided so as to contact the first insulating layer 11. On the other hand, the fifth embodiment is different in that the second wiring layer is provided so as to be separated from the adhesive layer, and the second wiring layer is provided so as to contact the second insulating layer.

  FIG. 17 is a schematic cross-sectional view of a semiconductor device 50v according to Embodiment 5 of the present invention. As shown in the figure, the semiconductor device 50v includes a semiconductor element 1, an insulating layer 10v, and a wiring structure 20v. The semiconductor element 1 according to the fifth embodiment includes a semiconductor substrate 2 that is thinly ground. The semiconductor substrate 2 is provided with a substrate through portion 3 as an opening.

  The insulating layer 10v includes a first insulating layer 11v, an adhesive layer 19, and a second insulating layer 12. The semiconductor element 1 is embedded in the insulating layer 10v. Specifically, the second principal surface 2B side of the semiconductor substrate 2 of the semiconductor element 1 is in contact with the adhesive layer 19, and the other region is in contact with the first insulating layer 11v. The second insulating layer 12 is disposed on the side of the adhesive layer 19 opposite to the side in contact with the semiconductor substrate 2. In other words, the adhesive layer 19 having substantially the same shape as that of the semiconductor substrate 2 is laminated on the second insulating layer 12. The semiconductor substrate 2 is mounted on the adhesive layer 19. Further, a first insulating layer 11v is formed in the upper layer of the semiconductor element 1 so as to embed the semiconductor element 1.

  The materials of the first insulating layer 11v and the adhesive layer 19 are as described in the first embodiment. Although the material of the 2nd insulating layer 12 is not specifically limited, The material similar to the 1st insulating layer 11 described in the said Embodiment 1 can be applied suitably. By using the same material for the first insulating layer 11v and the second insulating layer 12, the yield in the manufacturing process can be improved. Further, by making the thermal expansion coefficient of the second insulating layer 12 smaller than the thermal expansion coefficient of the first insulating layer 11v, it is possible to reduce the amount of warpage protruding downward on the entire semiconductor device 50v. In the fifth embodiment, epoxy resin is applied to both the first insulating layer 11v and the second insulating layer 12.

  The wiring structure 20v includes a first wiring layer 21, an element connection plug 30, a second wiring layer 22v, and a first through plug 31v. The second wiring layer 22v is provided on the second main surface 12B side of the second insulating layer 12. A part of the second wiring layer 22v is electrically connected to the first wiring layer 21 via the first through plug 31v. In addition, a part of the second wiring layer 22v is disposed opposite to the lower layer of the semiconductor element 1 with the adhesive layer 19 and the second insulating layer 12 interposed therebetween.

  The first through plug 31v plays a role of electrically connecting the first wiring layer 21 and the second wiring layer 22v. The first through plug 31v is composed of a conductor disposed in a via 42 that penetrates from the first main surface 11A of the first insulating layer 11v to the surface of the second wiring layer 22v. Accordingly, the via 42 is formed from the first insulating layer 11 v to the second insulating layer 12.

  The thickness of the semiconductor element 1 can be appropriately adjusted according to the thickness required for the semiconductor device. In the fifth embodiment, the semiconductor substrate 2 provided in the semiconductor element 1 is silicon, and the thickness of the semiconductor substrate 2 is 30 μm. The chip size of the semiconductor element 1 was 10 mm square. Further, copper was used for the first wiring layer 21 and the second wiring layer 22v. Note that the number of semiconductor elements 1 incorporated may be one or plural. The substrate penetrating portion 3 can be provided at an arbitrary place as long as the mechanical strength of the semiconductor element 1 is not lowered.

  The first through plug 31v can be formed, for example, by opening a via 42 in a part of the first insulating layer 11v and the second insulating layer 12 with a laser and then filling the conductor. Further, it may be formed by providing a metal bump or the like in advance on the second wiring layer 22v. In the fifth embodiment, copper filled by plating in a via opened by a laser is used.

  In the semiconductor device 50v according to the fifth embodiment, it was confirmed that a profile similar to the warp profile of the solid line (first embodiment) in FIG. 4 was obtained. That is, it was confirmed that the warpage amount of the semiconductor device 50v can be effectively reduced. This employs a structure in which the substrate through-hole 3 is provided in the semiconductor element 1 and the inside of the substrate through-hole 3 is filled with a gap or a low elastic material, so that the mechanical strength of the semiconductor element 1 is deteriorated. However, it is considered that the internal stress that causes the warp could be reduced.

  When a temperature cycle test (-55 ° C. to + 125 ° C., held for 10 minutes) was performed on the semiconductor device according to the fifth embodiment, it was confirmed that no defect occurred even after 2000 cycles. It is considered that this is because the internal stress of the semiconductor element is reduced by the substrate penetration part 3 of the semiconductor substrate 2 and the warpage amount of the entire semiconductor device (insulating layer) is reduced.

  According to the semiconductor device 50v according to the fifth embodiment, the same effect as in the third embodiment can be obtained. Furthermore, in the semiconductor device according to the fifth embodiment, it is possible to arrange a plurality of fine wirings below the semiconductor element 1 by arranging the second insulating layer 12, which is shown in the third embodiment. It becomes possible to accommodate wiring with higher density than the example. These effects can be obtained even if a counterbore portion is provided instead of the substrate penetration portion.

[Embodiment 6]
The basic configuration of the semiconductor device according to the sixth embodiment is the same as that of the fifth embodiment except for the following points. That is, the sixth embodiment is different in that a third wiring layer is further provided above the first wiring layer 21 according to the fifth embodiment via a third insulating layer. Another difference is that a fourth wiring layer is further provided above the second wiring layer 22 according to the fifth embodiment via a fourth insulating layer.

  FIG. 18 is a schematic cross-sectional view of a semiconductor device 50w according to Embodiment 6 of the present invention. As shown in the figure, the semiconductor device 50w includes a semiconductor element 1, an insulating layer 10w, and a wiring structure 20w. A semiconductor element 1 according to the sixth embodiment includes a semiconductor substrate 2 that is thinly ground. The semiconductor substrate 2 is provided with a substrate through portion 3 as an opening for reducing warpage of the semiconductor element 1.

  The insulating layer 10w includes a first insulating layer 11v, an adhesive layer 19, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14. The semiconductor element 1 is embedded in the insulating layer 10w. Specifically, the second principal surface 2B side of the semiconductor substrate 2 of the semiconductor element 1 is in contact with the adhesive layer 19, and the other region is in contact with the first insulating layer 11v. The second insulating layer 12 is disposed on the side of the adhesive layer 19 opposite to the side in contact with the semiconductor substrate 2. A third insulating layer 13 is disposed above the first insulating layer 11v, and a fourth insulating layer 14 is disposed below the second insulating layer 12. In other words, the second insulating layer 12 is formed on the fourth insulating layer 14, and the semiconductor element 1 is disposed on the second insulating layer 12 with the adhesive layer 19 interposed therebetween. A first insulating layer 11v is disposed on the second insulating layer 12 and the semiconductor element 1, and a third insulating layer 13 is disposed on the first insulating layer 11v.

  The materials of the first insulating layer 11v, the adhesive layer 19, and the second insulating layer 12 are as described in the fifth embodiment. Further, as the materials of the third insulating layer 13 and the fourth insulating layer 14, those exemplified for the first insulating layer 11v and the second insulating layer 12 can be suitably applied. By making the materials of the first insulating layer 11v to the fourth insulating layer 14 the same, the yield in the manufacturing process can be improved. Further, by making the thermal expansion coefficient of the second insulating layer 12 smaller than the thermal expansion coefficient of the first insulating layer 11v, it is possible to reduce the amount of warpage protruding downward on the entire semiconductor device 50w. In the sixth embodiment, epoxy resin is applied to all of the first insulating layer 11v to the fourth insulating layer 14.

  The wiring structure 20w includes a first wiring layer 21, an element connection plug 30, a second wiring layer 22v, a first through plug 31v, a third wiring layer 23, a second through plug 32, a fourth wiring layer 24, and a third through plug. 33.

  The third wiring layer 23 is formed in the upper layer of the third insulating layer 13. The first wiring layer 21 and the third wiring layer 23 are electrically connected by a second through plug 32 provided in the third insulating layer 13. On the other hand, the fourth wiring layer 26 is formed on the second main surface 15B side of the fourth insulating layer 14. The second wiring layer 23 and the fourth wiring layer 24 are electrically connected by a third through plug 33.

  The material and thickness of the semiconductor substrate were the same as those in the fifth embodiment. The size of the semiconductor element 1 was also the same as that of the first embodiment. Also, copper was used for the first wiring layer 21, the second wiring layer 22, the third wiring layer 23, and the fourth wiring layer 24. Note that the number of semiconductor elements 1 incorporated may be one or plural. The board penetration part 3 can be provided in an arbitrary place.

  In the semiconductor device 50w according to the sixth embodiment, it was confirmed that a profile similar to the warp profile of the solid line (first embodiment) in FIG. 4 was obtained. That is, it was confirmed that the warpage amount of the semiconductor device 50w can be effectively reduced. This employs a structure in which the substrate through-hole 3 is provided in the semiconductor element 1 and the inside of the substrate through-hole 3 is filled with a gap or a low elastic material, so that the mechanical strength of the semiconductor element 1 is deteriorated. However, it is considered that the internal stress that causes the warp could be reduced.

  As a result of conducting a temperature cycle test (-55 ° C. to + 125 ° C., 10 minutes hold) for the semiconductor device according to the sixth embodiment, it was confirmed that no defect occurred even after 2000 cycles. It is considered that this is because the internal stress of the semiconductor element is reduced by the substrate penetration part 3 of the semiconductor substrate 2 and the warpage amount of the entire semiconductor device (insulating layer) is reduced.

  According to the semiconductor device 50w according to the sixth embodiment, the same effect as in the fifth embodiment can be obtained. Further, by adding the third wiring layer and the fourth wiring layer, it is possible to accommodate the wiring at a higher density than in the fifth embodiment.

[Embodiment 7]
The basic configuration of the semiconductor device according to the seventh embodiment is the same as that of the sixth embodiment except for the following points. That is, the seventh embodiment is different from the semiconductor device according to the sixth embodiment in that one wiring layer and one insulating layer are added on both sides of the main surface. Specifically, a fifth wiring layer is provided on the third wiring layer 23 of the sixth embodiment via a fifth insulating layer. Further, a sixth wiring layer is further provided below the fourth wiring layer 24 of the sixth embodiment via a sixth insulating layer. Hereinafter, differences from the sixth embodiment will be described.

  FIG. 19 is a schematic cross-sectional view of a semiconductor device 50x according to Embodiment 7 of the present invention. As shown in the figure, the semiconductor device 50x includes a semiconductor element 1, an insulating layer 10x, and a wiring structure 20x. The semiconductor element 1 according to the seventh embodiment includes a semiconductor substrate 2 that is thinly ground. The semiconductor substrate 2 is provided with a substrate through portion 3 as an opening for reducing warpage of the semiconductor element 1.

  The insulating layer 10x includes a first insulating layer 11v, an adhesive layer 19, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, a fifth insulating layer 15, and a sixth insulating layer 16. A third insulating layer 13 is disposed above the first insulating layer 11v, and a fifth insulating layer 15 is disposed thereon. On the other hand, a fourth insulating layer 14 is disposed below the second insulating layer 12, and a sixth insulating layer 16 is disposed below the fourth insulating layer 14. In other words, the fourth insulating layer 14 is formed above the sixth insulating layer 16, and the second insulating layer 12 is formed above the fourth insulating layer 14. The semiconductor element 1 is disposed on the second insulating layer 12 with an adhesive layer 19 interposed therebetween. A first insulating layer 11v is disposed on the second insulating layer 12 and the semiconductor element 1, and a third insulating layer 13 is disposed on the first insulating layer 11v. Further, a fifth insulating layer 15 is disposed on the third insulating layer 13.

  The materials of the fifth insulating layer 15 and the sixth insulating layer 16 are not particularly limited. For example, the materials exemplified in the first insulating layer 11v and the second insulating layer 12 can be suitably applied. . By making the materials of the first insulating layer 11v to the sixth insulating layer 16 the same, the yield in the manufacturing process can be improved. Further, by making the thermal expansion coefficient of the insulating layer disposed below the semiconductor element 1 smaller than the thermal expansion coefficient of the insulating layer disposed on the upper layer side of the semiconductor element 1, The amount of convex warpage can be reduced. In the seventh embodiment, epoxy resin is applied to all of the first insulating layer 11v to the sixth insulating layer 16.

  The wiring structure 20x includes a first wiring layer 21, an element connection plug 30, a second wiring layer 22v, a first through plug 31v, a third wiring layer 23, a second through plug 32, a fourth wiring layer 24, and a third through plug. 33, a fifth wiring layer 25, a fourth through plug 34, a sixth wiring layer 26, and a fifth through plug 35.

  The fifth wiring layer 25 is formed in the upper layer of the fifth insulating layer 15. The fifth wiring layer 25 and the third wiring layer 23 are electrically connected by a fourth through plug 34 provided in the fifth insulating layer 15. On the other hand, the sixth wiring layer 26 is provided on the second main surface 16B side of the sixth insulating layer 16. The sixth wiring layer 26 and the fourth wiring layer 24 are electrically connected by a fifth through plug 35.

  In the seventh embodiment, the material, thickness, semiconductor element size, and the like of the semiconductor substrate 2 are the same as those in the sixth embodiment. Further, copper was used for the first wiring layer 21 and the second wiring layer 22v.

  In the semiconductor device 50x according to the seventh embodiment, it was confirmed that a profile similar to the warp profile of the solid line (first embodiment) in FIG. 4 was obtained. That is, it was confirmed that the warpage amount of the semiconductor device 50x can be effectively reduced. Moreover, as a result of carrying out a temperature cycle test (-55 ° C. to + 125 ° C., 10 minutes hold), it was confirmed that no defect occurred even after 2000 cycles.

  According to the semiconductor device 50x according to the seventh embodiment, the same effect as in the sixth embodiment can be obtained. Further, by adding the fifth wiring layer 25 and the sixth wiring layer 26, it is possible to accommodate wiring with higher density than in the sixth embodiment. Further, the power supply supplied to the semiconductor element 1 can be stabilized by providing a power supply or ground dedicated layer as the wiring layer. As a result, a highly reliable semiconductor device can be provided.

[Eighth embodiment]
The basic configuration of the semiconductor device according to the eighth embodiment is the same as that of the seventh embodiment except for the following points. That is, the eighth embodiment is different from the semiconductor device according to the seventh embodiment in that a solder resist and an external terminal are provided below the sixth wiring layer 26.
Hereinafter, differences from the seventh embodiment will be described.

  FIG. 20 is a schematic cross-sectional view of a semiconductor device 50y according to Embodiment 8 of the present invention. As shown in the figure, the semiconductor device 50y includes a semiconductor element 1, an insulating layer 10y, and a wiring structure 20y. Further, a solder resist 46 is disposed on the second main surface 16B of the sixth insulating layer 16. An external terminal 47 is disposed on the exposed surface of the sixth wiring layer 26. In the seventh embodiment, a photosensitive resist ink is used as a solder resist. As the external terminal 47, an alloy of tin, silver and copper was used. Others were the same as in the seventh embodiment.

  Next, an example of a method for manufacturing the semiconductor device 50y according to the eighth embodiment will be described with reference to the manufacturing process cross-sectional views of FIGS. 21 (a) to 21 (e) and FIGS. 22 (f) to 22 (h). To do. In addition, the manufacturing method demonstrated below is an example, Comprising: It is not limited to this.

  First, the second wiring layer 22v is formed on the main surface of the support 45. Then, the support body 45 and the second wiring layer 22v are covered with the second insulating layer 12 (see FIG. 21A). The material of the support 45 is as described in the third embodiment. In the eighth embodiment, a copper alloy is used as the support body 45. In addition, as a position mark for mounting the semiconductor element 1, nickel having a thickness of 5 μm was provided by electroplating.

  Suitable materials for the second insulating layer 12 are as described in the fifth embodiment. As a method for forming the second insulating layer 12, a transfer molding method, a compression molding method, a printing method, a vacuum pressing method, a vacuum laminating method, a spin coating method, a die coating method, a curtain coating method, a photolithography method, or the like is applied. be able to. In the eighth embodiment, the second insulating layer 12 is formed by vacuum lamination using an epoxy resin.

  Next, the semiconductor element 1 having the semiconductor substrate 2 on which the substrate penetration part 3 is formed is prepared. Then, the semiconductor element 1 is mounted on the upper layer of the support 45 at a predetermined position via the adhesive layer 19. Thereafter, the first insulating layer 11v is formed so as to cover the second insulating layer 12 and the semiconductor element 1 (see FIG. 21B). The substrate penetrating portion 3 can be provided at an arbitrary place as long as the mechanical strength of the semiconductor element 1 is not lowered. As the substrate material of the semiconductor element, for example, the materials described in the first embodiment can be suitably applied. In the eighth embodiment, a silicon LSI is used. The semiconductor element 1 was mounted on the support 45 using a semiconductor mounting machine in a face-up state.

  The first insulating layer 11v is formed so as to embed the semiconductor element 1 therein. As a material of the first insulating layer 11v, for example, the material described in the first embodiment can be suitably applied. The method for incorporating the semiconductor element 1 is as described in the third embodiment.

  Subsequently, a via 41 penetrating from the surface of the first insulating layer 11v to the surface of the pad (not shown) of the semiconductor element 1 is provided. At the same time, a via 42 penetrating from the surface of the first insulating layer 11v to the surface of the second wiring layer 22 is formed (see FIG. 21C). In the eighth embodiment, the via 41 and the via 42 are formed using a laser processing method.

  Next, a conductor is formed inside the via 41 and the via 42 to form the first wiring layer 21 (see FIG. 21D). The element connection plug 30 is formed by filling the via 41 with a conductor, and the first through plug 31 is formed by filling the via 42 with the conductor. Suitable examples of these conductor materials and formation methods are as described in the third embodiment. In addition, the material and the method described in the third embodiment can be suitably applied to the material and the formation method of the first wiring layer 21. In the eighth embodiment, copper is used to form the first wiring layer 21 by a semi-additive method.

  Thereafter, the support body 45 is removed (see FIG. 21E). The method for removing the support 45 can be suitably applied to the method described in the third embodiment, but is not limited thereto. In this Embodiment 8, the support body 45 which is a copper alloy was removed using alkaline wet etching liquid.

  Next, the third insulating layer 13, the fourth insulating layer 14, the third wiring layer 23, the second through plug 32, the fourth wiring layer 24, and the third through plug 33 are formed (see FIG. 22F). Suitable materials for the third insulating layer 13 and the fourth insulating layer 14 are as described above. Moreover, as a formation method of the 3rd insulating layer 13 and the 4th insulating layer 14, it can form by the method similar to the 2nd insulating layer mentioned above, for example. In the eighth embodiment, the third insulating layer 13 and the fourth insulating layer 14 are formed by vacuum lamination using epoxy resin.

  A method for forming the vias of the third insulating layer 13 and the fourth insulating layer 14 is not particularly limited, but the same method as the via 41 and the via 42 can be suitably applied. In the eighth embodiment, the opening is formed using a laser processing method. Further, the third wiring layer 23 and the fourth wiring layer 24 were formed by using a semi-additive method using copper.

  Next, the fifth insulating layer 15, the sixth insulating layer 16, the fifth wiring layer 25, the fourth through plug 34, the sixth wiring layer 26, and the fifth through plug 35 are formed (see FIG. 22G). Suitable materials for the fifth insulating layer 15 and the sixth insulating layer 16 are as described above. Moreover, as a formation method of the 5th insulating layer 15 and the 6th insulating layer 16, it can form by the method similar to the 2nd insulating layer mentioned above, for example.

  Thereafter, a solder resist 46 having an opening is formed on the sixth wiring layer 26 (see FIG. 22H). By providing the solder resist 46, the surface circuit of the semiconductor device can be protected and flame retardancy can be imparted. In the eighth embodiment, a photosensitive resist ink is used.

  Next, external terminals 47 connected to the sixth wiring layer 26 are formed on the solder resist 46 side. Through the above steps, the semiconductor device 50y shown in FIG. 20 is manufactured.

  In the semiconductor device 50y according to the eighth embodiment, it was confirmed that a profile similar to the warp profile of the solid line (first embodiment) in FIG. 4 was obtained. That is, it was confirmed that the warpage amount of the semiconductor device 50y can be effectively reduced. Moreover, as a result of carrying out a temperature cycle test (-55 ° C. to + 125 ° C., 10 minutes hold), it was confirmed that no defect occurred even after 2000 cycles.

  According to the semiconductor device 50y according to the eighth embodiment, the same effect as in the seventh embodiment can be obtained. Also, by providing the external terminal 47, the semiconductor device 50y can be more stably mounted on the substrate of the device.

  Note that the number of wiring layers and the insulating layers are merely examples, and it is needless to say that the wiring layers can be stacked in a necessary number without being limited to the above embodiment.

[Embodiment 9]
Next, a method for manufacturing a semiconductor device different from that of the eighth embodiment will be described. The basic configuration of the semiconductor device according to the ninth embodiment is the same as that of the eighth embodiment except for the following points. That is, the fourth wiring layer 24 is formed on the lower surface of the fourth insulating layer 14 in the drawing in the eighth embodiment, whereas the sixth insulating layer 16 in the ninth embodiment. Are different in that they are formed on the upper surface in FIG. This is based on the difference in the manufacturing method.

  FIG. 23 is a schematic cross-sectional view of a semiconductor device 50z according to Embodiment 9 of the present invention. As shown in the figure, the semiconductor device 50z includes a semiconductor element 1, an insulating layer 10z, and a wiring structure 20z. The fourth wiring layer 24 is formed on the upper surface of the sixth insulating layer 16 in the drawing. Therefore, the configuration of the insulating layer 10z is different from that of the eighth embodiment in relation to the fourth wiring layer 24, but the other configurations are the same.

  Hereinafter, the manufacturing method of Embodiment 9 will be described with reference to the manufacturing process cross-sectional views of FIGS. 24 (a) to 26 (g). Note that the same materials are applied to the same members as those in the eighth embodiment unless otherwise specified. Also, the manufacturing method of each member applies the same method as in Embodiment 8 unless otherwise specified.

  First, on the main surface of the support 45, the sixth wiring layer 26, the sixth insulating layer 16, the fifth through plug 35, the fourth wiring layer 24, the fourth insulating layer 14, the third through plug 33, the second wiring. The layer 22v and the second insulating layer 12 are formed (see FIG. 24A). Specifically, first, the sixth wiring layer 26 was formed, and the sixth insulating layer 16 was formed so as to cover it. Then, vias were formed in the sixth insulating layer 16 and a fifth through plug 35 was disposed. As described above, a method of forming a post for energization in advance may be applied. The same applies to the through plug described below.

  Thereafter, the fourth wiring layer 24 is formed. Then, the fourth insulating layer 14 is covered, a via penetrating from the surface of the fourth insulating layer 14 to the surface of the fourth wiring layer 24 is formed, and the third through plug 33 is disposed. Next, the second wiring layer 22v is formed.

  Next, the semiconductor element 1 having the semiconductor substrate 2 in which the substrate penetration part 3 is formed is mounted on the upper layer of the support 45 at a predetermined position via the adhesive layer 19 (FIG. 24B). reference). Thereafter, the first insulating layer 11v is formed so as to embed the semiconductor element 1 (see FIG. 24C).

  Subsequently, a via 41 penetrating from the surface of the first insulating layer 11v to the surface of the pad (not shown) of the semiconductor element 1, and a via 42 penetrating from the surface of the first insulating layer 11v to the surface of the second wiring layer 22v. Form. Then, the element forming plug 30 and the first through plug 31 are formed by forming a conductor inside the via 41 and the via 42. Thereafter, the first wiring layer 21 is formed (see FIG. 25D).

  Next, the third insulating layer 13, the second through plug 32, the third wiring layer 23, the fifth insulating layer 15, the fourth through plug 34, and the fifth wiring layer 25 are formed (see FIG. 25E).

  Thereafter, the support body 45 is removed (see FIG. 26F). Next, a solder resist 46 having an opening is formed on the sixth wiring layer 26 (see FIG. 26G). Thereafter, external terminals 47 connected to the sixth wiring layer 26 are formed on the solder resist 46 side. Through the above steps and the like, the semiconductor device 50z shown in FIG. 23 is manufactured.

  According to the method for manufacturing a semiconductor device according to the ninth embodiment, since all the wiring layers can be formed on the support body 45, warpage during the manufacturing process is small, and the manufacturing yield can be improved. The semiconductor device according to the ninth embodiment can obtain the same effects as those of the eighth embodiment.

  In addition, the said embodiment is an example, Comprising: It is not limited to these. Moreover, what combined each embodiment can also be applied suitably. For example, the aspect which changes the location which applied the board | substrate penetration part as the opening part 3 to a board spot part can also be applied suitably. Moreover, a substrate counterbore part or a substrate through part may be mixed in one semiconductor substrate. Further, when a plurality of semiconductor elements are mounted, a semiconductor element having a counterbore part, a semiconductor element having a substrate through part, or a semiconductor element not having these openings may be mixed. Further, in addition to the counterbore portion of the substrate, a reinforcing structure or the like may be added. In the semiconductor device of the present invention, another electronic component may be mounted at a desired position. Although it does not specifically limit as an electronic component, For example, the LCR element which plays the role of the noise filter of a circuit can be provided. Moreover, a MEMS component, a sensor, an energy device, an optical component, etc. may be mounted as a passive component. These other electronic components may be incorporated in the insulating layer 10. In addition, various modifications can be made without departing from the spirit of the present invention.

  In the above-described embodiment, the example in which the semiconductor device (insulating layer 10) warps downward and the semiconductor element 1 protrudes upward has been described. However, the semiconductor device (insulating layer 10) warps upward. The present invention can also be applied to an example in which the semiconductor element 1 is convex downward. In addition, when the warp of the semiconductor device 1 (insulating layer 10) and the semiconductor element 1 is in the same direction, and the warp amount of the semiconductor element 1 is larger, the present invention can be suitably applied.

DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Semiconductor substrate 3 Opening part (substrate penetration part, substrate spot part)
6 Filler 10 Insulating layer 11 First insulating layer 12 Second insulating layer 13 Third insulating layer 14 Fourth insulating layer 15 Fifth insulating layer 19 Adhesive layer 20 Wiring structure 21 First wiring layer 22 Second wiring layer 23 Third Wiring layer 24 Fourth wiring layer 25 Fifth wiring layer 26 Sixth wiring layer 30 Element connection plug 31 First through plug 32 Second through plug 33 Third through plug 34 Fourth through plug 35 Fifth through plug 41 Via 42 Via 45 Support 46 Solder Resist 47 External Terminal 50 Semiconductor Device

Claims (19)

A semiconductor device comprising a semiconductor substrate;
An insulating layer in which the semiconductor element is embedded;
And at least a part of the wiring structure connected to the semiconductor element,
The semiconductor substrate is a semiconductor device having one or more openings formed on at least one main surface side of the semiconductor substrate,
The opening is a void, or a part or all of the opening is filled with an insulating material as a main component and an elastic modulus of 5 MPa or more and 5 GPa or less , provided that the filler Is a semiconductor device characterized by not having conductivity as a whole . The semiconductor device according to claim 1 , wherein the opening is provided at least in the vicinity of an outer peripheral portion of the semiconductor substrate. The opening, the semiconductor device according to claim 1 or 2, characterized in that a substrate through portion that penetrates the semiconductor substrate. The substrate penetrating portion is a combination of a groove provided on one main surface side of the semiconductor substrate and a plurality of through holes penetrating from the groove to the other main surface side of the semiconductor substrate. The semiconductor device according to claim 3. Wherein the shape of the openings, the semiconductor device according to claim 1 or 2, characterized in that a recess shape that does not penetrate the semiconductor substrate. 6. The semiconductor device according to claim 5 , wherein the depth of the concave portion is set to be not less than half of the thickness of the semiconductor substrate. The semiconductor device according to claim 5 , wherein the recess is formed on a side opposite to an element formation surface of the semiconductor substrate. A plurality of the openings are formed,
Wherein the plurality of openings, wherein the semiconductor substrate, axisymmetric, or / and a semiconductor device according to any one of claims 1 to 7, characterized in that it is formed in point symmetry. The insulating layer includes an adhesive layer;
A first main surface of the adhesive layer is in contact with one main surface side of the semiconductor substrate;
It said first major surface and a second major surface opposite to the adhesive layer, a semiconductor according to any one of claims 1 to 8, characterized in that contact with the formed wiring layer by the wiring structure apparatus. The through-hole reaching the wiring layer is provided in the adhesive layer, and the filler is filled in the through-hole of the opening and the adhesive layer. 9. The semiconductor device according to 9. The wiring structure, a semiconductor device according to any one of claims 1 to 10, characterized in that it comprises a multi-layer wiring layer. The semiconductor device according to any one of claims 1 to 11, characterized in that said insulating layer, further electronic components are mounted. Forming a semiconductor element;
Mounting the semiconductor element on a support;
A step of incorporating the semiconductor element with an insulating layer;
Forming a wiring structure so that at least a portion is connected to the semiconductor element;
And removing the support.
In the step of forming the semiconductor element, one or more openings are formed on at least one main surface side of the semiconductor substrate included in the semiconductor element,
A step of leaving an opening formed in the semiconductor substrate as a void, or filling a part or all of the opening with a filler having an insulating material as a main component and an elastic modulus of 5 MPa or more and 5 GPa or less. including, however, a method of manufacturing a semiconductor device you characterized in that the filler is not electrically conductive as a whole. The method of manufacturing a semiconductor device according to claim 13 , wherein the opening is provided so as to penetrate the semiconductor substrate. The method of manufacturing a semiconductor device according to claim 13 , wherein the opening is provided in the semiconductor substrate so as to form a recess that does not penetrate the semiconductor substrate . 16. The method of manufacturing a semiconductor device according to claim 15 , wherein the depth of the concave portion is set to half or more of the thickness of the semiconductor substrate. The method of manufacturing a semiconductor device according to claim 15 , wherein the recess is formed on a side opposite to an element formation surface of the semiconductor substrate. The wiring structure includes a multilayer wiring layer,
18. The method of manufacturing a semiconductor device according to claim 13 , wherein at least a part of the multilayer wiring layer is formed after the support is removed. The wiring structure includes a multilayer wiring layer,
The method for manufacturing a semiconductor device according to claim 13 , wherein the multilayer wiring layer is formed before the support is removed.