JP5548855B2 - Wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a wiring board having a built-in electronic component and a manufacturing method thereof.

  As electronic devices become lighter, thinner and smaller, high-density mounting technology in semiconductor packages is progressing along with miniaturization and high integration of semiconductor elements.

  In packaging of a semiconductor element such as an IC chip, the connection between the wiring board and the semiconductor element in the package is performed by wire bonding connection using a gold wire or the like, or flip chip connection using a solder ball or the like.

  Wire bonding connection has the merit that it can be packaged at low cost when the number of connection pads of the semiconductor element is small, but it is necessary to reduce the wire diameter as the number of connection pads increases and the pitch becomes narrower. There is a problem that the yield decreases due to assembly failure such as cutting. Further, in the wire bonding connection, since a certain distance is required for the connection path between the terminal of the semiconductor element and the terminal of the wiring board, there is a problem that the high-speed transmission characteristics are likely to deteriorate.

  Flip-chip connection enables high-speed signal transmission because the connection path between the semiconductor element and the wiring board is shorter than wire bonding connection, and terminals can be provided not only around the circuit surface of the semiconductor element but also throughout. Therefore, the number of connection terminals can be increased. However, as the number of connection pads of the semiconductor element increases and the pitch becomes narrower, the connection strength becomes weaker as the size of the solder bumps becomes smaller. Therefore, there is a problem that connection defects such as cracks are likely to occur.

  In recent years, as a high-density mounting technology that facilitates further higher density and higher functionality of a semiconductor device, a package technology in which a semiconductor element is embedded in a wiring board, a so-called semiconductor element built-in technology has been proposed.

  For example, Patent Document 1 has a lower wiring board, a semiconductor element provided on the lower wiring board, and a through hole formed by hollowing out a portion corresponding to the semiconductor element, and the semiconductor element is placed in the through hole. A multilayer wiring substrate with a built-in semiconductor element is described which includes an intermediate wiring substrate provided on a lower wiring substrate so as to be accommodated and an upper wiring substrate provided on the intermediate wiring substrate. The insulating layer of each wiring board is formed of an insulating material made of a thermoplastic resin such as an epoxy resin and an inorganic material such as glass fiber. Between the wiring boards and between the wiring board and the semiconductor element, a prepreg having almost the same composition as this insulating material is provided, and the space around the semiconductor element is filled with this prepreg by reducing the pressure under heating and pressurization. It is cured. It is described that according to such a structure, stress caused by the surroundings of the built-in semiconductor element can be suppressed, and troubles caused by the stress can be prevented.

  Patent Document 2 discloses a step of adhering a semiconductor element on a first sheet and a second sheet made of an insulating resin in the middle of a curing reaction and having an opening so that the semiconductor element is accommodated in the opening. A step of placing on the first sheet, a step of placing on the second sheet a conductive third sheet provided on the side where the insulating resin layer in the middle of the curing reaction faces the second sheet, A step of collectively thermocompression bonding the first, second and third sheets, a step of electrically connecting the electrodes of the semiconductor element and the third sheet, and a step of patterning the third sheet to form wiring. The manufacturing method of the board | substrate with a built-in semiconductor element containing is described. In order to prevent the flatness of the surface after thermocompression bonding from being impaired, it is described that a prepreg material containing a glass cloth can be used for the second sheet.

  Japanese Patent Application Laid-Open No. H11-228707 is a wiring board with a built-in semiconductor chip, and has an insulating layer in which the semiconductor chip is embedded, and a wiring structure connected to the semiconductor chip, and the insulating layer includes the insulating layer. A wiring board is described in which a reinforcing structure for reinforcing the structure is embedded. It is described that the reinforcing structure can be formed so as to surround the semiconductor chip on the same plane as the semiconductor chip. Further, it is described that the reinforcing structure can be formed of an organic core material (prepreg material) or a metal material. According to such a configuration, it is described that the wiring board incorporating the semiconductor chip can be thinned and the warping of the wiring board can be suppressed.

JP 2002-270712 A Japanese Patent Laid-Open No. 2004-335641 JP 2006-261246 A

  Wiring boards with built-in electronic components are required to be made thinner, but it is difficult to reduce the thickness while ensuring the rigidity of the entire board and suppressing warpage.

  An object of the present invention is to provide a thin wiring board with excellent rigidity and a built-in electronic component, and a method for manufacturing the wiring board.

According to one aspect of the invention,
A base insulating layer;
A pedestal pattern provided on the upper surface side of the base insulating layer;
Electronic components provided on the pedestal pattern;
A reinforcing insulating layer provided on an upper surface side of the base insulating layer and surrounding an outer periphery of the electronic component;
A core provided on the reinforcing insulating layer, including a core insulating layer having an opening in which the electronic component is disposed, a core wiring on an upper surface side of the core insulating layer, and a core wiring on a lower surface side of the core insulating layer A wiring structure layer;
A buried insulating layer provided on the core wiring structure layer so as to embed the electronic component;
A first wiring electrically connected to the electronic component and provided on the buried insulating layer;
A wiring board including a second wiring provided on a lower surface side of the base insulating layer,
The outer edge of the pedestal pattern is located outside the outer edge of the electronic component,
The reinforcing insulating layer includes a first reinforcing fiber, and the first reinforcing fiber is provided from a peripheral region outside the outer edge of the pedestal pattern to a position immediately above the outer edge of the pedestal pattern. .

According to another aspect of the invention,
Forming a base pattern wider than the surface on the electronic component mounting side on the base insulating layer on the support substrate;
Mounting the electronic component on the pedestal pattern so as to be arranged on the inner side of the outer edge of the pedestal pattern; and
A step of providing a reinforcing insulating layer including an opening that can be disposed inside an outer edge of the pedestal pattern and can be disposed inside the electronic component;
Providing a core wiring structure layer including a core insulating layer having an opening capable of disposing the electronic component inside, a core wiring on an upper surface side of the core insulating layer, and a core wiring on a lower surface side of the core insulating layer;
The electronic component is disposed inside the opening of the reinforcing insulating layer, and the first reinforcing fiber is disposed from a peripheral region outside the outer edge of the pedestal pattern to directly above the outer edge of the pedestal pattern. Overlying the base insulating layer;
Superimposing the core wiring structure layer on the reinforcing insulating layer so that the electronic component is disposed inside the opening;
Overlaying a buried insulating layer on the reinforcing insulating layer so as to cover the electronic component;
Heating is performed to fluidize the reinforcing insulating layer and the embedded insulating layer to fill a space around the electronic component, and to cure the base. The base insulating layer, the reinforcing insulating layer, the core wiring structure layer, and the embedded Crimping the insulating layer;
Forming a first wiring on the buried insulating layer;
Removing the support substrate before or after forming the first wiring;
A method of manufacturing a wiring board is provided, which includes a step of forming a second wiring on the lower surface side of the base insulating layer.

  ADVANTAGE OF THE INVENTION According to this invention, the thin wiring board excellent in rigidity and incorporating an electronic component and its manufacturing method can be provided.

Sectional drawing which showed the wiring board of embodiment of this invention typically. Sectional drawing which showed typically the wiring board of other embodiment of this invention. Sectional drawing which showed typically the wiring board of other embodiment of this invention. The typical sectional view for explaining the manufacturing method of the wiring board of the embodiment of the present invention. Typical sectional drawing for demonstrating the process following the process shown in FIG. FIG. 6 is a schematic cross-sectional view for explaining a step that follows the step shown in FIG. 5. Sectional drawing which showed typically the wiring board of other embodiment of this invention.

  A preferred embodiment of the present invention will be described below.

  FIG. 1 is a cross-sectional view schematically showing a wiring board according to an embodiment of the present invention.

  In the wiring board of the present embodiment, a plate-like pedestal pattern 102 is provided on the insulating base layer 101, and the electronic component 200 is provided on the pedestal pattern via an adhesive layer 103. Further, a reinforcing insulating layer 110 surrounding the outer periphery of the electronic component 200 is provided on the insulating base layer 101. This reinforcing insulating layer includes first reinforcing fibers 111.

  A core wiring structure layer 120 is provided on the reinforcing insulating layer 110. The core wiring structure layer has an opening, and the electronic component 200 is disposed inside the opening. The core wiring structure layer 120 includes a core insulating layer 121 provided with the opening, a core wiring 122 on the upper surface side of the core insulating layer, and a core wiring 123 on the lower surface side. The core wiring 122 on the upper surface side and the core wiring 123 on the lower surface side can be connected via vias penetrating the core insulating layer 121 as shown in FIG.

  An embedded insulating layer 130 is provided on the core wiring structure layer 120 so as to embed the electronic component 200.

  A first wiring structure layer 140 is provided on the buried insulating layer 130. The first wiring structure layer includes a first wiring 141a electrically connected to the electronic component 200, a first insulating layer 142a on the first wiring, a first wiring 141b on the first insulating layer, A protective insulating layer 142b is included. A protective insulating layer (for example, a solder resist layer) 142b is provided so that a part of the first wiring 141b on the upper layer side is exposed, and the exposed portion of the first wiring 141b can be used as an external terminal. The first wiring 141a on the lower layer side and the first wiring 141b on the upper layer side are connected via a via penetrating the first insulating layer 142a.

  The first wiring 141 a on the lower layer side and the upper core wiring 122 on the core wiring structure layer 120 are connected via vias that penetrate the buried insulating layer 130. Thereby, since the board | substrate internal area | region around an electronic component is utilized effectively, a high-density wiring is attained.

  The first wiring structure layer 140 may further have a multilayer wiring structure in which one or more wirings and one or more insulating layers are alternately stacked. In the structure shown in FIG. 1, the first wiring 141a is provided directly on the buried insulating layer 130. However, another insulating layer may be provided on the buried insulating layer 130 and the first wiring 141a may be provided thereon. Good.

  A second wiring structure layer 150 is provided on the lower surface side of the base insulating layer 101 (the side opposite to the side on which electronic components are mounted). The second wiring structure layer 150 includes a second wiring 151 and a protective insulating layer (for example, a solder resist layer) 152 provided so that a part of the second wiring 151 is exposed. The exposed portion of the second wiring 151 can be used as an external terminal.

  As shown in FIG. 1, the second wiring 151 and the lower core wiring 123 can be connected via vias that penetrate the base insulating layer 101 and the reinforcing insulating layer 110. Thereby, since the board | substrate internal area | region around an electronic component is utilized effectively, high-density wiring is attained also in the lower surface side of a wiring board. Further, when the upper layer side core wiring 122 and the lower layer side core wiring 123 are connected via the via 124, the wiring on the upper surface side and the lower surface side of the wiring substrate, and the upper surface of the core wiring structure layer 120. Since the wiring on the side and the lower surface side is electrically connected, the area on the upper surface side of the wiring board, the area on the lower surface side of the wiring board, and the board internal area around the electronic component can be used as one wiring area. High density wiring can be formed. In addition, since the external terminals on the upper surface side of the wiring board and the external terminals on the lower surface side are electrically connected, design freedom can be achieved by connecting other electronic components to both the upper surface side and the lower surface side of the wiring board. A high-density and high-density system can be configured. In addition, since the electronic components connected to the upper surface side and the lower surface side of the wiring board can be connected at a short distance, device performance can be improved. The second wiring structure layer 150 may further have a multilayer wiring structure in which one or more wirings and one or more insulating layers are alternately stacked. By providing the second wiring structure layer, the lower surface side of the wiring board can also be used as a wiring board, and high-density packaging becomes possible. Further, the effect of suppressing warpage can be obtained by making the structures such as the number of laminated layers of wirings and insulating layers and the material type close between the first wiring structure layer and the second wiring structure layer.

  The wiring board of this embodiment is wider than the lower surface of the built-in electronic component (the surface facing the pedestal pattern: hereinafter referred to as “mounting surface”) from the viewpoint of ensuring rigidity and suppressing warpage while achieving a reduction in thickness. A pedestal pattern 102 is provided on the base insulating layer 101, the electronic component 200 is arranged inside the outer edge of the pedestal pattern 102, and a reinforcing insulating layer 110 surrounding the periphery of the electronic component 200 mounted on the pedestal pattern is provided. Is provided. The reinforcing insulating layer 110 includes reinforcing fibers 111. Since the electronic component 200 is disposed inside the outer edge of the pedestal pattern, no electronic component is disposed immediately above the outer edge of the pedestal pattern, and a reinforcing insulating layer is disposed. That is, the base pattern 102 has an outer peripheral portion that extends to a peripheral region outside the outer edge of the electronic component mounting surface. An end portion of the reinforcing fiber 111 facing the side surface of the electronic component is arranged immediately above the outer edge (end portion of the outer peripheral portion) of the pedestal pattern 102, that is, the reinforcing fiber 111 is an end facing the electronic component. The portion is arranged so as to overlap the outer edge of the base pattern 102. This overlapping portion corresponds to a size W portion in FIG. From the viewpoint of obtaining sufficient rigidity, it is preferable that the overlapping portion surrounds the outer periphery of the electronic component 200. Since the electronic component mounting region is reinforced by the pedestal pattern and the peripheral region of the pedestal pattern is reinforced by the reinforcing fiber, sufficient rigidity can be obtained over the entire wiring board. In particular, it is possible to effectively reinforce by providing an overlapping portion between the base pattern and the reinforcing fiber so that there is no gap in the substrate plane direction. At that time, it is desirable that the reinforcing fiber is not brought into contact with the electronic component in terms of insulation reliability and prevention of damage to the electronic component during the manufacturing process.

  The size W of the overlapping portion is preferably 10 μm or more, and more preferably 20 μm or more from the viewpoint of the reinforcing effect and overlay accuracy. The size W of the overlapping portion can be set as appropriate according to the size of the electronic component as long as the size is equal to or larger than this size. However, in order to reduce the size while securing the interval between the reinforcing fiber and the electronic component, the size is 100 μm or less. Can be set. Here, the size W of the overlapping portion refers to the length in the direction perpendicular to the outer periphery (lower surface outer periphery) of the electronic component mounting surface in the substrate plane direction. When the shape of the mounting surface (the lower surface of the electronic component) is square or rectangular, it corresponds to the length in the direction perpendicular to the side, and when the outer periphery of the mounting surface is a curve, it corresponds to the length in the normal direction. .

  The size L of the outer peripheral portion of the pedestal pattern on which the electronic component is mounted is preferably 60 μm or more from the viewpoint of obtaining a sufficient overlapped portion size W while ensuring the interval between the reinforcing fiber and the electronic component, and the processing accuracy. 110 micrometers or more are more preferable, and 160 micrometers or more are further more preferable. If it is more than this size, it can be set as appropriate according to the size of the electronic component, but it can be set to 200 μm or less from the viewpoint of miniaturization and the like. Here, the outer peripheral portion of the pedestal pattern on which the electronic component is mounted refers to a portion outside the electronic component in the pedestal pattern. ) In the direction perpendicular to. When the shape of the mounting surface (the lower surface of the electronic component) is square or rectangular, it corresponds to the length in the direction perpendicular to the side, and when the outer periphery of the mounting surface is a curve, it corresponds to the length in the normal direction. .

  In the overlapping part of the base pattern and the reinforcing fiber, the distance between the base pattern and the reinforcing fiber (distance perpendicular to the substrate plane, D in FIG. 1) is as short as possible from the viewpoint of obtaining a sufficient reinforcing effect. Is preferably 50 μm or less, and more preferably 30 μm or less. When the pedestal pattern is formed of a non-conductive material or is coated with a non-conductive material, the pedestal pattern and the reinforcing fiber may be in contact with each other. When the pedestal pattern is formed of a conductive material, it is desirable to avoid mutual contact from the viewpoint of ensuring insulation, and the distance (D) between the pedestal pattern and the reinforcing fiber is preferably 5 μm or more, 10 μm or more is more preferable.

  The size of the pedestal pattern ensures sufficient overlap between the pedestal pattern and the reinforcing fibers, and the rigidity of the wiring board is improved by the pedestal pattern itself, so that the electronic components can be placed inside the outer edge of the pedestal pattern, It is desirable that it is sufficiently wider than the electronic component mounting surface. Further, when a pedestal pattern made of a material having high thermal conductivity is used, heat dissipation can be enhanced by widening the pedestal pattern. If the pedestal pattern is too narrow with respect to the mounting surface of the electronic component, the effect of reinforcement by the pedestal pattern is reduced, and a sufficient overlapping portion between the pedestal pattern and the reinforcing fibers cannot be secured. On the other hand, if the pedestal pattern is too wide, it is necessary to avoid the pedestal pattern when forming wiring in the thickness direction around the electronic component (particularly, forming vias), thereby preventing the formation of high-density wiring.

  The planar shape of the pedestal pattern is not particularly limited as long as the overlapping portion between the pedestal pattern and the reinforcing fiber is sufficiently provided. Square, rectangular, other polygons, circles, ellipses, crosses, and holes in these The shape which provided is mentioned. From the viewpoint of evenly reinforcing the periphery of the electronic component, the shape can be made in accordance with the shape of the outer edge of the mounting surface of the electronic component. When the planar shape of the electronic component mounting surface is square, the planar shape of the pedestal pattern can be square. When the planar shape of the electronic component mounting surface is rectangular (rectangular), the planar shape of the pedestal pattern can be a rectangle similar to the planar shape of the electronic component mounting surface. The size L of the outer peripheral portion of the pedestal pattern on which the electronic component is mounted is desirably uniform over the periphery of the electronic component.

  The material of such a pedestal pattern can be appropriately selected from various metals and inorganic materials that have a reinforcing effect on the wiring board. For example, in addition to the reinforcing effect, copper or a copper alloy can be suitably used from the viewpoint of ease of processing and thermal conductivity. The thickness of this pedestal pattern can be appropriately set according to the desired effect, but is preferably 3 μm or more, more preferably 6 μm or more, and even more preferably 10 μm or more from the viewpoint of the reinforcing effect and thermal conductivity. From the viewpoint of workability and thinning, 40 μm or less is preferable, and 30 μm or less is more preferable. For example, a pedestal pattern made of copper having a thickness of 20 μm can be formed.

  As the reinforcing fiber, a fiber sheet made of woven fabric or nonwoven fabric can be used. Glass fiber is preferable from the viewpoint of strength and heat resistance, and glass cloth can be particularly preferably used. The thickness of the reinforcing fiber sheet is preferably 10 μm or more from the viewpoint of obtaining a sufficient reinforcing effect, preferably 20 μm or more, and preferably 200 μm or less, more preferably 100 μm or less from the viewpoint of thinning the wiring board.

  It is preferable that the reinforcing fiber is disposed so as to surround the electronic component so that the reinforcing fiber does not contact the electronic component and its end portion overlaps the outer edge of the base pattern. As the reinforcing fibers arranged in this manner, a fiber sheet having an opening of a size that allows electronic components to be arranged inside is preferable. The opening shape can be a shape corresponding to the outer edge shape of the electronic component from the viewpoint of uniformly reinforcing the periphery of the electronic component. Moreover, this opening shape can be made into the shape corresponding to the outer edge shape of the base pattern from a viewpoint of making the overlapping width of a reinforcing fiber and a base pattern uniform over the circumference | surroundings of an electronic component.

  As shown in FIG. 1, the via 112 that penetrates the reinforcing insulating layer 110 preferably has an upper end diameter on the upper surface side of the substrate smaller than a lower end diameter on the lower surface side of the substrate. Since the via diameter on the side where the reinforcing fiber 111 is arranged is small, not only high-density connection is possible, but also the contact with the reinforcing fiber is difficult, and the insulation failure due to the fiber bridge with other adjacent conductive parts is reduced. Insulation reliability can be improved.

  In the present embodiment, the wiring (lower surface side core wiring 123) arranged on the upper surface side of the reinforcing insulating layer 110 is provided on the lower surface plane of the core insulating layer 121 and is covered with the reinforcing insulating layer 110. As a result, the side surface and the lower surface of the wiring are in contact with the reinforcing insulating layer 110. That is, the wiring 123 is embedded not on the core insulating layer 121 side but on the reinforcing insulating layer 110 side. For this reason, the wiring 123 and the reinforcing fiber 111 come close to each other, and the reinforcing effect can be enhanced. Further, as a result of the pedestal pattern 102 being covered with the reinforcing insulating layer 110, the side surface and the upper surface of the pedestal pattern are in contact with the reinforcing insulating layer 110. That is, the base pattern 102 is embedded not on the base insulating layer 101 side but on the reinforcing insulating layer 110 side. For this reason, the base pattern 102 and the reinforcing fiber 111 approach, and the reinforcing effect can be enhanced.

  As shown in FIG. 7, the lower surface side core wiring 123 may have a lower surface in the same plane as the core insulating layer 121 or in a recessed position. Since the lower surface side core wiring 123 is arranged on the core insulating layer 121 side from the boundary plane between the core insulating layer 121 and the reinforcing insulating layer 110, it is compared with the structure shown in FIG. 1 arranged on the reinforcing insulating layer 110 side. Thus, the gap between the reinforcing fiber 111 and the lower surface side core wiring 123 can be increased, which is advantageous in reducing the thickness.

  The core wiring structure layer 120 including such a lower surface side core wiring 123 can be formed as follows, for example. First, a resist mask having an opening pattern corresponding to a predetermined wiring pattern is formed on a support substrate made of a metal such as copper. Next, a conductive layer is formed in the opening pattern by plating. By removing the resist mask, a wiring made of this conductive layer (corresponding to the lower surface core wiring 123) is formed. Next, an insulating layer (corresponding to the core insulating layer 121) is provided on the support substrate on which the wiring is formed. Next, a via hole reaching the wiring is formed in this insulating layer. Next, a conductive layer is formed on the insulating layer so as to fill the via hole, and the conductive layer is patterned to form a wiring (corresponding to the upper surface side core wiring 122). Thereafter, the support substrate is removed by etching or polishing, and as a result, a wiring structure suitable for the core wiring structure layer 120 can be obtained. Using this wiring structure, the wiring board shown in FIG. 7 can be obtained according to the manufacturing method described later.

  The reinforcing fiber may be provided in the embedded insulating layer 130. Further, the reinforcing fiber may be provided in the core insulating layer 121. An example in which the reinforcing fiber is provided in both the buried insulating layer and the core insulating layer is shown in FIG. Further, the reinforcing fiber may be provided in the base insulating layer 101. As these reinforcing fibers, the same reinforcing fibers as the reinforcing fibers 111 provided in the reinforcing insulating layer 110 can be used.

  The wiring board of this embodiment can incorporate a semiconductor element (IC chip such as an LSI) as an electronic component. The semiconductor substrate included in the semiconductor element includes, for example, silicon, germanium, gallium arsenide (GaAs), gallium arsenide phosphorus, gallium nitride (GaN), silicon carbide (SiC), zinc oxide (ZnO), and other compound semiconductors (II− A substrate made of a group VI compound, a group III-V compound, a group VI compound), diamond, or the like can be used, but is not limited thereto. As the semiconductor element of this embodiment, an LSI chip using a silicon substrate can be suitably used. When the planar shape of the semiconductor element is a polygon such as a square or a rectangle (rectangle), one having a side of 0.5 mm to 22 mm and a circumference of 2 mm to 88 mm can be used from the viewpoint of processing accuracy, miniaturization, and the like. . The thickness of the semiconductor element is preferably 5 to 400 μm, more preferably 10 to 300 μm. For example, the thickness of the semiconductor element can be set to 50 μm, and the size can be set to 10 mm square.

  Moreover, chip parts, such as a capacitor | condenser, resistance, a diode, an inductor, and a filter, can also be incorporated as an electronic component. When the planar shape of the chip component is a polygon such as a square or a rectangle, one having a side of 0.1 mm to 2 mm and a circumference of 1 mm to 8 mm can be used from the viewpoints of processing accuracy and miniaturization. The thickness of the chip component is preferably 30 to 500 μm, and more preferably 50 to 200 μm. For example, the thickness of the chip component can be set to 50 μm, and the size can be set to 1.0 × 0.5 mm, 0.6 × 0.3 mm, and 0.4 × 0.2 mm.

  The wiring board according to the present embodiment may include a plurality of electronic components, a configuration including a plurality of semiconductor elements, a configuration including a plurality of chip components, and at least one semiconductor element and at least one chip component. The built-in form can be taken.

  Examples of wiring boards incorporating a plurality of electronic components are shown in FIGS.

  The structure shown in FIG. 2 is an example in which a plurality of pedestal patterns 102 are provided on the insulating base layer 101 and an electronic component is provided on each pedestal pattern. The structure shown in FIG. 3 is an example when a plurality of electronic components are provided on one pedestal pattern 102. Reference numeral 200a in the figure indicates a semiconductor element as an electronic component, and reference numeral 200b indicates a chip component as an electronic component. In the structure shown in FIG. 2, reinforcing fibers are provided so as to overlap the outer edge of each pedestal pattern, and reinforcing fibers are arranged around each electronic component. In the structure shown in FIG. 3, the reinforcing fibers are provided so as to overlap the outer edge of the base pattern on which a plurality of electronic components are mounted, and no reinforcing fibers are arranged between the electronic components. Reinforcing fibers may be disposed between the electronic components.

  The wiring board of this embodiment can be provided with fan-out wiring extending from the upper surface of the electronic component to the peripheral region as the first wiring 141a. Thereby, when an electronic component is a semiconductor element, a wiring structure and an external terminal can be formed with a pitch sufficiently enlarged with respect to the pitch in the semiconductor element. As a result, a higher-density semiconductor element can be incorporated, and connection reliability can be improved.

  As the materials of the base insulating layer 101, the reinforcing insulating layer 110, the core insulating layer 121, and the buried insulating layer 130 in this embodiment, insulating materials used for ordinary build-up substrates can be used. For example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, BCB (benzocycle), PBO (polybenzoxazole), and a polynorbornene resin can be given. The reinforcing insulating layer 110 includes the above-described reinforcing fibers. The other insulating layer preferably includes reinforcing fibers from the viewpoint of substrate rigidity, and preferably does not include reinforcing fibers from the viewpoint of forming a micro-diameter via.

  The material of the adhesive layer 103 in the present embodiment is not particularly limited as long as the electronic component can be fixed on the base insulating layer 101 with a desired strength. For example, a semi-cured resin called a die attachment film (DAF) or an epoxy resin is used. In addition, a resin paste such as polyimide resin, BCB (benzocycle), PBO (polybenzoxazole), or a silver paste can be used.

  The core wiring structure layer 120, the first wiring structure layer 140, and the second wiring structure layer 150 can be formed by using a normal printed wiring board manufacturing technique, and a build-up method that is particularly applicable to the formation of an interposer substrate is used. And can be suitably formed.

  Wirings included in these wiring structure layers can be formed by a subtractive method, a semi-additive method, a full additive method, or the like. In the semi-additive method, a power supply layer is formed by an electroless plating method, a sputtering method, a CVD method, etc., a resist having an opening in a desired pattern is formed, and a metal is deposited in the resist opening by an electrolytic plating method. This is a method of obtaining a desired wiring pattern by etching the power feeding layer after removing the wire. The subtractive method is a method in which a resist having a desired pattern is formed on a copper foil provided on a substrate or an insulating layer, an unnecessary copper foil is etched, and then the resist is removed to obtain a desired pattern. In the full additive method, after an electroless plating catalyst is adsorbed on a substrate or an insulating layer, a resist having a desired pattern is formed, and the catalyst is activated while leaving this resist as an insulating film. In this method, a desired wiring pattern is obtained by depositing metal in the opening of the insulating film.

  The thickness of the wiring is preferably 3 μm or more from the viewpoint of resistance, more preferably 5 μm or more, further preferably 10 μm or more, and on the other hand, 40 μm or less is preferable and 30 μm or less is more preferable from the viewpoint of workability and thinning.

  As a material for these wirings, a metal material composed of one or more selected from the group consisting of copper, silver, gold, nickel, aluminum, titanium, molybdenum, tungsten, and palladium can be used. In particular, copper is desirable from the viewpoint of electrical resistance and cost. For example, a wiring made of copper having a thickness of about 10 μm can be formed by a semi-additive method.

  As the material of the insulating layer of these wiring structure layers, a resin insulating material can be suitably used, and for example, it can be formed using a photosensitive or non-photosensitive organic material. Examples of such a material include epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocycle), PBO (polybenzoxole), and polynorbornene resin. Further, composite materials obtained by impregnating those resins with reinforcing fibers such as woven fabrics and nonwoven fabrics made of glass cloth or aramid fibers, those resins containing inorganic fillers or organic fillers, and silicon resins (silicone resins) can be mentioned. . For example, from the viewpoint of forming sufficient unevenness on the surface in order to improve the adhesion to the wiring, for example, an epoxy resin containing a filler that is advantageous for forming unevenness can be used.

  The thickness of the insulating layer is preferably 10 μm or more from the viewpoint of insulation reliability and impedance matching, more preferably 20 μm or more, and on the other hand, 200 μm or less is preferable and 100 μm or less is more preferable from the viewpoint of thinning. For example, it can be set to 20 μm. The thickness of the insulating layer provided alternately with the wiring in each wiring structure layer is the thickness direction from the upper surface of the insulating layer in contact with the lower surface of the lower wiring to the upper surface of the insulating layer in contact with the lower surface of the upper wiring (substrate The length along the direction perpendicular to the plane.

  The insulating layers of these wiring structure layers are formed by using, for example, a transfer molding method, a compression molding method, a printing method, a vacuum pressing method, a vacuum laminating method, a spin coating method, a die coating method, a curtain coating method, and a photolithography method. can do. For example, it can be satisfactorily formed by a vacuum laminating method using an epoxy resin containing a filler. When a photosensitive material is used, a via hole can be formed by a photolithography method. When a non-photosensitive material or an organic material that is photosensitive but has low pattern resolution is used, the via hole can be formed by laser, dry etching, blasting, or the like.

The wiring board described above may be provided with an LCR element that functions as a noise filter of a circuit in any of the wiring structure layers. Examples of the dielectric material constituting the capacitor include metal oxides such as titanium oxide, tantalum oxide, Al ₂ O ₃ , SiO ₂ , ZrO ₂ , HfO ₂ , and Nb ₂ O ₅ ; BST ((Ba _x , Sr _1-x ) TiO ₃ ), PZT (Pb (Zr _x , Ti _1-x ) O ₃ , PLZT ((Pb _1-y , La _y ) (Zr _x , Ti _1-x ) O ₃ ) and other perovskite materials (0 <X <1, 0 <y <1); Bi-based layered compounds such as SrBi ₂ Ta ₂ O ₉ are preferable, and an organic material mixed with an inorganic material or a magnetic material is used as a dielectric material constituting the capacitor. May be used.

  Hereinafter, the manufacturing method of the wiring board of this invention is demonstrated.

  4 to 6 are schematic cross-sectional views for explaining the method for manufacturing the wiring board of the present embodiment.

  First, a substrate provided with a base insulating layer 101 over a supporting substrate 100 is prepared. A base pattern 102 is formed on the base insulating layer 101 by a semi-additive method or a full additive method used in a normal build-up method (FIG. 4A). Examples of the support substrate include metal plates (copper, copper alloy, aluminum, stainless steel, etc.), glass plates, ceramic plates, and Si wafers. In particular, a copper alloy can be suitably used.

  Next, as shown in FIG. 4B, the electronic component 200 is provided on the pedestal pattern 102 via an adhesive layer.

  Next, as shown in FIG. 4C, the reinforcing insulating layer 110, the core wiring structure layer 120, the buried insulating layer 130, and the protective layer 201 are overlaid in this order on the substrate on which the electronic component 200 is provided.

  The reinforcing insulating layer 110 is a semi-cured resin sheet made of a thermosetting resin including reinforcing fibers such as glass cloth, and is provided with an opening in which the electronic component 200 can be disposed inside. During the formation of the opening, the opening is also formed in the reinforcing fiber. The resin sheet is disposed such that the electronic component is disposed in the opening and the entire opening is located inside the outer edge of the base pattern. At that time, the size of the opening and the size of the pedestal pattern are set so that the peripheral edge of the opening of the reinforcing fiber and the outer edge of the pedestal pattern can overlap each other with a predetermined size. The thickness of the reinforcing insulating layer is preferably set such that the upper surface of the cured insulating insulating layer is lower than the upper surface of the electronic component provided on the pedestal pattern. Thereby, the core wiring structure layer 120 can be arrange | positioned around an electronic component, and thickness reduction of a wiring board can be achieved.

  As the core wiring structure layer 120, a layer in which a desired wiring structure is formed in advance using a normal printed wiring board manufacturing technique can be used. The wiring structure layer is provided with an opening through which the electronic component 200 can be disposed. As the core insulating layer of the core wiring structure layer, a cured resin insulating layer can be used, which may contain a reinforcing material such as a reinforcing fiber from the viewpoint of improving the rigidity of the wiring board, The reinforcing material may not be included from the point. The core wiring structure layer 120 is overlaid on the reinforcing insulating layer 110 so that the electronic component is disposed in the opening.

  The embedded insulating layer 130 is a semi-cured resin sheet made of a thermosetting resin, and may contain a reinforcing material such as a reinforcing fiber from the viewpoint of improving the rigidity of the wiring board, or the formation of a fine via or the like. The reinforcing material may not be included. The buried insulating layer is overlaid on the core wiring structure layer 120 so as to cover the electronic component.

  As the protective layer 201, those used in ordinary printed wiring board manufacturing techniques can be used, and examples thereof include Cu foil and heat-resistant film.

  After laminating as described above, heat treatment is performed by a normal vacuum press method. Instead of this vacuum press method, a heat pressing process by a normal laminating method may be performed. As a result of this thermocompression treatment, the layers are pressure-bonded, and as shown in FIG. 4D, the resin of the reinforcing resin layer and the resin of the embedded insulating layer are fluidized, filled in the gap around the electronic component, and cured. .

  Next, as shown in FIG. 5A, the support substrate 100 and the protective layer 201 are removed. When the support substrate is formed of a copper alloy and the protective layer is formed of a copper foil, it can be removed simultaneously by wet etching. The removal of the protective layer and the removal of the support substrate may be performed separately. Alternatively, the support substrate may be removed after the protective layer 201 is removed and a base insulating layer 131 described later is formed.

  Next, as shown in FIG. 5B, a base insulating layer 131 is formed on the buried insulating layer 130 by a vacuum press method or a laminate method. This base insulating layer can also be formed by spin coating or printing. As the material of the base insulating layer, an insulating material used for the above-described normal build-up substrate can be used. The base insulating layer can be provided as necessary, and the next step may be performed without providing the base insulating layer.

  Next, as shown in FIG. 5C, holes for forming vias are formed by a laser method. From the upper surface side of the substrate, a hole 161a reaching the upper surface side wiring of the core wiring structure layer and a hole 161c reaching the terminal of the electronic component are formed. A hole 161b reaching the lower surface side wiring of the core wiring structure layer is formed from the lower surface side of the substrate. By forming a hole from the substrate lower surface side, it is possible to form a hole whose hole upper end diameter on the core wiring structure layer side is smaller than the hole lower end diameter on the substrate lower surface side. By forming a via in this hole, a via having a via upper end diameter on the core wiring structure layer side smaller than a via lower end diameter on the substrate lower surface side can be formed. These holes can be formed by a photolithography method, a blast method, an etching method, or the like instead of the laser method.

  Next, as shown in FIG. 5D, holes are filled and wirings 141a and 151a are formed by a semi-additive method or a subtractive method used in a normal build-up method. The hole may not be filled as long as a desired electrical connection path is formed. The wiring may be formed after filling the hole with a conductive material such as a conductive paste.

  When a buried insulating layer not containing reinforcing fibers is used, the connection between the terminal of the electronic component and the wiring on the upper layer side can also be formed as follows. A bump is formed in advance on a terminal of the electronic component, a buried insulating layer is formed on the electronic component on which the bump is formed, and the insulating layer (buried insulating layer) on the bump is removed to expose the upper surface of the bump. Then, a wiring is formed so as to connect to the bump.

  Next, as shown in FIG. 5E, insulating layers 142a and 152a are formed by a vacuum press method or a laminate method. These insulating layers can also be formed by spin coating or printing. As the material for these insulating layers, the insulating material used for the above-described ordinary build-up substrate can be used.

  Next, as shown in FIG. 6A, holes for forming vias are formed by a laser method. A hole 162a reaching the wiring 141a is formed from the upper surface side of the substrate. A hole 162b reaching the wiring 151a is formed from the lower surface side of the substrate. These holes can be formed by a photolithography method, a blast method, an etching method, or the like instead of the laser method.

  Next, as shown in FIG. 6B, holes are filled and wirings 141b and 151b are formed by a semi-additive method or a subtractive method used in a normal build-up method. The hole may not be filled as long as a desired electrical connection path is formed. The wiring may be formed after filling the hole with a conductive material such as a conductive paste.

  Next, as shown in FIG. 6C, solder resist layers 142b and 152b are formed according to a normal method. The exposed part of the wiring can be used as a terminal. A bump may be formed by providing a solder material on the exposed portion according to a normal method.

DESCRIPTION OF SYMBOLS 100 Support substrate 101 Base insulating layer 102 Base pattern 103 Adhesive layer 110 Reinforcing insulating layer 111 1st reinforcing fiber 112 Via 120 Core wiring structure layer 121 Core insulating layer 122 Upper surface side core wiring 123 Lower surface side core wiring 124 Via 130 Embedded insulating layer 131 Base insulating layer 140 First wiring structure layer 141a First wiring 141b First wiring 142a First insulating layer 142b Protective insulating layer (solder resist layer)
150 Second wiring structure layer 151 Second wiring 151a Second wiring 151b wiring 152 Protective insulating layer (solder resist layer)
152a Second insulating layer 152b Solder resist layer 161a hole 161b hole 161c hole 162a hole 162b hole 200 electronic component 200a semiconductor element 200b chip component 201 protective layer

Claims (23)

A base insulating layer;
A pedestal pattern provided on the upper surface side of the base insulating layer;
Electronic components provided on the pedestal pattern;
A reinforcing insulating layer provided on an upper surface side of the base insulating layer and surrounding an outer periphery of the electronic component;
A core provided on the reinforcing insulating layer, including a core insulating layer having an opening in which the electronic component is disposed, a core wiring on an upper surface side of the core insulating layer, and a core wiring on a lower surface side of the core insulating layer A wiring structure layer;
A buried insulating layer provided on the core wiring structure layer so as to embed the electronic component;
A first wiring electrically connected to the electronic component and provided on the buried insulating layer;
A wiring board including a second wiring provided on a lower surface side of the base insulating layer,
The outer edge of the pedestal pattern is located outside the outer edge of the electronic component,
The reinforcing insulating layer includes a first reinforcing fiber, and the first reinforcing fiber is arranged from a peripheral region outside the outer edge of the pedestal pattern to directly above the outer edge of the pedestal pattern.   The said 1st reinforcement fiber is a fiber sheet with the opening by which the said electronic component was arrange | positioned inside, The peripheral edge part of opening of this fiber sheet is arrange | positioned just above the outer edge of the said base pattern. Wiring board as described in. A plurality of pedestal patterns are provided on the insulating base layer,
The wiring board according to claim 1, wherein an electronic component is provided on each pedestal pattern.   The wiring board according to claim 1, wherein a plurality of electronic components are provided on the base pattern.   The wiring board according to claim 1, wherein a semiconductor element is incorporated as the electronic component.   The wiring board according to claim 1, wherein a chip part is incorporated as the electronic part.   The wiring board according to claim 3, wherein a semiconductor element and a chip component are incorporated as the electronic component.   The wiring board according to claim 4, wherein a semiconductor element and a chip component are incorporated as the electronic component.   The wiring board according to claim 6, wherein the chip component is selected from a capacitor, a resistor, a diode, an inductor, and a filter. The core wiring structure layer includes a via that penetrates the core insulating layer and connects the upper surface side core wiring and the lower surface side core wiring,
The upper surface side core wiring is electrically connected to the first wiring through a via penetrating the buried insulating layer,
10. The wiring board according to claim 1, wherein the lower surface side core wiring is electrically connected to the second wiring through a via penetrating the reinforcing insulating layer. 11.   The wiring board according to claim 10, wherein the via penetrating the reinforcing insulating layer has an upper end diameter on the upper surface side of the substrate smaller than a lower end diameter on the lower surface side of the substrate.   The wiring board according to any one of claims 1 to 11, wherein the lower surface side core wiring is located at a position where a lower surface protrudes from a lower surface of the core insulating layer.   The wiring substrate according to claim 1, wherein the lower surface side core wiring has a lower surface in the same plane as the lower surface of the core insulating layer.   The wiring board according to claim 1, wherein the first reinforcing fiber is a glass fiber.   The wiring board according to claim 1, wherein the embedded insulating layer includes a second reinforcing fiber.   The wiring board according to claim 1, wherein the core insulating layer includes a third reinforcing fiber. A protective insulating film covering the first wiring;
The protective insulating film has an opening, and includes an external terminal formed of an exposed portion of the first wiring in the opening or an external terminal formed of a conductive portion provided in the opening. The wiring board according to claim 1. A first wiring structure layer including wiring and insulating layers alternately provided on the buried insulating layer;
17. The device according to claim 1, wherein the uppermost insulating layer has an opening, and includes an external terminal formed of an exposed portion of the wiring in the opening or an external terminal formed of a conductive portion provided in the opening. The wiring board according to one item. A protective insulating film covering the second wiring;
19. The device according to claim 1, wherein the protective insulating film has an opening, and includes an external terminal formed of an exposed portion of the second wiring in the opening or an external terminal formed of a conductive portion provided in the opening. The wiring board according to claim 1. A second wiring structure layer including wiring and insulating layers alternately provided on the lower surface side of the base insulating layer;
19. The device according to claim 1, further comprising an external terminal formed of an exposed portion of the wiring in the opening or an external terminal formed of a conductive portion provided in the opening. The wiring board according to one item. Forming a base pattern wider than the surface on the electronic component mounting side on the base insulating layer on the support substrate;
Mounting the electronic component on the pedestal pattern so as to be arranged on the inner side of the outer edge of the pedestal pattern; and
A step of providing a reinforcing insulating layer including an opening that can be disposed inside an outer edge of the pedestal pattern and can be disposed inside the electronic component;
Providing a core wiring structure layer including a core insulating layer having an opening capable of disposing the electronic component inside, a core wiring on an upper surface side of the core insulating layer, and a core wiring on a lower surface side of the core insulating layer;
The electronic component is disposed inside the opening of the reinforcing insulating layer, and the first reinforcing fiber is disposed from a peripheral region outside the outer edge of the pedestal pattern to directly above the outer edge of the pedestal pattern. Overlying the base insulating layer;
Superimposing the core wiring structure layer on the reinforcing insulating layer so that the electronic component is disposed inside the opening;
Overlaying a buried insulating layer on the reinforcing insulating layer so as to cover the electronic component;
Heating is performed to fluidize the reinforcing insulating layer and the embedded insulating layer to fill a space around the electronic component, and to cure the base. The base insulating layer, the reinforcing insulating layer, the core wiring structure layer, and the embedded Crimping the insulating layer;
Forming a first wiring on the buried insulating layer;
Removing the support substrate before or after forming the first wiring;
A method for manufacturing a wiring board, comprising a step of forming a second wiring on a lower surface side of the base insulating layer.   The method for manufacturing a wiring board according to claim 21, wherein a plurality of the pedestal patterns are provided, and electronic components are mounted on each pedestal pattern.   The method for manufacturing a wiring board according to claim 21, wherein a plurality of electronic components are mounted on the base pattern.

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