JP7486934B2 - Circuit Board - Google Patents

Description

The present invention relates to a circuit board and a manufacturing method thereof, and in particular to a circuit board having a multilayer wiring structure and a manufacturing method thereof.

The circuit board described in Patent Document 1 is known as an example of a circuit board having a multilayer wiring structure. The circuit board described in Patent Document 1 has a semiconductor IC embedded therein, and via conductors that connect upper and lower conductor layers are provided in positions that do not overlap with the semiconductor IC in a plan view.

JP 2013-229548 A

However, in the circuit board described in Patent Document 1, the angle of the inner wall of the via in which the via conductor is embedded is nearly perpendicular, so there is a possibility that the thickness of the conductor layer will be thin at the edge of the via, or that a break will occur in this area. To solve this problem, it would be possible to reduce the taper angle of the inner wall of the via, but in this case, the area occupied by the via will be large, which will hinder high-density mounting.

Therefore, the present invention aims to provide a circuit board that achieves high-density mounting while improving the connection reliability of via conductors.

A circuit board according to one aspect of the present invention includes first and second conductor layers, an insulating layer located between the first and second conductor layers, and a via conductor formed inside a via that penetrates the insulating layer and connects the first and second conductor layers, the via having a shape in which the diameter decreases in the depth direction, the via includes a first section located on the first conductor layer side and a second section located on the second conductor layer side, and the reduction in diameter per unit depth in the first section is greater than the reduction in diameter per unit depth in the second section.

According to the present invention, the angle of the edge located at the end of the first section of the via is reduced, which makes it possible to improve the connection reliability of the via conductor.

In the present invention, the first section may have a shape in which the amount of reduction in diameter per unit depth increases as the depth position becomes deeper. This makes it possible to increase the volume of the via.

The circuit board according to the present invention further includes a semiconductor IC embedded in the insulating layer, and the thickness of the semiconductor IC is less than the depth of the second section, and the depth position of the semiconductor IC may be within the range of the second section. This allows the semiconductor IC to be placed closer to the vias, thereby enabling high-density mounting to be achieved.

A circuit board according to another aspect of the present invention is a circuit board in which an electronic component is embedded, comprising an insulating layer covering a terminal electrode of the electronic component, a conductor layer covering the electronic component through the insulating layer, and a via conductor formed inside a via that penetrates the insulating layer and connects the terminal electrode and the conductor layer, the via having a shape in which the diameter decreases in the depth direction, the via includes a first section located on the conductor layer side and a second section located on the terminal electrode side, and the amount of reduction in diameter per unit depth in the first section is greater than the amount of reduction in diameter per unit depth in the second section.

In the present invention, the angle of the edge located at the end of the first section of the via is also reduced, making it possible to improve the connection reliability of the via conductor.

The method for manufacturing a circuit board according to the present invention is characterized by comprising the steps of preparing a structure including first and second conductor layers and an insulating layer located between the first and second conductor layers, patterning the first conductor layer to form an opening that exposes a portion of the insulating layer, performing laser processing on the center portion of the opening to form a via that penetrates the insulating layer, performing blast processing using the first conductor layer as a mask after the laser processing to enlarge the diameter of the upper portion of the via, and forming a via conductor inside the via to connect the first conductor layer and the second conductor layer.

According to the present invention, a two-stage process consisting of laser processing and blast processing is performed, making it possible to form a via having a first section and a second section with different shapes. This reduces the angle of the edge located at the end of the first section of the via, making it possible to improve the connection reliability of the via conductor.

In this way, the present invention makes it possible to provide a circuit board and a manufacturing method thereof that achieves high-density mounting while improving the connection reliability of the via conductors.

FIG. 1 is a schematic cross-sectional view for explaining the structure of a circuit board 100 with a built-in semiconductor IC according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view showing a state in which the circuit board 100 with a built-in semiconductor IC is mounted on the motherboard 10. As shown in FIG. FIG. 3 is a schematic cross-sectional view for explaining the shape of the via 253a. FIG. 4 is a schematic cross-sectional view for explaining the shape of a via 253a according to a modified example. FIG. 5 is a schematic cross-sectional view for explaining the positional relationship between the via 253 a and the semiconductor IC 300 . 6A to 6C are process diagrams for explaining a manufacturing method of the circuit board 100 with a built-in semiconductor IC. 7A to 7C are process diagrams for explaining a manufacturing method of the circuit board 100 with a built-in semiconductor IC. 8A to 8C are process diagrams for explaining a manufacturing method of the circuit board 100 with a built-in semiconductor IC. 9A to 9C are process diagrams for explaining a manufacturing method of the circuit board 100 with a built-in semiconductor IC. 10A to 10C are process diagrams for explaining a manufacturing method of the circuit board 100 with a built-in semiconductor IC. 11A to 11C are process diagrams for explaining a manufacturing method of the circuit board 100 with a built-in semiconductor IC. 12A to 12C are process diagrams for explaining a manufacturing method of the circuit board 100 with a built-in semiconductor IC. 13A to 13C are process diagrams for explaining a manufacturing method of the circuit board 100 with a built-in semiconductor IC. 14A to 14C are process diagrams for explaining a manufacturing method of the circuit board 100 with a built-in semiconductor IC. 15A to 15C are process diagrams for explaining a manufacturing method of the circuit board 100 with a built-in semiconductor IC. 16A to 16C are process diagrams for explaining a manufacturing method of the circuit board 100 with a built-in semiconductor IC. 17A to 17C are process diagrams for explaining a manufacturing method of the circuit board 100 with a built-in semiconductor IC. FIG. 18 is a schematic cross-sectional view illustrating the structure of a circuit board 200 with built-in thin film capacitors according to a second embodiment of the present invention. 19A to 19C are process diagrams for explaining a manufacturing method of the circuit board 200 with built-in thin film capacitors. 20A to 20C are process diagrams for explaining a manufacturing method of the circuit board 200 with built-in thin film capacitors. 21A to 21C are process diagrams illustrating a manufacturing method of the circuit board 200 with built-in thin film capacitors. 22A to 22C are process diagrams for explaining a manufacturing method of the circuit board 200 with built-in thin film capacitors.

A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First Embodiment
FIG. 1 is a schematic cross-sectional view for explaining the structure of a circuit board 100 with a built-in semiconductor IC according to a first embodiment of the present invention.

As shown in FIG. 1, the semiconductor IC built-in circuit board 100 according to this embodiment has four insulating layers 111-114 and conductor layers L1-L4 located on the surfaces of the insulating layers 111-114. Although not particularly limited, the uppermost insulating layer 111 and the lowermost insulating layer 114 may be core layers in which a core material such as glass fiber is impregnated with a resin material such as epoxy. In contrast, the insulating layers 112 and 113 may be made of a resin material that does not contain a core material such as glass cloth. In particular, it is preferable that the thermal expansion coefficient of the insulating layers 111 and 114 is smaller than that of the insulating layers 112 and 113.

The insulating layer 114 located at the bottom layer and a part of the conductor layer L1 formed on the surface of the insulating layer 114 may be covered with a solder resist 121. Similarly, the insulating layer 111 located at the top layer and a part of the conductor layer L4 formed on the surface of the insulating layer 111 may be covered with a solder resist 122. Although not particularly limited, the solder resist 121 forms the lower surface 101 of the circuit board 100 with a built-in semiconductor IC, and the solder resist 122 forms the upper surface 102 of the circuit board 100 with a built-in semiconductor IC. In this embodiment, an electronic component 400 may be mounted on the upper surface 102 of the circuit board 100 with a built-in semiconductor IC. The electronic component 400 may be a passive component such as a capacitor or an inductor. The electronic component 400 is sealed by a molded resin 130 that covers the upper surface 102 of the circuit board 100 with a built-in semiconductor IC. Although only one electronic component 400 is illustrated in FIG. 1, a larger number of electronic components 400 may be mounted.

As shown in FIG. 1, the circuit board 100 with a built-in semiconductor IC according to this embodiment has a semiconductor IC 300 embedded in an insulating layer 113. The semiconductor IC 300 is embedded so that the main surface on which the pad electrodes are provided faces the lower surface 101, and the back surface faces the upper surface 102. As will be described in detail later, a rewiring layer 321 connected to the pad electrodes is provided on the main surface of the semiconductor IC 300. The rewiring layer 321 includes rewiring patterns 321a and 321b. Although only one semiconductor IC 300 is shown in FIG. 1, two or more semiconductor ICs 300 may be embedded.

The conductor layer L1 includes wiring patterns 211 and 212. The portions of the wiring patterns 211 and 212 that are not covered by the solder resist 121 form the external terminals E1 and E2 of the circuit board 100 with a built-in semiconductor IC. Of these, the external terminal E1 is used as a terminal that provides a power supply potential (typically a ground potential) to the semiconductor IC 300. The circuit board 100 with a built-in semiconductor IC is provided with a plurality of external terminals E2, which are used as signal terminals, power supply terminals, or dummy terminals.

The conductor layer L2 includes wiring patterns 221 and 222. Of these, the wiring pattern 221 is connected to the wiring pattern 211 of the conductor layer L1 through a plurality of via conductors 251 provided to penetrate the insulating layer 114. Although only two via conductors 251 are illustrated in FIG. 1, a greater number of via conductors 251 can be provided in practice. As shown in FIG. 1, the wiring pattern 221 is in contact with the rewiring pattern 321a of the semiconductor IC 300 over a large area. Furthermore, the wiring pattern 222 is connected to the rewiring pattern 321b of the semiconductor IC 300, and is connected to the wiring pattern 212 of the conductor layer L1 through a via conductor 252 provided to penetrate the insulating layer 114.

The conductor layer L3 includes a wiring pattern 231. A portion of the wiring pattern 231 is connected to the wiring pattern 222 of the conductor layer L2 through a plurality of via conductors 253 that penetrate the insulating layers 112 and 113. The via conductors 253 are arranged at positions that do not overlap the semiconductor IC 300 in a plan view.

The conductor layer L4 includes wiring patterns 241 and 242. Of these, the wiring pattern 242 is connected to the wiring pattern 231 of the conductor layer L3 through a plurality of via conductors 254 that are provided penetrating the insulating layer 111. Furthermore, the portion of the wiring pattern 242 that is not covered with the solder resist 122 constitutes a land pattern L. The land pattern L is connected to the terminal electrode 401 of the electronic component 400 through the solder 402.

Figure 2 is a schematic cross-sectional view showing the state in which the circuit board 100 with built-in semiconductor IC according to this embodiment is mounted on the motherboard 10. As shown in Figure 2, the circuit board 100 with built-in semiconductor IC is mounted so that the bottom surface 101 faces the motherboard 10, and the land patterns 11 and 12 provided on the motherboard 10 and the external terminals E1 and E2 of the circuit board 100 with built-in semiconductor IC are connected via solder 20, respectively.

3 to 5 are detailed cross-sectional views of the via conductor connecting the conductor layer L2 and the conductor layer L3. The via 253a in which the via conductor 253 is embedded has a shape in which the diameter decreases in the depth direction, and the shape of the section S1 located on the conductor layer L2 side and the shape of the section S2 located on the conductor layer L3 side may be different from each other. In the example shown in FIG. 3, the angle of the inner wall of the via 253a is closer to perpendicular in the section S2 than in the section S1. In other words, the amount of reduction in the diameter per unit depth in the section S1 is greater than the amount of reduction in the diameter per unit depth in the section S2. If the via 253a is shaped in this way, the angle θ1 between the inner wall of the section S1 and the surface of the insulating layer 113 becomes larger, thereby improving the coverage of the conductor layer L2 at the edge portion of the via 253a, and as a result, the connection reliability of the via conductor 253 is improved.

In contrast, as shown by dashed line C, if the entire via 253a has the same shape as section S2, the angle θ2 at the edge portion of the via 253a becomes small, and the plating thickness of the conductor layer L2 in this portion may become thin, or a break may occur in this portion. Such problems can be solved by giving the via 253a the above-mentioned shape. Note that the shape shown in FIG. 3 is the shape obtained when the via 253a is formed from the conductor layer L2 side. If the via 253a is formed from the conductor layer L3 side, the vertical positions of sections S1 and S2 will be reversed from those in FIG. 3.

The shape of section S1 may be curved as shown in FIG. 4. In other words, the shape may be such that the amount of reduction in diameter per unit depth in section S1 increases as the depth position increases. This makes it possible to increase the volume of via 253a.

Also, if the via 253a is shaped as shown in FIG. 3 or FIG. 4, the distance between the semiconductor IC 300 and the via 253a can be shortened as shown in FIG. 5, which allows the planar size of the circuit board 100 with a built-in semiconductor IC to be reduced. In other words, as shown by the dashed line D, if the diameter at the upper end of the via 253a is fixed and the inner wall is made linear, the semiconductor IC 300 cannot be placed in the position shown in FIG. 5 and must be placed at a position farther away from the via 253a. However, if the via 253a is shaped as shown in FIG. 3 or FIG. 4, the semiconductor IC 300 can be placed closer to the via 253a. To achieve this effect, the thickness of the semiconductor IC 300 is reduced to less than the depth of section S2, and the depth position of the semiconductor IC 300 is set within the range of section S2.

Next, a method for manufacturing the semiconductor IC-embedded circuit board 100 according to this embodiment will be described.

Figures 6 to 17 are process diagrams illustrating the manufacturing method of the semiconductor IC-embedded circuit board 100 according to this embodiment.

First, as shown in FIG. 6, a substrate (work board) is prepared in which conductor layers L3 and L4 made of Cu foil or the like are laminated on both sides of an insulating layer 111 containing a core material such as glass fiber, i.e., a double-sided CCL (Copper Clad Laminate). The thickness of the core material contained in the insulating layer 111 is desirably 40 μm or more in order to ensure appropriate rigidity for easy handling. The material of the conductor layers L3 and L4 is not particularly limited, and in addition to the above-mentioned Cu, for example, metal conductive materials such as Au, Ag, Ni, Pd, Sn, Cr, Al, W, Fe, Ti, and SUS material can be mentioned. Among these, it is preferable to use Cu from the viewpoint of conductivity and cost. The same applies to the other conductor layers L1 and L2 described later.

In addition, the resin material used for the insulating layer 111 is not particularly limited as long as it can be molded into a sheet or film, and can be used. In addition to glass epoxy, for example, vinylbenzyl resin, polyvinylbenzyl ether compound resin, bismaleimide triazine resin (BT resin), polyphenylene ether (polyphenylene ether oxide) resin (PPE, PPO), cyanate ester resin, epoxy + active ester cured resin, polyphenylene ether resin (polyphenylene oxide resin), curable polyolefin resin, benzocyclobutene resin, polyimide resin, aromatic polyester resin, aromatic liquid crystal polyester resin, polyphenylene sulfide resin, polyetherimide resin, polyacrylate resin, polyether ether ketone resin, fluororesin, etc. Materials that can be used include fluorine resin, epoxy resin, phenol resin, or benzoxazine resin alone, or materials in which silica, talc, calcium carbonate, magnesium carbonate, aluminum hydroxide, magnesium hydroxide, aluminum borate whisker, potassium titanate fiber, alumina, glass flakes, glass fiber, tantalum nitride, aluminum nitride, or the like is added to these resins, and materials in which metal oxide powder containing at least one metal selected from magnesium, silicon, titanium, zinc, calcium, strontium, zirconium, tin, neodymium, samarium, aluminum, bismuth, lead, lanthanum, lithium, and tantalum is added to these resins, and can be appropriately selected and used from the viewpoints of electrical properties, mechanical properties, water absorption, reflow resistance, and the like. Furthermore, examples of the core material contained in the insulating layer 111 include materials that are blended with resin fibers such as glass fibers and aramid fibers. The same applies to the other insulating layers 112 to 114 described below.

7, the conductor layer L3 is patterned using a known method such as photolithography to form the wiring pattern 231. Furthermore, an uncured (B-stage) resin sheet or the like is laminated on the surface of the insulating layer 111 by vacuum pressure bonding or the like so as to embed the wiring pattern 231, thereby forming the insulating layer 112.

Next, as shown in FIG. 8, the semiconductor IC 300 is placed on the insulating layer 112. The semiconductor IC 300 is mounted in a face-up manner so that the main surface on which the rewiring patterns 321a and 321b are exposed faces upward. As described above, the semiconductor IC 300 may be thinned. Specifically, the thickness of the semiconductor IC 300 is, for example, 200 μm or less, more preferably about 50 to 100 μm. In this case, it is desirable to process a large number of semiconductor ICs 300 in a wafer state at once from the viewpoint of cost, and the processing order is grinding the back surface, and then dicing to separate the individual semiconductor ICs 300. As another method, when cutting and separating or half-cutting the individual semiconductor ICs 300 by dicing before thinning by polishing, the back surface of the semiconductor IC 300 can be polished with the main surface of the semiconductor IC 300 covered with a thermosetting resin or the like. Therefore, the order of insulating film grinding, electronic component back surface grinding, and dicing varies widely. Furthermore, methods for grinding the back surface of the semiconductor IC 300 include roughening methods such as etching, plasma treatment, laser treatment, blasting, polishing with a grinder, buffing, and chemical treatment. These methods not only make it possible to thin the semiconductor IC 300, but also to improve adhesion to the insulating layer 112.

Next, as shown in FIG. 9, an insulating layer 113 and a conductor layer L2 are formed to cover the semiconductor IC 300. The insulating layer 113 is preferably formed, for example, by applying an uncured or semi-cured thermosetting resin, then heating it to semi-cure it if it is uncured, and then hardening and molding it together with the conductor layer L2 using a press. The insulating layer 113 is preferably a resin sheet that does not contain fibers that would prevent the semiconductor IC 300 from being embedded. This improves the adhesion between the insulating layer 113 and the conductor layer L2, the insulating layer 112, and the semiconductor IC 300.

Next, as shown in FIG. 10, a portion of the conductor layer L2 is etched away using a known technique such as photolithography to form openings 261-263 that expose the insulating layer 113. Of these, opening 261 is formed at a position overlapping rewiring pattern 321a, opening 262 is formed at a position overlapping rewiring pattern 321b, and opening 263 is formed at a position not overlapping semiconductor IC 300 and overlapping wiring pattern 231 of conductor layer L3. Here, the diameter of opening 261 is smaller than the planar size of rewiring pattern 321a, so that the entire opening 261 overlaps rewiring pattern 321a in plan view. Similarly, the diameter of opening 262 is smaller than the planar size of rewiring pattern 321b, so that the entire opening 262 overlaps rewiring pattern 321b in plan view.

Next, as shown in FIG. 11, a via C is formed in the insulating layers 112 and 113 by performing laser processing on the center portion of the opening 263. The via C corresponds to the dashed line C shown in FIG. 3. In other words, the entire via C has the same shape as section S2. Here, the laser light is not irradiated to the entire opening 263, but only to the center portion of the opening 263, leaving a ring-shaped unprocessed region. Furthermore, the openings 261 and 262 are also laser processed to form openings 113a and 113b in the insulating layer 113. Rewiring patterns 321a and 321b are exposed from the openings 113a and 113b, respectively.

Next, as shown in FIG. 12, blasting is performed on the entire surface using the conductor layer L2 as a mask to remove the insulating layer 113 from the portion not covered by the conductor layer L2. As a result, at the position corresponding to the opening 263 of the conductor layer L2, the diameter of the upper portion of the via C is enlarged by the blasting, and a via 253a having sections S1 and S2 as shown in FIG. 3 is formed. In this way, by performing laser processing and then further blasting, the via 253a can be made to have a shape having sections S1 and S2 as shown in FIG. 3. Therefore, the shape of section S1 is mainly due to the blasting, and the shape of section S2 is mainly due to the laser processing.

Next, as shown in FIG. 13, electroless plating and electrolytic plating are performed to form via conductors 253 and to form wiring patterns 221 and 222 that contact rewiring patterns 321a and 321b.

Next, as shown in FIG. 14, the wiring patterns 221 and 222 are separated by patterning them using a known method. After that, the sheet in which the insulating layer 114 and the conductor layer L1 are laminated is vacuum hot pressed so that the conductor layer L2 is embedded. The material and thickness used for the insulating layer 114 may be the same as those of the insulating layer 111.

Next, as shown in FIG. 15, a portion of the conductor layer L1 is etched away using a known technique such as photolithography to form openings 271 and 272 that expose the insulating layer 114. Of these, a plurality of openings 271 are formed at positions overlapping the wiring pattern 221, and openings 272 are formed at positions overlapping the wiring pattern 222. Since the wiring pattern 221 is provided at a position overlapping the semiconductor IC 300, the openings 271 are also provided at a position overlapping the semiconductor IC 300. In the example shown in FIG. 15, the openings 272 are provided at positions that do not overlap the semiconductor IC 300, but some of the openings 272 may be provided at positions that overlap the semiconductor IC 300.

Next, as shown in FIG. 16, the openings 271 and 272 are subjected to known laser processing or blast processing to remove the insulating layer 114 from the portions not covered by the conductor layer L1. As a result, an opening 114a is formed in the insulating layer 114 at a position corresponding to the opening 271 in the conductor layer L1, exposing the wiring pattern 221. Similarly, an opening 114b is formed in the insulating layer 114 at a position corresponding to the opening 272 in the conductor layer L1, exposing the wiring pattern 222.

Next, as shown in FIG. 17, via conductors 251, 252 are formed inside openings 114a, 114b by electroless plating and electrolytic plating, respectively. After that, conductor layers L1, L4 are patterned using a known method such as photolithography, to form wiring patterns 211, 212 on conductor layer L1 and wiring patterns 241, 242 on conductor layer L4, as shown in FIG. 1. Then, solder resists 121, 122 are formed at predetermined planar positions, and electronic components 400 are mounted and molded resin 130 is formed, completing the semiconductor IC-embedded circuit board 100 according to this embodiment.

In this manner, in this embodiment, the structure that contributes to heat dissipation, that is, the heat dissipation structure that connects the rewiring pattern 321a and the wiring pattern 211, is not formed by a separate process, but can be formed simultaneously with the process for obtaining the structure that connects the signal or power rewiring pattern 321b and the wiring pattern 222, making it possible to manufacture the circuit board 100 with the built-in semiconductor IC in fewer steps. Furthermore, in forming the via 253a that connects the conductor layer L2 and the conductor layer L3, two-stage processing, laser processing and blast processing, is performed, so that the via 253a can be formed into the shape shown in FIG. 3, which makes it possible to improve the connection reliability of the via conductor 253 formed inside the via 253a.

Second Embodiment
FIG. 18 is a schematic cross-sectional view illustrating the structure of a circuit board 200 with built-in thin film capacitors according to a second embodiment of the present invention.

18, the thin-film capacitor-embedded circuit board 200 according to this embodiment differs from the semiconductor IC-embedded circuit board 100 according to the first embodiment in that a thin-film capacitor 500 is embedded instead of the semiconductor IC 300, and a semiconductor IC 600 is mounted instead of the electronic component 400. The thin-film capacitor 500 has a pair of terminal electrodes 501, 502, of which the terminal electrode 501 is connected to the wiring pattern 223 via the via conductor 255, and the terminal electrode 502 is connected to the wiring pattern 224 via the via conductor 256. The semiconductor IC 600 also has a plurality of pad electrodes 601 to 605. The pad electrodes 601 to 605 are connected to the wiring pattern 243 of the conductor layer L4 via the solder 606. As an example, the pad electrodes 601, 605 are each given a power supply potential and a ground potential. The pad electrode 601 is connected to the terminal electrode 501 of the thin-film capacitor 500 via the wiring pattern 223, and the pad electrode 602 is connected to the terminal electrode 502 of the thin-film capacitor 500 via the wiring pattern 224. This causes the thin-film capacitor 500 to function as a decoupling capacitor for the semiconductor IC 600.

In this embodiment, not only the via in which the via conductor 253 is embedded, but also the via in which the via conductors 255, 256 are embedded have a shape consisting of sections S1 and S2 as shown in Figures 3 and 4. In other words, the via in which the via conductors 255, 256 are embedded has a section S1 in which the amount of reduction in diameter per unit depth is large, and a section S2 in which the amount of reduction in diameter per unit depth is small. This improves the coverage of the via conductors 255, 256, thereby achieving high connection reliability.

Next, a method for manufacturing the thin-film capacitor-embedded circuit board 200 according to this embodiment will be described.

First, after carrying out the steps described with reference to Figures 6 to 9, as shown in Figure 19, a portion of the conductor layer L2 is etched away using a known technique such as photolithography to form openings 263 to 265 that expose the insulating layer 113. Of these, opening 263 is formed at a position that does not overlap the thin-film capacitor 500 and overlaps the wiring pattern 231 of the conductor layer L3, and openings 264 and 265 are formed at positions that overlap the terminal electrodes 501 and 502 of the thin-film capacitor 500, respectively.

Next, as shown in FIG. 20, via C is formed in insulating layers 112 and 113 by performing laser processing on the center portion of opening 263. Furthermore, via C is formed in insulating layer 113 by performing laser processing on the center portions of openings 264 and 265. Via C corresponds to dashed line C shown in FIG. 3. In other words, the entire via C has the same shape as section S2. Here, the laser light is not irradiated to the entire openings 263-265, but only to the center portions of openings 263-265, leaving a ring-shaped unprocessed region.

Next, as shown in FIG. 21, blasting is performed overall using the conductor layer L2 as a mask to remove the insulating layer 113 from the portion not covered by the conductor layer L2. As a result, in the positions corresponding to the openings 263-265 of the conductor layer L2, the diameter of the upper portion of the via C is enlarged by the blasting, and the vias 253a, 255a, 256a having the sections S1 and S2 shown in FIG. 3 are formed. In this way, the vias 253a, 255a, 256a can be made to have the shapes having the sections S1 and S2 shown in FIG. 3 by further performing blasting after the laser processing. Therefore, the shape of section S1 is mainly due to the blasting, and the shape of section S2 is mainly due to the laser processing.

Next, as shown in FIG. 22, via conductors 253, 255, and 256 are formed by performing electroless plating and electrolytic plating.

Then, the process described with reference to Figures 14 to 17 is carried out, and finally, the semiconductor IC 600 is mounted to complete the thin-film capacitor-embedded circuit board 200 according to this embodiment.

As exemplified in this embodiment, a plurality of vias having different depths may have a shape consisting of sections S1 and S2. In addition, a via having a shape consisting of sections S1 and S2 does not need to connect two conductor layers (e.g., conductor layer L2 and conductor layer L3), but may connect a conductor layer (e.g., conductor layer L2) and a terminal electrode (e.g., terminal electrodes 501 and 502) of an electronic component embedded in a circuit board. Furthermore, in this embodiment, an example is shown in which a two-terminal thin film capacitor 500 is embedded in a circuit board, but even when an electronic component or semiconductor IC with more terminals is embedded, the via that exposes the terminal electrodes of these electronic components or semiconductor ICs may have a shape consisting of sections S1 and S2, as in this embodiment. Even in this case, the same effect as in this embodiment can be expected.

Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications are possible without departing from the spirit of the present invention, and it goes without saying that these are also included within the scope of the present invention.

10 Motherboard 11, 12 Land pattern 20 Solder 100 Circuit board with built-in semiconductor IC 101 Lower surface of circuit board with built-in semiconductor IC 102 Upper surface of circuit board with built-in semiconductor IC 111 to 114 Insulating layers 113a, 113b, 114a, 114b, 261 to 265, 271, 272 Openings 121, 122 Solder resist 130 Molding resin 200 Circuit board with built-in thin film capacitor 211, 212, 221 to 224, 231, 241 to 243 Wiring patterns 251 to 256 Via conductors 253a, 255a, 256a Vias 300 Semiconductor IC
321 Rewiring layer 321a, 321b Rewiring pattern 322 Protective film 400 Electronic component 401 Terminal electrode 402 Solder 500 Thin film capacitor 501, 502 Terminal electrode 600 Semiconductor IC
601 to 605 Pad electrode 602 Pad electrode 606 Solder C Via E1, E2 External terminal L Land patterns L1 to L4 Conductive layers S1, S2 Section

Claims (2)

First and second conductor layers;
an insulating layer located between the first conductor layer and the second conductor layer;
a via conductor formed inside a via provided to penetrate the insulating layer and connecting the first conductor layer and the second conductor layer;
a semiconductor IC embedded in the insulating layer;
the via has a shape in which a diameter decreases in a depth direction from the first conductor layer side to the second conductor layer side,
the via includes a first section located on the first conductor layer side and a second section located on the second conductor layer side;
a reduction in diameter per unit depth in the first section is greater than a reduction in diameter per unit depth in the second section;
a thickness of the semiconductor IC is less than a depth of the second section, and a depth position of the semiconductor IC is within the range of the second section;
The circuit board , wherein the semiconductor IC overlaps with the first section when viewed in the depth direction . The circuit board according to claim 1, characterized in that the first section has a shape in which the amount of reduction in diameter per unit depth increases as the depth position increases.

Images