JP7272046B2 - Electronic component built-in circuit board and its manufacturing method - Google Patents

Description

The present invention relates to a circuit board with built-in electronic components and a method of manufacturing the same, and more particularly to a circuit board with built-in electronic components having a multi-layer wiring structure and a method of manufacturing the same.

A circuit board described in Patent Document 1 is known as a circuit board in which an electronic component such as a semiconductor IC is embedded. In the circuit board described in Patent Document 1, an electronic component is mounted face-up on the surface of a first insulating layer, and a second insulating layer is formed on the surface of the first insulating layer so as to cover the main surface of the electronic component. It forms an insulating layer. A wiring pattern is formed on the surface of the second insulating layer.

Japanese Unexamined Patent Application Publication No. 2007-150002

However, since the thickness of the second insulating layer on the main surface of the electronic component is very thin, when inspecting the shape of the wiring pattern formed on the surface of the second insulating layer by image recognition, the second insulating layer The rewiring layer formed on the main surface of the electronic component can be seen through the layer. For this reason, interference occurs between the wiring pattern and the rewiring layer in the photographed image, and there is a problem that the image recognition accuracy is lowered when inspecting the shape of the wiring pattern.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to reduce interference between a wiring pattern and a rewiring layer in a photographed image when inspecting the shape of the wiring pattern by image recognition.

A circuit board with built-in electronic components according to the present invention has a first insulating layer, a main surface provided with a rewiring layer, and a back surface located on the opposite side of the main surface, and the back surface is covered with the first insulating layer. the electronic component mounted on the surface of the first insulating layer, the second insulating layer provided on the surface of the first insulating layer and covering the main surface of the electronic component, and the surface of the second insulating layer and a first conductor layer at least partially overlapping the rewiring layer, wherein the second insulating layer has a lower light transmittance than the first insulating layer.

A method of manufacturing a circuit board with a built-in electronic component according to the present invention prepares an electronic component having a main surface provided with a rewiring layer and a back surface located on the opposite side of the main surface, and the back surface is covered with a first insulating layer. a step of mounting an electronic component on the surface of a first insulating layer; a step of providing a second insulating layer covering the main surface of the electronic component on the surface of the first insulating layer; forming a conductor layer at least partially overlapping the rewiring layer on the surface; and inspecting the shape of the conductor layer by image recognition, wherein the second insulating layer transmits more light than the first insulating layer. Characterized by a low rate.

According to the present invention, since the light transmittance of the second insulating layer is low, when the shape of the first conductor layer is inspected by image recognition, it is difficult to see through the rewiring layer provided on the electronic component. . Therefore, it is possible to improve the accuracy of image recognition when inspecting the shape of the first conductor layer.

In the present invention, the second insulating layer may be colored with pigment, dye or carbon black. According to this, it becomes possible to greatly reduce the light transmittance of the second insulating layer.

The electronic component built-in circuit board according to the present invention further comprises third and fourth insulating layers sandwiching the first and second insulating layers, and the third and fourth insulating layers are formed by impregnating a core material with a resin material. The first and second insulating layers may be resin layers that do not contain a core material. According to this, it is possible to increase the mechanical strength of the electronic component built-in circuit board.

The electronic component built-in circuit board according to the present invention further comprises a second conductor layer provided between the first insulating layer and the third insulating layer and having an opening for exposing the surface of the third insulating layer, The third insulating layer may have a lower light reflectance than the fourth insulating layer. According to this, when the opening provided in the second conductor layer is used as the alignment mark, it is possible to obtain high contrast because the third insulating layer, which is the base of the alignment mark, has a low light reflectance. becomes.

As described above, according to the present invention, when the shape of the first conductor layer is inspected by image recognition, the rewiring layer provided on the electronic component is difficult to see through, so that the image recognition accuracy can be improved. It becomes possible.

FIG. 1 is a schematic cross-sectional view for explaining the structure of an electronic component built-in circuit board 100 according to a first embodiment of the present invention. FIG. 2 is a schematic plan view showing an example of the pattern shape of the rewiring layer 133. As shown in FIG. FIG. 3 is a process diagram for explaining the method of manufacturing the circuit board 100 with built-in electronic components. FIG. 4 is a process diagram for explaining the method of manufacturing the electronic component built-in circuit board 100. As shown in FIG. FIG. 5 is a process diagram for explaining the method of manufacturing the circuit board 100 with built-in electronic components. FIG. 6 is a process diagram for explaining the method of manufacturing the electronic component built-in circuit board 100. As shown in FIG. FIG. 7 is a process diagram for explaining the method of manufacturing the electronic component built-in circuit board 100. As shown in FIG. FIG. 8 is a process diagram for explaining the method of manufacturing the circuit board 100 with built-in electronic components. FIG. 9 is a process diagram for explaining the method of manufacturing the electronic component built-in circuit board 100. As shown in FIG. 10A to 10D are process diagrams for explaining a method of manufacturing the electronic component built-in circuit board 100. FIG. 11A to 11D are process diagrams for explaining the method of manufacturing the electronic component built-in circuit board 100. FIG. FIG. 12 is a process diagram for explaining the method of manufacturing the electronic component built-in circuit board 100. As shown in FIG. 13A to 13D are process diagrams for explaining the method of manufacturing the electronic component built-in circuit board 100. FIG. 14A to 14D are process diagrams for explaining the method of manufacturing the electronic component built-in circuit board 100. FIG. 15A and 15B are process diagrams for explaining a method of manufacturing the electronic component built-in circuit board 100. FIG. 16A to 16D are process diagrams for explaining the method of manufacturing the electronic component built-in circuit board 100. FIG. FIG. 17 is a schematic cross-sectional view for explaining the structure of the electronic component built-in circuit board 200 according to the second embodiment of the present invention.

Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional view for explaining the structure of an electronic component built-in circuit board 100 according to a first embodiment of the present invention.

As shown in FIG. 1, the electronic component built-in circuit board 100 according to the first embodiment has four insulating layers 111 to 114 and conductor layers L1 to L4 located on the respective surfaces of the insulating layers 111 to 114. ing. Although not particularly limited, the insulating layer 111 located at the bottom layer and the insulating layer 114 located at the top layer may be a core layer in which a core material such as glass fiber is impregnated with a resin material such as epoxy. I do not care. On the other hand, the insulating layers 112 and 113 may be resin layers that do not contain a core material such as glass cloth. In particular, the coefficient of thermal expansion of insulating layers 111 and 114 is preferably smaller than the coefficient of thermal expansion of insulating layers 112 and 113 . In this way, with a structure in which the insulating layers 112 and 113, which are resin layers, are sandwiched between the insulating layers 111 and 114, which are core layers, sufficient mechanical strength can be obtained even when the electronic component built-in circuit board 100 is thin. Strength can be obtained.

In this embodiment, the insulating layer 113 is colored with pigment, dye or carbon black. In contrast, the other insulating layers 111, 112, and 114 are not colored as such. Therefore, the insulating layer 113 is opaque and has a lower light transmittance than the other insulating layers 111 , 112 and 114 . Thus, the insulating layer 112 and the insulating layer 113 that constitute the resin layer have different optical characteristics. On the other hand, the insulating layer 111 and the insulating layer 114 forming the core layer may have the same optical characteristics.

The uppermost insulating layer 114 and part of the conductor layer L1 formed thereon are covered with a solder resist 121 . Similarly, the lowermost insulating layer 111 and part of the conductor layer L4 formed thereon are covered with a solder resist 122 . Solder resist 121 constitutes upper surface 101 of circuit board 100 with a built-in electronic component, and solder resist 122 constitutes lower surface 102 of circuit board 100 with a built-in electronic component, although they are not particularly limited. Although not shown, electronic components such as capacitors and inductors can be mounted on the upper surface 101 of the electronic component built-in circuit board 100 . The bottom surface 102 may be formed with user terminals that are connected to the motherboard. Alternatively, the electronic component built-in circuit board 100 may be turned upside down and the electronic component may be mounted on the lower surface 102 .

As shown in FIG. 1, an electronic component built-in circuit board 100 according to this embodiment has an electronic component 130 embedded in an insulating layer 113 . The electronic component 130 is, for example, a semiconductor IC. ing. FIG. 2 is a schematic plan view showing an example of the pattern shape of the rewiring layer 133. As shown in FIG. As shown in FIG. 2, the rewiring layer 133 is connected to the electrode pads P provided on the electronic component 130 and serves to increase the electrode pitch and electrode area. Although only one electronic component 130 is shown in FIG. 1, two or more electronic components 130 may be embedded.

The conductor layer L1 includes wiring patterns 141 . A portion of the wiring pattern 141 that is not covered with the solder resist 121 constitutes an external terminal of the electronic component built-in circuit board 100 .

The conductor layer L2 includes wiring patterns 142 . A portion of the wiring pattern 142 is connected to the wiring pattern 141 of the conductor layer L1 through a plurality of via conductors 151 provided through the insulating layer 114 . Another part of wiring pattern 142 is connected to rewiring layer 133 of electronic component 130 via via conductor 152 provided at a position overlapping electronic component 130 in plan view.

The conductor layer L3 includes wiring patterns 143 . A portion of the wiring pattern 143 is connected to the wiring pattern 142 of the conductor layer L2 through a plurality of via conductors 153 provided through the insulating layers 112,113. Via conductor 153 is arranged at a position not overlapping electronic component 130 in plan view.

The conductor layer L4 includes wiring patterns 144 . A portion of the wiring pattern 144 is connected to the wiring pattern 143 of the conductor layer L3 through a plurality of via conductors 154 provided through the insulating layer 111 . A portion of the wiring pattern 144 that is not covered with the solder resist 122 constitutes a terminal electrode.

Next, a method for manufacturing the electronic component built-in circuit board 100 according to this embodiment will be described.

3 to 16 are process diagrams for explaining the method of manufacturing the electronic component built-in circuit board 100 according to this embodiment.

First, as shown in FIG. 3, a base material (work board) in which conductor layers L3 and L4 made of conductor foil such as Cu are laminated on both sides of an insulating layer 111 containing a core material such as glass fiber, that is, both sides Prepare CCL (Copper Clad Laminate). The thickness of the core material included in the insulating layer 111 is desirably 40 μm or more in order to ensure appropriate rigidity for facilitating handling. In addition, the material of the conductor layers L3 and L4 is not particularly limited, and in addition to Cu described above, for example, metal conductive materials such as Au, Ag, Ni, Pd, Sn, Cr, Al, W, Fe, Ti, SUS materials, etc. Among these materials, it is preferable to use Cu from the viewpoint of electrical conductivity and cost. The same applies to other conductor layers L1 and L2, which will be described later. In addition, the surface L3a of the conductor layer L3 is preferably roughened in order to improve adhesion to the insulating layer 112. As shown in FIG. When the surface L3a of the conductor layer L3 is roughened, the light irradiated to the conductor layer L3 is scattered, so even if it is made of a metal material such as Cu, it looks slightly black.

The resin material used for the insulating layer 111 is not particularly limited as long as it can be molded into a sheet or film. Bismaleimide triazine resin (BT resin), polyphenylene ether (polyphenylene ether oxide) resin (PPE, PPO), cyanate ester resin, epoxy + active ester curing resin, polyphenylene ether resin (polyphenylene oxalate resin), curable polyolefin resin, Benzocyclobutene resin, polyimide resin, aromatic polyester resin, aromatic liquid crystal polyester resin, polyphenylene sulfide resin, polyetherimide resin, polyacrylate resin, polyetheretherketone resin, fluorine resin, epoxy resin, phenolic resin, or benzoxazine Resin alone, or these resins containing silica, talc, calcium carbonate, magnesium carbonate, aluminum hydroxide, magnesium hydroxide, aluminum borate whisker, potassium titanate fiber, alumina, glass flakes, glass fiber, tantalum nitride, Materials obtained by adding aluminum nitride or the like, and at least one of magnesium, silicon, titanium, zinc, calcium, strontium, zirconium, tin, neodymium, samarium, aluminum, bismuth, lead, lanthanum, lithium and tantalum to these resins. A material to which a metal oxide powder containing a seed metal is added can be used, and can be appropriately selected and used from the viewpoint of electrical properties, mechanical properties, water absorption, reflow resistance, and the like. Furthermore, examples of the core material included in the insulating layer 111 include materials in which resin fibers such as glass fibers and aramid fibers are blended. The same applies to other insulating layers 112 to 114, which will be described later.

Next, as shown in FIG. 4, a wiring pattern 143 is formed by patterning the conductor layer L3 using a known technique such as photolithography. At this time, an opening A that functions as an alignment mark is formed in the conductor layer L3 at a position that does not overlap the area where the electronic component 130 is mounted. The opening A exposes the underlying insulating layer 111, and functions as an alignment mark due to the difference in contrast between the conductor layer L3 and the insulating layer 111. FIG.

Next, as shown in FIG. 5, an insulating layer 112 is formed by laminating, for example, an uncured (B-stage state) resin sheet or the like on the surface of the insulating layer 111 by vacuum pressure bonding or the like so as to embed the conductor layer L3. do. The insulating layer 112 is not colored and has high transparency.

Next, as shown in FIG. 6, electronic component 130 is placed on insulating layer 112 . Electronic component 130 is mounted face-up so that main surface 131 faces upward. When the electronic component 130 is a semiconductor IC, the thickness of the silicon substrate may be reduced to, for example, 200 μm or less, more preferably about 50 to 100 μm. When the electronic component 130 is mounted, the positioning of the electronic component 130 is performed by recognizing the image of the alignment mark formed by the opening A. FIG.

Next, as shown in FIG. 7, an insulating layer 113 colored with a pigment, a dye or carbon black and a conductor layer L2 are formed to cover the electronic component 130. Then, as shown in FIG. The insulating layer 113 is formed, for example, by applying an uncured or semi-cured thermosetting resin, heating it to semi-cur it in the case of an uncured resin, and further using a pressing means to form the resin together with the conductor layer L2. Curing molding is preferred. The insulating layer 113 is desirably a resin sheet that does not contain fibers that interfere with the embedding of the electronic component 130 . Thereby, the adhesion between the insulating layer 113 and the conductor layer L2, the insulating layer 112 and the electronic component 130 is improved.

Next, as shown in FIG. 8, openings 162 and 163 that expose the insulating layer 113 are formed by removing part of the conductor layer L2 by etching using a known technique such as photolithography. Of these, the opening 162 is formed at a position overlapping the rewiring layer 133 of the electronic component 130, and the opening 163 is formed at a position not overlapping the electronic component 130 but overlapping the wiring pattern 143 of the conductor layer L3. .

Next, as shown in FIG. 9, the insulating layers 113 and 112 in the portions not covered with the conductor layer L2 are removed by laser processing or blast processing using the conductor layer L2 as a mask. As a result, a via 152a is formed in the insulating layer 113 at a position corresponding to the opening 162 of the conductor layer L2, and the rewiring layer 133 of the electronic component 130 is exposed. Similarly, vias 153a are formed in the insulating layers 113 and 112 at positions corresponding to the openings 163 of the conductor layer L2, and the wiring pattern 143 of the conductor layer L3 is exposed.

Next, as shown in FIG. 10, via conductors 152 and 153 are formed on the inner walls of vias 152a and 153a by applying electroless plating and electrolytic plating. Thereby, the rewiring layer 133 of the electronic component 130 and the wiring pattern 143 of the conductor layer L3 are connected to the conductor layer L2 through the via conductors 152 and 153 .

Next, as shown in FIG. 11, a wiring pattern 142 is formed by patterning the conductor layer L2 by a known technique such as photolithography. A portion of the wiring pattern 142 overlaps the rewiring layer 133 of the electronic component 130 in plan view. After that, the shape of the wiring pattern 142 is inspected by image recognition. In the present embodiment, the insulating layer 113 is colored with a pigment, dye, or carbon black to reduce the light transmittance. The rewiring layer 133 of the electronic component 130 is less likely to be seen through, and interference between the wiring pattern 142 and the rewiring layer 133 is less likely to occur in the captured image. This makes it possible to improve the accuracy of image recognition when inspecting the shape of the wiring pattern 142 .

Next, as shown in FIG. 12, the sheet in which the insulating layer 114 and the conductor layer L1 are laminated is vacuum hot pressed so as to embed the conductor layer L2. The thickness of the insulating layer 114 may be the same as that of the insulating layer 111 .

Next, as shown in FIG. 13, a portion of the conductor layers L1 and L4 is removed by etching using a known technique such as photolithography, thereby forming an opening 161 that exposes the insulating layer 114 in the conductor layer L1. is formed to form an opening 164 exposing the insulating layer 111 in the conductor layer L4. Among them, the opening 161 is formed at a position overlapping with the wiring pattern 142 , and the opening 164 is formed at a position overlapping with the wiring pattern 143 .

Next, as shown in FIG. 14, laser processing or blast processing is performed using the conductor layers L1 and L4 as a mask to remove the insulating layer 114 in the portions not covered with the conductor layer L1, and the conductor layer L4. The insulating layer 111 is removed in the uncovered portions. As a result, a via 151a is formed in the insulating layer 114 at a position corresponding to the opening 161 of the conductor layer L1, and the wiring pattern 142 of the conductor layer L2 is exposed. A via 154a is formed in the insulating layer 111 at a position corresponding to the opening 164 of the conductor layer L4, and the wiring pattern 143 of the conductor layer L3 is exposed.

Next, as shown in FIG. 15, via conductors 151 and 154 are formed on the inner walls of vias 151a and 154a by applying electroless plating and electrolytic plating. As a result, the wiring pattern 142 of the conductor layer L2 is connected to the conductor layer L1 through the via conductors 151 . In addition, the wiring pattern 143 of the conductor layer L3 is connected to the conductor layer L4 through the via conductors 154 .

Next, as shown in FIG. 16, the conductor layers L1 and L4 are patterned by a known technique such as photolithography to form a wiring pattern 141 on the conductor layer L1 and a wiring pattern 144 on the conductor layer L4. . Then, by forming the solder resists 121 and 122 at predetermined planar positions, the electronic component built-in circuit board 100 according to the present embodiment is completed.

As described above, in the present embodiment, the insulating layer 113 is colored with pigment, dye, or carbon black to reduce the light transmittance. Therefore, when inspecting the shape of the wiring pattern 142 by image recognition, The rewiring layer 133 of the electronic component 130 is less visible through the insulating layer 113 . This makes it possible to improve the accuracy of image recognition when inspecting the shape of the wiring pattern 142 . Further, since the insulating layer 112 has a high light transmittance, it is possible to easily recognize the image of the alignment mark formed by the opening A when the electronic component 130 is mounted.

FIG. 17 is a schematic cross-sectional view for explaining the structure of the electronic component built-in circuit board 200 according to the second embodiment of the present invention.

As shown in FIG. 17, in the electronic component built-in circuit board 200 according to the second embodiment, instead of the insulating layer 111, an insulating layer 111A colored with pigment, dye or carbon black is used. It is different from the electronic component built-in circuit board 100 according to the first embodiment. Since other points are the same as the electronic component built-in circuit board 100 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.

In this embodiment, the insulating layer 111A is colored with pigment, dye or carbon black. In contrast, the insulating layers 112 and 114 are not colored as such. Therefore, the insulating layer 111A is opaque and has a lower light reflectance and transmittance than the insulating layers 112 and 114 . Thus, in the present embodiment, the optical properties of the insulating layer 111A and the insulating layer 114 that constitute the core layer are also different from each other.

As described above, when the surface L3a of the conductor layer L3 is roughened, the conductor layer L3 looks blackish, and the contrast of the alignment mark formed by the opening A may be insufficient. In particular, when the alignment mark formed by the opening A is covered with the insulating layer 112, its contrast is greatly reduced. However, in this embodiment, since the insulating layer 111A is colored, sufficient contrast is ensured even when covered with the insulating layer 112. FIG.

As described above, since the insulating layer 111A is colored in this embodiment, the contrast of the alignment mark is sufficiently ensured. Therefore, it is possible to control the mounting position of the electronic component 130 with very high accuracy. The insulating layer 114 may also be colored by adding a pigment, dye, or carbon black. To avoid this, it is preferable not to color the insulating layer 114 .

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. Needless to say, it is included within the scope.

For example, in the above embodiments, the insulating layer 113 is colored with a pigment, dye, or carbon black, but the method of reducing the light transmittance of the insulating layer 113 is not limited to this.

100, 200 electronic component built-in circuit board 101 electronic component built-in circuit board top surface 102 electronic component built-in circuit board bottom surfaces 111 to 114, 111A insulating layers 121, 122 solder resist 130 electronic component 131 electronic component main surface 132 electronic component back surface 133 rewiring layers 141-144 wiring patterns 151-154 via conductors 151a-154a vias 161-164 opening A openings L1-L4 conductor layer L3a conductor layer surface P electrode pad

Claims (5)

a first insulating layer;
It has a main surface provided with a rewiring layer and a back surface located on the opposite side of the main surface, and is mounted on the surface of the first insulating layer so that the back surface is covered with the first insulating layer. electronic components;
a second insulating layer provided on the surface of the first insulating layer and covering the main surface of the electronic component;
a first conductor layer provided on the surface of the second insulating layer and at least partially overlapping with the rewiring layer;
a third insulating layer covering the first insulating layer from the side opposite to the second insulating layer;
a second conductor layer provided between the first insulating layer and the third insulating layer and having an opening that exposes the surface of the third insulating layer;
The electronic component is positioned with respect to the opening,
The electronic component built-in circuit board, wherein the second insulating layer has a lower light transmittance than the first insulating layer. 2. The circuit board with built-in electronic parts according to claim 1, wherein said second insulating layer is colored with pigment, dye or carbon black. further comprising a fourth insulating layer covering the second insulating layer from a side opposite to the first insulating layer;
The third and fourth insulating layers are core layers obtained by impregnating a core material with a resin material,
3. The electronic component built-in circuit board according to claim 1, wherein the first and second insulating layers are resin layers that do not contain a core material. 4. The electronic component built-in circuit board according to claim 3, wherein the third insulating layer has lower light transmittance and reflectance than the fourth insulating layer. forming an opening in a second conductor layer provided on the surface of a third insulating layer to expose the third insulating layer;
covering the surface of the third insulating layer with a first insulating layer such that the second conductor layer is embedded;
By preparing an electronic component having a main surface provided with a rewiring layer and a back surface located on the opposite side of the main surface, and performing image recognition of the opening so that the back surface is covered with a first insulating layer. mounting an electronic component on the surface of the first insulating layer while positioning;
providing a second insulating layer covering the main surface of the electronic component on the surface of the first insulating layer;
forming a first conductor layer at least partially overlapping with the rewiring layer on the surface of the second insulating layer;
inspecting the shape of the first conductor layer by image recognition;
A method of manufacturing an electronic component built-in circuit board, wherein the second insulating layer has a lower light transmittance than the first insulating layer.

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