JP7435043B2 - Circuit board with built-in electronic components and its manufacturing method - Google Patents

Circuit board with built-in electronic components and its manufacturing method Download PDF

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JP7435043B2
JP7435043B2 JP2020038547A JP2020038547A JP7435043B2 JP 7435043 B2 JP7435043 B2 JP 7435043B2 JP 2020038547 A JP2020038547 A JP 2020038547A JP 2020038547 A JP2020038547 A JP 2020038547A JP 7435043 B2 JP7435043 B2 JP 7435043B2
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insulating layer
electronic component
cavity
wiring pattern
built
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JP2021141226A (en
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和俊 露谷
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TDK Corp
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TDK Corp
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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Description

本発明は電子部品内蔵回路基板及びその製造方法に関し、特に、厚みの異なる複数の電子部品を内蔵可能な電子部品内蔵回路基板及びその製造方法に関する。 The present invention relates to a circuit board with a built-in electronic component and a method of manufacturing the same, and more particularly to a circuit board with a built-in electronic component that can embed a plurality of electronic components having different thicknesses, and a method of manufacturing the same.

半導体ＩＣなどの電子部品が埋め込まれた回路基板としては、特許文献１に記載された回路基板が知られている。特許文献１に記載された回路基板は、研磨などにより薄型化された半導体ＩＣが絶縁層に埋め込まれた構造を有している。 As a circuit board in which electronic components such as semiconductor ICs are embedded, a circuit board described in Patent Document 1 is known. The circuit board described in Patent Document 1 has a structure in which a semiconductor IC whose thickness has been reduced by polishing or the like is embedded in an insulating layer.

特開２００７－１５０００２号公報Japanese Patent Application Publication No. 2007-150002

しかしながら、厚みの異なる複数の電子部品を同じ絶縁層に内蔵すると、絶縁層の厚みを大きくする必要があることから、電子部品内蔵回路基板の全体の厚みが大幅に増加するという問題があった。 However, when a plurality of electronic components having different thicknesses are built into the same insulating layer, the thickness of the insulating layer needs to be increased, resulting in a problem in that the overall thickness of the electronic component built-in circuit board increases significantly.

したがって、本発明は、厚みの異なる複数の電子部品を内蔵可能な電子部品内蔵回路基板及びその製造方法において、基板全体の厚みの大幅を抑えることを目的とする。 Therefore, an object of the present invention is to significantly reduce the thickness of the entire board in a circuit board with a built-in electronic component capable of incorporating a plurality of electronic components having different thicknesses, and a method for manufacturing the same.

本発明による電子部品内蔵回路基板は、第１の絶縁層と、第１の絶縁層に埋め込まれた第１の電子部品と、第１の絶縁層の一方の表面に設けられた第１の配線パターンと、第１の絶縁層の他方の表面を覆う第２の絶縁層と、第２の絶縁層の第１の絶縁層とは反対側の表面に設けられた第２の配線パターンとを備え、第１及び第２の絶縁層はキャビティを有し、キャビティの底面に第１の配線パターンが露出しており、第２の配線パターンは、キャビティの開口部の周囲において第２の絶縁層が露出しないよう、キャビティの開口部を取り囲むように設けられていることを特徴とする。 A circuit board with a built-in electronic component according to the present invention includes a first insulating layer, a first electronic component embedded in the first insulating layer, and a first wiring provided on one surface of the first insulating layer. a second insulating layer covering the other surface of the first insulating layer; and a second wiring pattern provided on a surface of the second insulating layer opposite to the first insulating layer. , the first and second insulating layers have a cavity, the first wiring pattern is exposed at the bottom of the cavity, and the second wiring pattern has a second insulating layer around the opening of the cavity. It is characterized by being provided so as to surround the opening of the cavity so as not to be exposed.

本発明によれば、第１及び第２の絶縁層にキャビティが設けられていることから、別の電子部品をキャビティに収容することができる。これにより、別の電子部品が第１の電子部品よりも厚い場合であっても、全体の厚みの増加を抑えることが可能となる。また、キャビティの底面には第１の配線パターンが露出していることから、キャビティに収容した電子部品の放熱性も高められる。しかも、第２の配線パターンがキャビティの開口部を取り囲むように設けられていることから、第２の絶縁層に含まれるフィラーや芯材の脱落も防止される。 According to the present invention, since the cavity is provided in the first and second insulating layers, another electronic component can be housed in the cavity. Thereby, even if another electronic component is thicker than the first electronic component, it is possible to suppress an increase in the overall thickness. Furthermore, since the first wiring pattern is exposed on the bottom surface of the cavity, the heat dissipation of the electronic components housed in the cavity is also improved. Furthermore, since the second wiring pattern is provided so as to surround the opening of the cavity, the filler and core material contained in the second insulating layer are also prevented from falling off.

本発明において、第１の絶縁層は、第２の絶縁層よりも熱膨張係数が大きくても構わないし、厚み方向に対するガラスクロスの比率が第２の絶縁層よりも少ない、或いは、樹脂に含まれるフィラーの充填率が第２の絶縁層よりも少なくても構わない。これによれば、キャビティの内壁をより垂直に近い形状に加工しやすくなるため、電子部品内蔵回路基板の平面サイズを小型化することが可能となる。 In the present invention, the first insulating layer may have a larger coefficient of thermal expansion than the second insulating layer, or the ratio of glass cloth to the thickness direction may be smaller than that of the second insulating layer, or the first insulating layer may have a glass cloth included in the resin. The filling rate of the filler may be lower than that of the second insulating layer. According to this, it becomes easier to process the inner wall of the cavity into a shape that is more nearly vertical, so that the planar size of the circuit board with built-in electronic components can be reduced.

本発明において、第１の配線パターンの外周部は、キャビティの底面に露出することなく第１の絶縁層で覆われていても構わない。これによれば、第１の配線パターンの外周部が第１の絶縁層に固定される。 In the present invention, the outer periphery of the first wiring pattern may be covered with the first insulating layer without being exposed to the bottom surface of the cavity. According to this, the outer peripheral portion of the first wiring pattern is fixed to the first insulating layer.

本発明において、キャビティの内壁がメッキ膜で覆われていても構わない。これによれば、メッキ膜を介した放熱ルートが形成されることから、放熱性をより高めることが可能となる。 In the present invention, the inner wall of the cavity may be covered with a plating film. According to this, a heat dissipation route is formed through the plating film, so that it is possible to further improve heat dissipation performance.

本発明による電子部品内蔵回路基板は、第１の絶縁層と第２の絶縁層の間に設けられた第３の配線パターンをさらに備え、第３の配線パターンは、キャビティの内壁に露出していても構わない。これによれば、第３の配線パターンを介した放熱ルートが形成されることから、放熱性をより高めることが可能となる。 The electronic component built-in circuit board according to the present invention further includes a third wiring pattern provided between the first insulating layer and the second insulating layer, and the third wiring pattern is exposed on the inner wall of the cavity. I don't mind. According to this, a heat dissipation route via the third wiring pattern is formed, so that it is possible to further improve heat dissipation performance.

本発明による電子部品内蔵回路基板は、第１の絶縁層の一方の表面を覆う第３の絶縁層と、第３の絶縁層の第１の絶縁層とは反対側の表面に設けられた第４の配線パターンと、第３の絶縁層を貫通して設けられ、第１の配線パターンと第４の配線パターンを接続するビア導体とをさらに備え、ビア導体は、キャビティと重なる位置に設けられていても構わない。これによれば、キャビティに収容した電子部品からの熱がビア導体を介して効率よく外部に放熱される。このため、高い放熱効率を得ることが可能となる。 The electronic component built-in circuit board according to the present invention includes a third insulating layer covering one surface of the first insulating layer, and a third insulating layer provided on the surface of the third insulating layer opposite to the first insulating layer. 4 wiring pattern and a via conductor provided penetrating the third insulating layer and connecting the first wiring pattern and the fourth wiring pattern, the via conductor provided at a position overlapping with the cavity. It doesn't matter if you stay there. According to this, heat from the electronic components housed in the cavity is efficiently radiated to the outside via the via conductor. Therefore, it is possible to obtain high heat dissipation efficiency.

本発明による電子部品内蔵回路基板は、キャビティに収容され、第１の電子部品よりも厚い第２の電子部品をさらに備えていても構わない。これによれば、基板全体の厚みの増加を抑えつつ、厚みの異なる複数の電子部品を内蔵することが可能となる。 The electronic component built-in circuit board according to the present invention may further include a second electronic component that is housed in the cavity and is thicker than the first electronic component. According to this, it becomes possible to incorporate a plurality of electronic components having different thicknesses while suppressing an increase in the thickness of the entire board.

本発明による電子部品内蔵回路基板は、キャビティに収容され、第１の電子部品よりも厚い第２の電子部品と、キャビティの内壁と第２の電子部品の間に充填された導電性ペーストとをさらに備え、導電性ペーストは、キャビティの内壁に露出する第３の配線パターンと接していても構わない。これによれば、第２の電子部品からの熱をより効率よく放熱することが可能となる。 A circuit board with a built-in electronic component according to the present invention includes a second electronic component that is housed in a cavity and is thicker than the first electronic component, and a conductive paste that is filled between the inner wall of the cavity and the second electronic component. Furthermore, the conductive paste may be in contact with a third wiring pattern exposed on the inner wall of the cavity. According to this, it becomes possible to radiate heat from the second electronic component more efficiently.

本発明による電子部品内蔵回路基板の製造方法は、一方の表面に第１の配線パターンが形成された第１の絶縁層に第１の電子部品を埋め込む第１の工程と、第１の絶縁層の他方の表面に第２の絶縁層を形成する第２の工程と、第１及び第２の絶縁層を貫通するキャビティを形成することにより、キャビティの底面に第１の配線パターンを露出させる第３の工程とを備え、第２の絶縁層の第１の絶縁層とは反対側の表面に設けられた第２の配線パターンは、キャビティの開口部の周囲において第２の絶縁層が露出しないよう、キャビティの開口部を取り囲むように設けられていることを特徴とする。 A method for manufacturing a circuit board with a built-in electronic component according to the present invention includes a first step of embedding a first electronic component in a first insulating layer having a first wiring pattern formed on one surface thereof; a second step of forming a second insulating layer on the other surface of the second insulating layer; and a second step of exposing the first wiring pattern on the bottom surface of the cavity by forming a cavity penetrating the first and second insulating layers. In the second wiring pattern provided on the surface of the second insulating layer opposite to the first insulating layer, the second insulating layer is not exposed around the opening of the cavity. It is characterized in that it is provided so as to surround the opening of the cavity.

本発明によれば、第１及び第２の絶縁層にキャビティが設けられていることから、別の電子部品をキャビティに収容することができる。これにより、別の電子部品が第１の電子部品よりも厚い場合であっても、全体の厚みの増加を抑えることが可能となる。また、キャビティの底面には第１の配線パターンが露出していることから、キャビティに収容した電子部品の放熱性も高められる。しかも、第２の配線パターンがキャビティの開口部を取り囲むように設けられていることから、第２の絶縁層に含まれるフィラーや芯材の脱落も防止される。 According to the present invention, since the cavity is provided in the first and second insulating layers, another electronic component can be housed in the cavity. Thereby, even if another electronic component is thicker than the first electronic component, it is possible to suppress an increase in the overall thickness. Furthermore, since the first wiring pattern is exposed on the bottom surface of the cavity, the heat dissipation of the electronic components housed in the cavity is also improved. Furthermore, since the second wiring pattern is provided so as to surround the opening of the cavity, the filler and core material contained in the second insulating layer are also prevented from falling off.

本発明において、第３の工程は、第２の配線パターンをマスクとし、第１の配線パターンをストッパーとして、第１及び第２の絶縁層の一部を除去することによりキャビティを形成するものであっても構わない。これによれば、キャビティを高精度に形成することが可能となる。 In the present invention, the third step is to form a cavity by removing part of the first and second insulating layers using the second wiring pattern as a mask and the first wiring pattern as a stopper. It doesn't matter if there is. According to this, it becomes possible to form the cavity with high precision.

本発明による電子部品内蔵回路基板の製造方法は、キャビティに、第１の電子部品よりも厚い第２の電子部品を収容する第４の工程をさらに備えるものであっても構わない。これによれば、第２の電子部品による基板全体の厚みの増加を抑えることが可能となる。 The method for manufacturing a circuit board with a built-in electronic component according to the present invention may further include a fourth step of accommodating a second electronic component that is thicker than the first electronic component in the cavity. According to this, it becomes possible to suppress an increase in the thickness of the entire board due to the second electronic component.

このように、本発明によれば、厚みの異なる複数の電子部品を内蔵可能な電子部品内蔵回路基板及びその製造方法において、基板全体の厚みの大幅を抑えることが可能となる。 As described above, according to the present invention, in a circuit board with a built-in electronic component capable of incorporating a plurality of electronic components having different thicknesses and a method for manufacturing the same, it is possible to significantly reduce the thickness of the entire board.

図１は、本発明の第１の実施形態による電子部品内蔵回路基板１の構造を説明するための模式的な断面図である。FIG. 1 is a schematic cross-sectional view for explaining the structure of a circuit board 1 with a built-in electronic component according to a first embodiment of the present invention. 図２は、電子部品内蔵回路基板１の略平面図である。FIG. 2 is a schematic plan view of the circuit board 1 with built-in electronic components. 図３は、本発明の第２の実施形態による電子部品内蔵回路基板２の構造を説明するための模式的な断面図である。FIG. 3 is a schematic cross-sectional view for explaining the structure of the electronic component built-in circuit board 2 according to the second embodiment of the present invention. 図４は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 4 is a process diagram for explaining the first manufacturing method of the electronic component built-in circuit boards 1 and 2. As shown in FIG. 図５は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 5 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図６は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 6 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図７は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 7 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図８は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 8 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図９は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 9 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図１０は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 10 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図１１は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 11 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図１２は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 12 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図１３は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 13 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図１４は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 14 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図１５は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 15 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図１６は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 16 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図１７は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 17 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図１８は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 18 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図１９は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 19 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図２０は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。FIG. 20 is a process diagram for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図２１は、電子部品内蔵回路基板１，２の第２の製造方法を説明するための工程図である。FIG. 21 is a process diagram for explaining the second manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図２２は、電子部品内蔵回路基板１，２の第２の製造方法を説明するための工程図である。FIG. 22 is a process diagram for explaining the second manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図２３は、電子部品内蔵回路基板１，２の第２の製造方法を説明するための工程図である。FIG. 23 is a process diagram for explaining the second manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図２４は、電子部品内蔵回路基板１，２の第３の製造方法を説明するための工程図である。FIG. 24 is a process diagram for explaining the third manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図２５は、電子部品内蔵回路基板１，２の第３の製造方法を説明するための工程図である。FIG. 25 is a process diagram for explaining the third manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図２６は、電子部品内蔵回路基板１，２の第３の製造方法を説明するための工程図である。FIG. 26 is a process diagram for explaining the third manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図２７は、電子部品内蔵回路基板１，２の第３の製造方法を説明するための工程図である。FIG. 27 is a process diagram for explaining the third manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図２８は、電子部品内蔵回路基板１，２の第３の製造方法を説明するための工程図である。FIG. 28 is a process diagram for explaining the third manufacturing method of the circuit boards 1 and 2 with built-in electronic components. 図２９は、電子部品内蔵回路基板１，２の第３の製造方法を説明するための工程図である。FIG. 29 is a process diagram for explaining the third manufacturing method of the circuit boards 1 and 2 with built-in electronic components.

以下、添付図面を参照しながら、本発明の好ましい実施形態について詳細に説明する。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

図１は、本発明の第１の実施形態による電子部品内蔵回路基板１の構造を説明するための模式的な断面図である。また、図２は、電子部品内蔵回路基板１の略平面図である。 FIG. 1 is a schematic cross-sectional view for explaining the structure of a circuit board 1 with a built-in electronic component according to a first embodiment of the present invention. Further, FIG. 2 is a schematic plan view of the circuit board 1 with built-in electronic components.

図１に示すように、第１の実施形態による電子部品内蔵回路基板１は、絶縁層３～５と、絶縁層３～５の各表面に位置する導体層Ｌ１～Ｌ４を有している。特に限定されるものではないが、最下層に位置する絶縁層３及び最上層に位置する絶縁層５は、ガラスクロスなどの芯材にエポキシなどの樹脂材料を含浸させたコア層であっても構わない。これに対し、絶縁層４は、ガラスクロスなどの芯材を含まない無芯材樹脂層であっても構わない。絶縁層４は、絶縁層４ａ，４ｂからなる。特に、絶縁層３，５の熱膨張係数は、絶縁層４の熱膨張係数よりも小さいことが好ましい。このように、無芯材樹脂層である絶縁層４をコア層である絶縁層３，５で挟み込む構造とすれば、電子部品内蔵回路基板１の厚さが薄い場合であっても十分な機械的強度を得ることが可能となる。絶縁層３と絶縁層５の厚みは、互いに同じであっても構わない。 As shown in FIG. 1, the electronic component built-in circuit board 1 according to the first embodiment includes insulating layers 3 to 5 and conductor layers L1 to L4 located on each surface of the insulating layers 3 to 5. Although not particularly limited, the insulating layer 3 located at the bottom layer and the insulating layer 5 located at the top layer may be a core layer made of a core material such as glass cloth impregnated with a resin material such as epoxy. I do not care. On the other hand, the insulating layer 4 may be a coreless resin layer that does not include a core material such as glass cloth. The insulating layer 4 consists of insulating layers 4a and 4b. In particular, it is preferable that the thermal expansion coefficients of the insulating layers 3 and 5 are smaller than that of the insulating layer 4. In this way, if the structure is such that the insulating layer 4, which is a coreless resin layer, is sandwiched between the insulating layers 3 and 5, which are core layers, even if the circuit board 1 with built-in electronic components is thin, it can be sufficiently machined. It becomes possible to obtain target strength. The thicknesses of the insulating layer 3 and the insulating layer 5 may be the same.

絶縁層４には、半導体ＩＣなどの電子部品６０が埋め込まれている。また、電子部品内蔵回路基板１には、電子部品６０の近傍に絶縁層４，５を貫通して設けられたキャビティＣが設けられており、キャビティＣの内部に半導体ＩＣなどの電子部品７０が収容されている。電子部品６０，７０の種類については特に限定されないが、電子部品７０についてはセンサーチップやＬＥＤチップであっても構わないし、電子部品６０については電子部品７０を制御するコントローラチップであっても構わない。キャビティＣを電子部品６０の近傍に設ければ、電子部品６０と電子部品７０を接続する配線の配線長を短くすることができる。電子部品６０は、絶縁層４に埋め込み可能な厚さ、例えば１００μｍ以下に薄型化されている。これに対し、電子部品７０は電子部品６０よりも厚みが大きいが、キャビティＣに収容することによって電子部品内蔵回路基板１の全体の厚みが抑制されている。電子部品７０は、最上層に位置する絶縁層５の表面から突出していても構わない。キャビティＣの内壁は、絶縁層３～５の主面に対して垂直であることが好ましいが、製造プロセスによってはキャビティＣの内壁を完全な垂直とすることは困難であるため、キャビティＣの内壁はテーパー状であっても構わない。 An electronic component 60 such as a semiconductor IC is embedded in the insulating layer 4. Further, the electronic component built-in circuit board 1 is provided with a cavity C that is provided near the electronic component 60 by penetrating the insulating layers 4 and 5, and an electronic component 70 such as a semiconductor IC is installed inside the cavity C. It is accommodated. The types of electronic components 60 and 70 are not particularly limited, but the electronic component 70 may be a sensor chip or an LED chip, and the electronic component 60 may be a controller chip that controls the electronic component 70. . By providing the cavity C near the electronic component 60, the length of the wiring connecting the electronic component 60 and the electronic component 70 can be shortened. The electronic component 60 is thinned to a thickness that can be embedded in the insulating layer 4, for example, 100 μm or less. On the other hand, although the electronic component 70 is thicker than the electronic component 60, by housing it in the cavity C, the overall thickness of the electronic component built-in circuit board 1 is suppressed. The electronic component 70 may protrude from the surface of the insulating layer 5 located at the top layer. The inner wall of the cavity C is preferably perpendicular to the main surfaces of the insulating layers 3 to 5. However, depending on the manufacturing process, it is difficult to make the inner wall of the cavity C completely vertical. may be tapered.

最上層に位置する絶縁層５及びその表面に形成された導体層Ｌ１の一部は、ソルダーレジストＳＲ１によって覆われている。同様に、最下層に位置する絶縁層３及びその表面に形成された導体層Ｌ４の一部は、ソルダーレジストＳＲ２によって覆われている。特に限定されるものではないが、ソルダーレジストＳＲ１は電子部品内蔵回路基板１の上面１ａを構成し、ソルダーレジストＳＲ２は電子部品内蔵回路基板１の下面１ｂを構成する。図示しないが、電子部品内蔵回路基板１の上面１ａには、キャパシタやインダクタなどの電子部品を搭載することができる。下面１ｂにはマザーボードと接続されるユーザー端子を形成することができる。 A part of the insulating layer 5 located at the top layer and the conductor layer L1 formed on the surface thereof are covered with a solder resist SR1. Similarly, a portion of the insulating layer 3 located at the bottom layer and the conductor layer L4 formed on the surface thereof are covered with a solder resist SR2. Although not particularly limited, the solder resist SR1 constitutes the upper surface 1a of the electronic component built-in circuit board 1, and the solder resist SR2 constitutes the lower surface 1b of the electronic component built-in circuit board 1. Although not shown, electronic components such as capacitors and inductors can be mounted on the upper surface 1a of the circuit board 1 with built-in electronic components. User terminals connected to the motherboard can be formed on the lower surface 1b.

導体層Ｌ１は、配線パターン１１～１４を含んでいる。配線パターン１１～１４のうち、ソルダーレジストＳＲ１で覆われていない部分は、ＡｕなどからなるメッキＰが施されていても構わない。配線パターン１１は、ボンディングワイヤＢＷ１を介して電子部品７０のボンディングパッド７１に接続される。同様に、配線パターン１２は、ボンディングワイヤＢＷ２を介して電子部品７０のボンディングパッド７２に接続される。一方、配線パターン１３は、図２に示すように、キャビティＣの開口部の周囲において絶縁層５が露出しないよう、キャビティＣの開口部を取り囲むように設けられている。配線パターン１３は、グランド電位が与えられるグランドパターンであることが好ましい。これによれば、配線パターン１３によってシールド効果も得られる。 The conductor layer L1 includes wiring patterns 11-14. The portions of the wiring patterns 11 to 14 that are not covered with the solder resist SR1 may be plated P made of Au or the like. The wiring pattern 11 is connected to the bonding pad 71 of the electronic component 70 via the bonding wire BW1. Similarly, the wiring pattern 12 is connected to the bonding pad 72 of the electronic component 70 via the bonding wire BW2. On the other hand, the wiring pattern 13 is provided so as to surround the opening of the cavity C so that the insulating layer 5 is not exposed around the opening of the cavity C, as shown in FIG. The wiring pattern 13 is preferably a ground pattern to which a ground potential is applied. According to this, a shielding effect can also be obtained by the wiring pattern 13.

導体層Ｌ２は、配線パターン２１～２３を含んでいる。配線パターン２１～２３は、絶縁層５を貫通して設けられたビア導体５０～５２を介して、導体層Ｌ１の配線パターン１１，１２，１４にそれぞれ接続されている。また、配線パターン２２，２３は、平面視で電子部品６０と重なる位置に設けられたビア導体５５，５６を介して、電子部品６０の端子電極６１，６２にそれぞれ接続されている。 The conductor layer L2 includes wiring patterns 21-23. The wiring patterns 21 to 23 are connected to the wiring patterns 11, 12, and 14 of the conductor layer L1 through via conductors 50 to 52 provided through the insulating layer 5, respectively. Further, the wiring patterns 22 and 23 are connected to terminal electrodes 61 and 62 of the electronic component 60, respectively, via via conductors 55 and 56 provided at positions overlapping with the electronic component 60 in plan view.

導体層Ｌ３は、配線パターン３１～３３を含んでいる。配線パターン３１は、キャビティＣの底面に露出しており、ダイアタッチフィルム７３を介して電子部品７０に接着されている。配線パターン３１の外周部は、絶縁層４ａに覆われている。配線パターン３２，３３は、絶縁層４を貫通して設けられたビア導体５３，５４を介して、導体層Ｌ２の配線パターン２１，２３にそれぞれ接続されている。ビア導体５３，５４は、平面視で電子部品６０と重ならない位置に配置されている。 The conductor layer L3 includes wiring patterns 31-33. The wiring pattern 31 is exposed on the bottom surface of the cavity C and is bonded to the electronic component 70 via a die attach film 73. The outer periphery of the wiring pattern 31 is covered with an insulating layer 4a. The wiring patterns 32 and 33 are connected to the wiring patterns 21 and 23 of the conductor layer L2 via via conductors 53 and 54 provided through the insulating layer 4, respectively. Via conductors 53 and 54 are arranged at positions that do not overlap electronic component 60 in plan view.

導体層Ｌ４は、配線パターン４１～４３を含んでいる。配線パターン４１～４３は、絶縁層３を貫通して設けられたビア導体５７～５９を介して、導体層Ｌ３の配線パターン３１～３３にそれぞれ接続されている。特に、配線パターン３１と配線パターン４１を接続するビア導体５７は複数個設けられ、且つ、複数のビア導体５７の少なくとも一部は電子部品７０と重なりを有している。これにより、電子部品７０の動作によって生じる熱は、配線パターン３１、ビア導体５７及び配線パターン４１を介して、効率よく外部に放出される。配線パターン４１～４３のうち、ソルダーレジストＳＲ２で覆われていない部分は、ＡｕなどからなるメッキＰが施されていても構わない。 The conductor layer L4 includes wiring patterns 41-43. The wiring patterns 41 to 43 are connected to the wiring patterns 31 to 33 of the conductor layer L3 via via conductors 57 to 59 provided through the insulating layer 3, respectively. In particular, a plurality of via conductors 57 connecting the wiring pattern 31 and the wiring pattern 41 are provided, and at least a portion of the plurality of via conductors 57 overlaps with the electronic component 70 . Thereby, heat generated by the operation of the electronic component 70 is efficiently released to the outside via the wiring pattern 31, the via conductor 57, and the wiring pattern 41. The portions of the wiring patterns 41 to 43 that are not covered with the solder resist SR2 may be plated P made of Au or the like.

以上が第１の実施形態による電子部品内蔵回路基板１の構造である。このように、本実施形態による電子部品内蔵回路基板１は、厚みの薄い電子部品６０を絶縁層４に埋め込むとともに、厚みの大きい電子部品７０をキャビティＣの内部に収容していることから、基板全体の厚みの増加を抑えることが可能となる。また、キャビティＣの底面には配線パターン３１が露出しており、配線パターン３１上に電子部品７０が載置されていることから、電子部品７０の熱を効率よく外部に排出することが可能となる。しかも、キャビティＣの開口部の周囲において絶縁層５が露出しないよう、配線パターン１３がキャビティＣの開口部を取り囲むように設けられていることから、絶縁層５に含まれるガラスクロスなどの芯材の脱落を防止することが可能となる。 The above is the structure of the electronic component built-in circuit board 1 according to the first embodiment. As described above, the electronic component built-in circuit board 1 according to the present embodiment has the thin electronic component 60 embedded in the insulating layer 4 and the thick electronic component 70 housed inside the cavity C. It becomes possible to suppress an increase in the overall thickness. Furthermore, since the wiring pattern 31 is exposed on the bottom surface of the cavity C and the electronic component 70 is placed on the wiring pattern 31, it is possible to efficiently discharge the heat of the electronic component 70 to the outside. Become. Moreover, since the wiring pattern 13 is provided so as to surround the opening of the cavity C so that the insulation layer 5 is not exposed around the opening of the cavity C, the core material such as glass cloth included in the insulation layer 5 This makes it possible to prevent the material from falling off.

図３は、本発明の第２の実施形態による電子部品内蔵回路基板２の構造を説明するための模式的な断面図である。 FIG. 3 is a schematic cross-sectional view for explaining the structure of the electronic component built-in circuit board 2 according to the second embodiment of the present invention.

図３に示すように、第２の実施形態による電子部品内蔵回路基板３は、キャビティＣの内壁と電子部品７０の間に電子部品７０を固定するための導電性ペースト７４が充填されている点において、第１の実施形態による電子部品内蔵回路基板１と相違している。その他の基本的な構成は、第１の実施形態による電子部品内蔵回路基板１と同じであることから同一の要素には同一の符号を付し、重複する説明は省略する。 As shown in FIG. 3, the electronic component built-in circuit board 3 according to the second embodiment has a conductive paste 74 filled between the inner wall of the cavity C and the electronic component 70 for fixing the electronic component 70. This is different from the electronic component built-in circuit board 1 according to the first embodiment. Other basic configurations are the same as the electronic component built-in circuit board 1 according to the first embodiment, so the same elements are denoted by the same reference numerals and redundant explanations will be omitted.

本実施形態のように、キャビティＣの内壁と電子部品７０の間に導電性ペースト７４を充填すれば、放熱効率をより高めることが可能となる。この場合、符号Ａで示すように、導体層Ｌ２に位置する配線パターンの一部、例えば配線パターン２１をキャビティＣの内壁に露出させ、キャビティＣの内壁に露出する配線パターン２１と導電性ペースト７４を接触させれば、放熱効率をよりいっそう高めることが可能となる。導電性ペースト７４は、電子部品７０の搭載時に電子部品７０の底面から側面に回り込ませることにより、電子部品７０の裏面及び側面に単一の工程で充填することができる。本実施形態においても導電性又は非導電性のダイアタッチフィルム７３を使用しても構わない。この場合、放熱性の観点から、導電性のダイアタッチフィルム７３を用いることが望ましい。また、導電性ペースト７４の代わりに非導電性ペーストを用いても構わないが、放熱性の観点から、導電性ペースト７４を用いることが望ましい。 If the conductive paste 74 is filled between the inner wall of the cavity C and the electronic component 70 as in this embodiment, it is possible to further improve the heat dissipation efficiency. In this case, as shown by symbol A, a part of the wiring pattern located in the conductor layer L2, for example, the wiring pattern 21, is exposed on the inner wall of the cavity C, and the wiring pattern 21 and the conductive paste 74 exposed on the inner wall of the cavity C are exposed. By bringing them into contact with each other, it is possible to further improve heat dissipation efficiency. The conductive paste 74 can be filled into the back and side surfaces of the electronic component 70 in a single process by passing it around from the bottom surface to the side surface of the electronic component 70 when the electronic component 70 is mounted. In this embodiment as well, a conductive or non-conductive die attach film 73 may be used. In this case, from the viewpoint of heat dissipation, it is desirable to use a conductive die attach film 73. Further, although a non-conductive paste may be used instead of the conductive paste 74, it is desirable to use the conductive paste 74 from the viewpoint of heat dissipation.

次に、電子部品内蔵回路基板１，２の製造方法について説明する。 Next, a method for manufacturing the electronic component built-in circuit boards 1 and 2 will be described.

図４～図２０は、電子部品内蔵回路基板１，２の第１の製造方法を説明するための工程図である。 4 to 20 are process diagrams for explaining the first manufacturing method of the circuit boards 1 and 2 with built-in electronic components.

まず、図４に示すように、ガラス繊維などの芯材を含む絶縁層３の両面にＣｕ等の導体箔からなる導体層Ｌ３，Ｌ４ａが貼合されてなる基材（ワークボード）、すなわち両面ＣＣＬ（Copper Clad Laminate）を準備する。絶縁層３に含まれる芯材の厚みは、ハンドリングを容易にするための適度な剛性を確保するため、４０μｍ以上であることが望ましい。なお、導体層Ｌ３，Ｌ４ａの材質については特に制限されず、上述したＣｕの他、例えば、Ａｕ、Ａｇ、Ｎｉ、Ｐｄ、Ｓｎ、Ｃｒ、Ａｌ、Ｗ、Ｆｅ、Ｔｉ、ＳＵＳ材等の金属導電材料が挙げられ、これらの中でも、導電率やコストの観点からＣｕを用いることが好ましい。後述する他の導体層Ｌ１，Ｌ２についても同様である。また、導体層Ｌ３の表面Ｌ３ａは、絶縁層４ａに対する密着性を高めるために、粗化されていることが好ましい。 First, as shown in FIG. 4, a base material (workboard) is formed by laminating conductive layers L3 and L4a made of conductive foil such as Cu on both sides of an insulating layer 3 containing a core material such as glass fiber. Prepare CCL (Copper Clad Laminate). The thickness of the core material included in the insulating layer 3 is preferably 40 μm or more in order to ensure appropriate rigidity for easy handling. Note that the material of the conductor layers L3 and L4a is not particularly limited, and in addition to the above-mentioned Cu, for example, conductive metals such as Au, Ag, Ni, Pd, Sn, Cr, Al, W, Fe, Ti, SUS materials, etc. Among these materials, it is preferable to use Cu from the viewpoint of electrical conductivity and cost. The same applies to other conductor layers L1 and L2, which will be described later. Further, the surface L3a of the conductor layer L3 is preferably roughened in order to improve adhesion to the insulating layer 4a.

また、絶縁層３に用いる樹脂材料は、シート状又はフィルム状に成形可能なものであれば特に制限されず使用可能であり、ガラスエポキシの他、例えば、ビニルベンジル樹脂、ポリビニルベンジルエーテル化合物樹脂、ビスマレイミドトリアジン樹脂（ＢＴレジン）、ポリフェニレエーテル（ポリフェニレンエーテルオキサイド）樹脂（ＰＰＥ，ＰＰＯ）、シアネートエステル樹脂、エポキシ＋活性エステル硬化樹脂、ポリフェニレンエーテル樹脂（ポリフェニレンオキサオド樹脂）、硬化性ポリオレフィン樹脂、ベンゾシクロブテン樹脂、ポリイミド樹脂、芳香族ポリエステル樹脂、芳香族液晶ポリエステル樹脂、ポリフェニレンサルファイド樹脂、ポリエーテルイミド樹脂、ポリアクリレート樹脂、ポリエーテルエーテルケトン樹脂、フッ素樹脂、エポキシ樹脂、フェノール樹脂、若しくはベンゾオキサジン樹脂の単体、又は、これらの樹脂に、シリカ、タルク、炭酸カルシウム、炭酸マグネシウム、水酸化アルミニウム、水酸化マグネシウム、ホウ酸アルミウイスカ、チタン酸カリウム繊維、アルミナ、ガラスフレーク、ガラス繊維、窒化タンタル、窒化アルミニウム等を添加した材料、さらに、これらの樹脂に、マグネシウム、ケイ素、チタン、亜鉛、カルシウム、ストロンチウム、ジルコニウム、錫、ネオジウム、サマリウム、アルミニウム、ビスマス、鉛、ランタン、リチウム及びタンタルのうち少なくとも１種の金属を含む金属酸化物粉末を添加した材料を用いることができ、電気特性、機械特性、吸水性、リフロー耐性等の観点から、適宜選択して用いることができる。さらに、絶縁層３に含まれる芯材としては、ガラス繊維、アラミド繊維等の樹脂繊維等を配合した材料を挙げることができる。後述する他の絶縁層４ａ，４ｂ，５についても同様である。 Further, the resin material used for the insulating layer 3 is not particularly limited as long as it can be molded into a sheet or film shape, and in addition to glass epoxy, for example, vinyl benzyl resin, polyvinyl benzyl ether compound resin, Bismaleimide triazine resin (BT resin), polyphenylene ether (polyphenylene ether oxide) resin (PPE, PPO), cyanate ester resin, epoxy + active ester cured resin, polyphenylene ether resin (polyphenylene oxaoxide resin), curable polyolefin resin, Benzocyclobutene resin, polyimide resin, aromatic polyester resin, aromatic liquid crystal polyester resin, polyphenylene sulfide resin, polyetherimide resin, polyacrylate resin, polyether ether ketone resin, fluororesin, epoxy resin, phenol resin, or benzoxazine Single resin or these resins, silica, talc, calcium carbonate, magnesium carbonate, aluminum hydroxide, magnesium hydroxide, aluminum borate whisker, potassium titanate fiber, alumina, glass flakes, glass fiber, tantalum nitride, A material to which aluminum nitride or the like is added, and at least one of magnesium, silicon, titanium, zinc, calcium, strontium, zirconium, tin, neodymium, samarium, aluminum, bismuth, lead, lanthanum, lithium, and tantalum to these resins. A material to which metal oxide powder containing a seed metal is added can be used, and can be appropriately selected and used from the viewpoint of electrical properties, mechanical properties, water absorption, reflow resistance, etc. Further, as the core material included in the insulating layer 3, a material blended with resin fibers such as glass fibers and aramid fibers can be mentioned. The same applies to other insulating layers 4a, 4b, and 5, which will be described later.

次に、図５に示すように、例えばフォトリソグラフィー法など公知の手法を用いて導体層Ｌ３をパターニングすることにより、配線パターン３１～３３を形成する。次に、図６に示すように、導体層Ｌ３を埋め込むよう、絶縁層３の表面に例えば未硬化（Ｂステージ状態）の樹脂シート等を真空圧着等によって積層することにより、絶縁層４ａを形成する。 Next, as shown in FIG. 5, wiring patterns 31 to 33 are formed by patterning the conductor layer L3 using a known method such as photolithography. Next, as shown in FIG. 6, an insulating layer 4a is formed by laminating, for example, an uncured (B stage state) resin sheet on the surface of the insulating layer 3 by vacuum pressure bonding or the like so as to embed the conductor layer L3. do.

次に、図７に示すように、絶縁層４ａ上に電子部品６０を載置する。電子部品６０は、端子電極６１，６２が形成された主面が上側を向くよう、フェースアップ方式で搭載される。電子部品６０が半導体ＩＣである場合、シリコン基板が例えば２００μｍ以下、より好ましくは５０～１００μｍ程度に薄型化されていても構わない。 Next, as shown in FIG. 7, an electronic component 60 is placed on the insulating layer 4a. The electronic component 60 is mounted face-up so that the main surface on which the terminal electrodes 61 and 62 are formed faces upward. When the electronic component 60 is a semiconductor IC, the silicon substrate may be thinned to, for example, 200 μm or less, more preferably about 50 to 100 μm.

次に、図８に示すように、電子部品６０を覆うよう、絶縁層４ｂ及び導体層Ｌ２ａを形成する。絶縁層４ｂの形成は、例えば、未硬化又は半硬化状態の熱硬化性樹脂を塗布した後、未硬化樹脂の場合それを加熱して半硬化させ、さらに、プレス手段を用いて導体層Ｌ２ａとともに硬化成形することが好ましい。絶縁層４ｂは、電子部品６０の埋め込みを妨げる繊維が含まれない樹脂シートが望ましい。これにより、電子部品６０が絶縁層４に埋め込まれる。 Next, as shown in FIG. 8, an insulating layer 4b and a conductive layer L2a are formed to cover the electronic component 60. The insulating layer 4b is formed, for example, by applying an uncured or semi-cured thermosetting resin, then heating it to semi-cure it in the case of an uncured resin, and then applying it together with the conductor layer L2a using a press. Curing and molding is preferred. The insulating layer 4b is preferably a resin sheet that does not contain fibers that would prevent the electronic component 60 from being embedded. Thereby, the electronic component 60 is embedded in the insulating layer 4.

次に、図９に示すように、例えばフォトリソグラフィー法など公知の手法を用いて導体層Ｌ２ａの一部をエッチングにより除去することにより、絶縁層４を露出させる開口部５３ａ～５６ａを形成する。このうち、開口部５３ａ，５４ａはそれぞれ配線パターン３２，３３と重なる位置に形成され、開口部５５ａ，５６ａはそれぞれ電子部品６０の端子電極６１，６２と重なる位置に形成される。 Next, as shown in FIG. 9, openings 53a to 56a exposing the insulating layer 4 are formed by removing a portion of the conductor layer L2a by etching using a known method such as photolithography. Among these, openings 53a and 54a are formed at positions overlapping with wiring patterns 32 and 33, respectively, and openings 55a and 56a are formed at positions overlapping with terminal electrodes 61 and 62 of electronic component 60, respectively.

次に、図１０に示すように、導体層Ｌ２ａをマスクとしてレーザー加工又はブラスト加工を行うことにより、導体層Ｌ２ａで覆われていない部分における絶縁層４を除去する。これにより、開口部５３ａ～５６ａに対応する位置には、それぞれビア５３ｂ～５６ｂが形成される。ビア５３ｂ～５６ｂの底部においては、それぞれ配線パターン３２，３３及び端子電極６１，６２が露出する。 Next, as shown in FIG. 10, the portions of the insulating layer 4 not covered with the conductor layer L2a are removed by laser processing or blasting using the conductor layer L2a as a mask. As a result, vias 53b to 56b are formed at positions corresponding to openings 53a to 56a, respectively. At the bottoms of vias 53b to 56b, wiring patterns 32 and 33 and terminal electrodes 61 and 62 are exposed, respectively.

次に、図１１に示すように、無電解メッキ及び電解メッキを施すことにより、ビア５３ｂ～５６ｂの内部にそれぞれビア導体５３～５６を形成する。無電解メッキ及び電解メッキを行う前に、導体層Ｌ２ａを全て削除しても構わない。これにより、ビア導体５３～５６を介して、導体層Ｌ３の配線パターン３２，３３及び電子部品６０の端子電極６１，６２が導体層Ｌ２に接続される。次に、図１２に示すように、導体層Ｌ２をフォトリソグラフィー法など公知の手法によってパターニングすることにより、配線パターン２１～２３を形成する。 Next, as shown in FIG. 11, via electroless plating and electrolytic plating are performed to form via conductors 53 to 56 inside the vias 53b to 56b, respectively. The conductor layer L2a may be completely removed before performing electroless plating and electrolytic plating. Thereby, the wiring patterns 32 and 33 of the conductor layer L3 and the terminal electrodes 61 and 62 of the electronic component 60 are connected to the conductor layer L2 via the via conductors 53 to 56. Next, as shown in FIG. 12, wiring patterns 21 to 23 are formed by patterning the conductor layer L2 by a known method such as photolithography.

次に、図１３に示すように、導体層Ｌ２を埋め込むよう、絶縁層５と導体層Ｌ１ａが積層されたシートを真空熱プレスする。次に、図１４に示すように、例えばフォトリソグラフィー法など公知の手法を用いて導体層Ｌ１ａ，Ｌ４ａの一部をエッチングにより除去することにより、導体層Ｌ１ａに絶縁層５を露出させる開口部５０ａ～５２ａを形成し、導体層Ｌ４ａに絶縁層３を露出させる開口部５７ａ～５９ａを形成する。このうち、開口部５０ａ～５２ａはそれぞれ配線パターン２１～２３と重なる位置に形成され、開口部５７ａ～５９ａはそれぞれ配線パターン３１～３３と重なる位置に形成される。 Next, as shown in FIG. 13, the sheet in which the insulating layer 5 and the conductor layer L1a are laminated is vacuum hot pressed so as to embed the conductor layer L2. Next, as shown in FIG. 14, a part of the conductor layers L1a and L4a is removed by etching using a known method such as photolithography, thereby forming an opening 50a in which the insulating layer 5 is exposed in the conductor layer L1a. 52a are formed, and openings 57a to 59a exposing the insulating layer 3 are formed in the conductor layer L4a. Among these, openings 50a to 52a are formed at positions overlapping with wiring patterns 21 to 23, respectively, and openings 57a to 59a are formed at positions overlapping with wiring patterns 31 to 33, respectively.

次に、図１５に示すように、導体層Ｌ１ａ，Ｌ４ａをマスクとしてレーザー加工又はブラスト加工を行うことにより、導体層Ｌ１ａで覆われていない部分における絶縁層５を除去するとともに、導体層Ｌ４ａで覆われていない部分における絶縁層３を除去する。これにより、開口部５０ａ～５２ａ，５７ａ～５９ａに対応する位置には、それぞれビア５０ｂ～５２ｂ，５７ｂ～５９ｂが形成される。ビア５０ｂ～５２ｂ，５７ｂ～５９ｂの底部においては、それぞれ配線パターン２１～２３，３１～３３が露出する。 Next, as shown in FIG. 15, by performing laser processing or blasting using the conductor layers L1a and L4a as masks, the insulating layer 5 in the portions not covered with the conductor layer L1a is removed, and the conductor layer L4a is removed. The insulating layer 3 in the uncovered parts is removed. As a result, vias 50b to 52b and 57b to 59b are formed at positions corresponding to openings 50a to 52a and 57a to 59a, respectively. Wiring patterns 21 to 23 and 31 to 33 are exposed at the bottoms of vias 50b to 52b and 57b to 59b, respectively.

次に、図１６に示すように、無電解メッキ及び電解メッキを施すことにより、ビア５０ｂ～５２ｂ，５７ｂ～５９ｂの内部にそれぞれビア導体５０～５２，５７～５９を形成する。無電解メッキ及び電解メッキを行う前に、導体層Ｌ１ａ，Ｌ４ａを全て削除しても構わない。次に、図１７に示すように、導体層Ｌ１，Ｌ４をフォトリソグラフィー法など公知の手法によってパターニングすることにより、導体層Ｌ１に配線パターン１１～１３を形成し、導体層Ｌ４に配線パターン４１～４３を形成する。次に、図１８に示すように、所定の平面位置にソルダーレジストＳＲ１，ＳＲ２を形成する。 Next, as shown in FIG. 16, via conductors 50 to 52 and 57 to 59 are formed inside the vias 50b to 52b and 57b to 59b, respectively, by performing electroless plating and electrolytic plating. The conductor layers L1a and L4a may all be removed before performing electroless plating and electrolytic plating. Next, as shown in FIG. 17, the conductor layers L1 and L4 are patterned by a known method such as photolithography to form wiring patterns 11 to 13 on the conductor layer L1, and wiring patterns 41 to 41 on the conductor layer L4. Form 43. Next, as shown in FIG. 18, solder resists SR1 and SR2 are formed at predetermined planar positions.

次に、図１９に示すように、平面視で配線パターン１３に囲まれた領域に位置する絶縁層４，５を除去することにより、キャビティＣを形成する。キャビティＣの形成は、レーザー加工又はブラスト加工により行うことができる。この場合、配線パターン１３をマスクの一部とし、配線パターン３１をストッパーとして加工を行うことにより、所望の形状を有するキャビティＣを容易に形成することができる。また、キャビティＣを形成すると、絶縁層５に含まれるガラスクロスなどの芯材がキャビティＣの内部に突出することがある。このような場合であっても、配線パターン１３がキャビティＣの開口部を取り囲むように設けられ、これによりキャビティＣの開口部の周囲が配線パターン１３によって押さえられることから、ガラスクロスなどの芯材の脱落が生じにくい。 Next, as shown in FIG. 19, a cavity C is formed by removing the insulating layers 4 and 5 located in a region surrounded by the wiring pattern 13 in plan view. The cavity C can be formed by laser processing or blasting. In this case, the cavity C having a desired shape can be easily formed by using the wiring pattern 13 as part of a mask and using the wiring pattern 31 as a stopper. Furthermore, when the cavity C is formed, a core material such as glass cloth included in the insulating layer 5 may protrude into the cavity C. Even in such a case, since the wiring pattern 13 is provided so as to surround the opening of the cavity C, and the periphery of the opening of the cavity C is pressed by the wiring pattern 13, a core material such as glass cloth can be used. is less likely to fall off.

レーザー加工又はブラスト加工においては、被加工物の厚み方向に対するガラスクロスの比率が多いほど、また、被加工物である樹脂に含まれるフィラーの充填率が多いほど、単位時間当たりの加工量が少なくなる。このことは、一般に、被加工物の熱膨張係数が大きいほど単位時間当たりの加工量が多くなることを意味する。このため、絶縁層５よりも絶縁層４の熱膨張係数が大きい場合、絶縁層５を加工する第１段階、つまりアスペクト比が小さい段階においては、単位時間当たりの加工量が比較的小さい。これに対し、絶縁層４を加工する第２の段階、つまりアスペクト比が大きい段階においては、単位時間当たりの加工量が比較的大きくなる。これにより、アスペクト比の大きいキャビティを形成する場合に生じる内壁のテーパーが抑えられ、より垂直に近い内壁を有するキャビティＣを形成することが可能となる。但し、キャビティＣの形成方法がレーザー加工又はブラスト加工に限定されるものではなく、他の方法、例えばドリル加工を用いても構わない。 In laser processing or blasting, the higher the ratio of glass cloth to the thickness of the workpiece, and the higher the filling rate of filler contained in the resin that is the workpiece, the smaller the amount of processing per unit time. Become. This generally means that the larger the coefficient of thermal expansion of the workpiece, the greater the amount of processing per unit time. Therefore, when the thermal expansion coefficient of the insulating layer 4 is larger than that of the insulating layer 5, the amount of processing per unit time is relatively small in the first stage of processing the insulating layer 5, that is, the stage where the aspect ratio is small. On the other hand, in the second stage of processing the insulating layer 4, that is, the stage where the aspect ratio is large, the amount of processing per unit time becomes relatively large. This suppresses the taper of the inner wall that occurs when forming a cavity with a large aspect ratio, and it becomes possible to form a cavity C having an inner wall that is more nearly vertical. However, the method for forming the cavity C is not limited to laser processing or blasting, and other methods such as drilling may be used.

そして、図２０に示すように、ソルダーレジストＳＲ１，ＳＲ２から露出する配線パターン１１～１３，４１～４３の表面にＡｕなどからなるメッキＰを形成すれば、電子部品内蔵回路基板１又は２の前駆体が完成する。電子部品内蔵回路基板１又は２の前駆体は、キャビティＣに電子部品７０を収容する前の半完成品である。そして、電子部品内蔵回路基板１又は２の前駆体に電子部品７０を収容し、ボンディングワイヤＢＷ１，ＢＷ２を用いた電気的接続を行えば、電子部品内蔵回路基板１又は２が完成する。 Then, as shown in FIG. 20, if a plating P made of Au or the like is formed on the surfaces of the wiring patterns 11 to 13 and 41 to 43 exposed from the solder resists SR1 and SR2, the precursor of the circuit board 1 or 2 with built-in electronic components can be formed. The body is completed. The precursor of the electronic component built-in circuit board 1 or 2 is a semi-finished product before the electronic component 70 is housed in the cavity C. Then, by accommodating the electronic component 70 in the precursor of the electronic component built-in circuit board 1 or 2 and performing electrical connection using bonding wires BW1 and BW2, the electronic component built-in circuit board 1 or 2 is completed.

このように、キャビティＣをレーザー加工又はブラスト加工によって形成する場合であっても、下層に位置する絶縁層４の材料として、ガラスクロスを含まず、且つ、上層に位置する絶縁層５よりも樹脂に含まれるフィラーの充填率が少なく、これにより絶縁層５よりも熱膨張係数の大きい材料を用いれば、キャビティＣの内壁をより垂直に加工することが可能となる。これにより、電子部品内蔵回路基板１又は２の平面サイズを小型化することが可能となる。しかも、配線パターン１３をマスクとし、配線パターン３１をストッパーとしてレーザー加工又はブラスト加工を行えば、所望の形状を有するキャビティＣを容易に形成することが可能となる。さらに、配線パターン３１の全部を露出させるのではなく、配線パターン３１の外周部を絶縁層４ａに埋め込むことにより、キャビティＣに収容された電子部品７０の固着強度が増し、信頼性を向上させることが可能となる。 In this way, even when the cavity C is formed by laser processing or blasting, the material of the lower insulating layer 4 does not contain glass cloth and is made of resin rather than the upper insulating layer 5. The filling rate of the filler contained in the insulating layer 5 is small, and if a material having a coefficient of thermal expansion larger than that of the insulating layer 5 is used, it becomes possible to process the inner wall of the cavity C more vertically. This makes it possible to reduce the planar size of the electronic component built-in circuit board 1 or 2. Moreover, by performing laser processing or blast processing using the wiring pattern 13 as a mask and the wiring pattern 31 as a stopper, it becomes possible to easily form the cavity C having a desired shape. Furthermore, by embedding the outer periphery of the wiring pattern 31 in the insulating layer 4a instead of exposing the entire wiring pattern 31, the adhesion strength of the electronic component 70 housed in the cavity C is increased, and reliability is improved. becomes possible.

図２１～図２３は、電子部品内蔵回路基板１，２の第２の製造方法を説明するための工程図である。 21 to 23 are process diagrams for explaining the second manufacturing method of the circuit boards 1 and 2 with built-in electronic components.

まず、図４～図１７に示した工程を行った後、図２１に示すように、キャビティＣを形成する。キャビティＣの形成方法は上述の通りである。次に、図２２に示すように、所定の平面位置にソルダーレジストＳＲ１，ＳＲ２を形成した後、図２３に示すように、ソルダーレジストＳＲ１，ＳＲ２から露出する配線パターン１１～１３，４１～４３の表面にＡｕなどからなるメッキＰを形成すれば、電子部品内蔵回路基板１又は２の前駆体が完成する。 First, after performing the steps shown in FIGS. 4 to 17, a cavity C is formed as shown in FIG. The method for forming the cavity C is as described above. Next, as shown in FIG. 22, after forming solder resists SR1 and SR2 at predetermined planar positions, as shown in FIG. By forming plating P made of Au or the like on the surface, a precursor of electronic component built-in circuit board 1 or 2 is completed.

このように、キャビティＣの形成は、ソルダーレジストＳＲ１，ＳＲ２の形成よりも前に行っても構わない。 In this way, the cavity C may be formed before the solder resists SR1 and SR2 are formed.

図２４～図２９は、電子部品内蔵回路基板１，２の第３の製造方法を説明するための工程図である。 FIGS. 24 to 29 are process diagrams for explaining the third manufacturing method of the circuit boards 1 and 2 with built-in electronic components.

まず、図４～図１３に示した工程を行った後、図２４に示すように、例えばフォトリソグラフィー法など公知の手法を用いて導体層Ｌ１，Ｌ４の一部をエッチングにより除去することにより、導体層Ｌ１に絶縁層５を露出させる開口部５０ａ～５２ａ，Ｃａを形成し、導体層Ｌ４に絶縁層３を露出させる開口部５７ａ～５９ａを形成する。開口部Ｃａは、配線パターン３１と重なる位置に設けられる。次に、図２５に示すように、導体層Ｌ１，Ｌ４をマスクとしてレーザー加工又はブラスト加工を行うことにより、導体層Ｌ１で覆われていない部分における絶縁層５を除去するとともに、導体層Ｌ４で覆われていない部分における絶縁層３を除去する。これにより、開口部５０ａ～５２ａ，５７ａ～５９ａに対応する位置には、それぞれビア５０ｂ～５２ｂ，５７ｂ～５９ｂが形成され、開口部Ｃａに対応する位置にはキャビティＣが形成される。開口部５０ａ～５２ａの形成とキャビティＣの形成は、同時に行っても構わないし、順次行っても構わない。 First, after performing the steps shown in FIGS. 4 to 13, as shown in FIG. 24, a part of the conductor layers L1 and L4 is removed by etching using a known method such as photolithography, for example. Openings 50a to 52a and Ca that expose the insulating layer 5 are formed in the conductor layer L1, and openings 57a to 59a that expose the insulating layer 3 are formed in the conductor layer L4. The opening Ca is provided at a position overlapping the wiring pattern 31. Next, as shown in FIG. 25, by performing laser processing or blasting using the conductor layers L1 and L4 as masks, the insulating layer 5 in the portions not covered with the conductor layer L1 is removed, and the conductor layer L4 is removed. The insulating layer 3 in the uncovered parts is removed. As a result, vias 50b to 52b and 57b to 59b are formed at the positions corresponding to the openings 50a to 52a and 57a to 59a, respectively, and a cavity C is formed at the position corresponding to the opening Ca. The formation of the openings 50a to 52a and the cavity C may be performed simultaneously or sequentially.

次に、図２６に示すように、無電解メッキ及び電解メッキを施すことにより、ビア５０ｂ～５２ｂ，５７ｂ～５９ｂの内部にそれぞれビア導体５０～５２，５７～５９を形成する。この時、キャビティＣの内壁にもメッキ膜８０が形成される。このため、キャビティＣの内壁に配線パターン２１が露出している場合、メッキ膜８０は配線パターン２１に接続される。 Next, as shown in FIG. 26, via conductors 50 to 52 and 57 to 59 are formed inside the vias 50b to 52b and 57b to 59b, respectively, by performing electroless plating and electrolytic plating. At this time, the plating film 80 is also formed on the inner wall of the cavity C. Therefore, when the wiring pattern 21 is exposed on the inner wall of the cavity C, the plating film 80 is connected to the wiring pattern 21.

次に、図２７に示すように、導体層Ｌ１，Ｌ４をフォトリソグラフィー法など公知の手法によってパターニングすることにより、導体層Ｌ１に配線パターン１１～１３を形成し、導体層Ｌ４に配線パターン４１～４３を形成する。次に、図２８に示すように、所定の平面位置にソルダーレジストＳＲ１，ＳＲ２を形成した後、図２９に示すように、ソルダーレジストＳＲ１，ＳＲ２から露出する配線パターン１１～１３，４１～４３の表面にＡｕなどからなるメッキＰを形成すれば、電子部品内蔵回路基板１又は２の前駆体が完成する。 Next, as shown in FIG. 27, the conductor layers L1 and L4 are patterned by a known method such as photolithography to form wiring patterns 11 to 13 on the conductor layer L1, and wiring patterns 41 to 41 on the conductor layer L4. Form 43. Next, as shown in FIG. 28, after forming solder resists SR1 and SR2 at predetermined planar positions, as shown in FIG. By forming plating P made of Au or the like on the surface, a precursor of electronic component built-in circuit board 1 or 2 is completed.

このように、開口部５０ａ～５２ａを形成する工程においてキャビティＣを形成しても構わない。これによれば、キャビティＣを形成する工程において、キャビティＣを形成すべき表面以外の部分を覆うマスクを形成する必要がなくなる。また、キャビティＣの内壁に配線パターン２１が露出している場合、キャビティＣの内壁を覆うメッキ膜８０が配線パターン２１に接続されることから、電子部品７０の熱がメッキ膜８０を介して配線パターン２１に伝わる。このため、放熱性をより高めることが可能となる。 In this way, the cavity C may be formed in the step of forming the openings 50a to 52a. According to this, in the step of forming the cavity C, there is no need to form a mask that covers a portion other than the surface where the cavity C is to be formed. Furthermore, when the wiring pattern 21 is exposed on the inner wall of the cavity C, the plating film 80 covering the inner wall of the cavity C is connected to the wiring pattern 21, so that the heat of the electronic component 70 is transferred to the wiring via the plating film 80. This is reflected in pattern 21. Therefore, it becomes possible to further improve heat dissipation.

以上、本発明の好ましい実施形態について説明したが、本発明は、上記の実施形態に限定されることなく、本発明の主旨を逸脱しない範囲で種々の変更が可能であり、それらも本発明の範囲内に包含されるものであることはいうまでもない。 Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention. Needless to say, it is included within the scope.

例えば、上記実施形態においては、絶縁層４及び５にキャビティＣを形成しているが、絶縁層３及び４に逆方向からキャビティＣを形成しても構わない。この場合、導体層Ｌ３に位置する配線パターン３１に相当する要素を導体層Ｌ２に形成すれば良い。 For example, in the above embodiment, the cavities C are formed in the insulating layers 4 and 5, but the cavities C may be formed in the insulating layers 3 and 4 from the opposite direction. In this case, elements corresponding to the wiring pattern 31 located in the conductor layer L3 may be formed in the conductor layer L2.

１，２ 電子部品内蔵回路基板
１ａ 電子部品内蔵回路基板の上面
１ｂ 電子部品内蔵回路基板の下面
３～５，４ａ，４ｂ 絶縁層
１１～１４，２１～２３，３１～３３，４１～４３ 配線パターン
５０～５９ ビア導体
５０ａ～５９ａ 開口部
５０ｂ～５９ｂ ビア
６０，７０ 電子部品
６１，６２ 端子電極
７１，７２ ボンディングパッド
７３ ダイアタッチフィルム
７４ 導電性ペースト
８０ メッキ膜
ＢＷ１，ＢＷ２ ボンディングワイヤ
Ｃ キャビティ
Ｃａ 開口部
Ｌ１～Ｌ４ 導体層
Ｌ３ａ 導体層の表面
Ｐ メッキ
ＳＲ１，ＳＲ２ ソルダーレジスト 1, 2 Circuit board with built-in electronic components 1a Upper surface 1b of circuit board with built-in electronic components Lower surface 3-5, 4a, 4b of circuit board with built-in electronic components Insulating layers 11-14, 21-23, 31-33, 41-43 Wiring pattern 50-59 Via conductors 50a-59a Openings 50b-59b Vias 60, 70 Electronic components 61, 62 Terminal electrodes 71, 72 Bonding pad 73 Die attach film 74 Conductive paste 80 Plating film BW1, BW2 Bonding wire C Cavity Ca Opening L1 to L4 Conductor layer L3a Surface P of conductor layer Plating SR1, SR2 Solder resist

Claims (10)

第１の絶縁層と、
前記第１の絶縁層に埋め込まれた第１の電子部品と、
前記第１の絶縁層の一方の表面に設けられた第１の配線パターンと、
前記第１の絶縁層の他方の表面を覆う第２の絶縁層と、
前記第１の絶縁層の前記一方の表面を覆う第３の絶縁層と、
前記第２の絶縁層の前記第１の絶縁層とは反対側の表面に設けられた第２の配線パターンと、
前記第３の絶縁層の前記第１の絶縁層とは反対側の表面に設けられた第３の配線パターンと、を備え、
前記第１及び第２の絶縁層はキャビティを有し、前記キャビティの底面に前記第１の配線パターンの一部が露出しており、
前記キャビティの底面に露出する前記第１の配線パターンの前記一部は、前記第３の絶縁層を貫通し、前記キャビティと重なる位置に設けられたビア導体を介して前記第３の配線パターンに接続され、
前記第２の配線パターンは、前記キャビティの開口部の周囲において前記第２の絶縁層が露出しないよう、前記キャビティの前記開口部を取り囲むように設けられていることを特徴とする電子部品内蔵回路基板。 a first insulating layer;
a first electronic component embedded in the first insulating layer;
a first wiring pattern provided on one surface of the first insulating layer;
a second insulating layer covering the other surface of the first insulating layer;
a third insulating layer covering the one surface of the first insulating layer;
a second wiring pattern provided on a surface of the second insulating layer opposite to the first insulating layer;
a third wiring pattern provided on a surface of the third insulating layer opposite to the first insulating layer;
The first and second insulating layers have a cavity, and a part of the first wiring pattern is exposed at the bottom of the cavity,
The part of the first wiring pattern exposed on the bottom surface of the cavity penetrates the third insulating layer and connects to the third wiring pattern via a via conductor provided at a position overlapping with the cavity. connected,
The electronic component built-in circuit is characterized in that the second wiring pattern is provided so as to surround the opening of the cavity so that the second insulating layer is not exposed around the opening of the cavity. substrate. 前記第１の絶縁層は、前記第２の絶縁層よりも熱膨張係数が大きいことを特徴とする請求項１に記載の電子部品内蔵回路基板。 The electronic component built-in circuit board according to claim 1, wherein the first insulating layer has a larger coefficient of thermal expansion than the second insulating layer. 前記第１の配線パターンの前記一部の外周部は、前記キャビティの底面に露出することなく前記第１の絶縁層で覆われていることを特徴とする請求項１又は２に記載の電子部品内蔵回路基板。 The electronic component according to claim 1 or 2, wherein an outer peripheral portion of the part of the first wiring pattern is covered with the first insulating layer without being exposed to the bottom surface of the cavity. Built-in circuit board. 前記キャビティの内壁がメッキ膜で覆われていることを特徴とする請求項１乃至３のいずれか一項に記載の電子部品内蔵回路基板。 4. The circuit board with a built-in electronic component according to claim 1, wherein an inner wall of the cavity is covered with a plating film. 前記第１の絶縁層と前記第２の絶縁層の間に設けられた第４の配線パターンをさらに備え、
前記第４の配線パターンは、前記キャビティの内壁に露出していることを特徴とする請求項１乃至４のいずれか一項に記載の電子部品内蔵回路基板。 further comprising a fourth wiring pattern provided between the first insulating layer and the second insulating layer,
5. The circuit board with a built-in electronic component according to claim 1, wherein the fourth wiring pattern is exposed on an inner wall of the cavity. 前記キャビティに収容され、前記第１の電子部品よりも厚い第２の電子部品をさらに備えることを特徴とする請求項１乃至５のいずれか一項に記載の電子部品内蔵回路基板。 The circuit board with a built-in electronic component according to any one of claims 1 to 5 , further comprising a second electronic component that is housed in the cavity and is thicker than the first electronic component. 前記キャビティに収容され、前記第１の電子部品よりも厚い第２の電子部品と、
前記キャビティの内壁と前記第２の電子部品の間に充填された導電性ペーストと、をさらに備え、
前記導電性ペーストは、前記キャビティの内壁に露出する前記第４の配線パターンと接していることを特徴とする請求項５に記載の電子部品内蔵回路基板。 a second electronic component housed in the cavity and thicker than the first electronic component;
further comprising a conductive paste filled between the inner wall of the cavity and the second electronic component,
6. The electronic component built-in circuit board according to claim 5, wherein the conductive paste is in contact with the fourth wiring pattern exposed on the inner wall of the cavity. 一方の表面に第１の配線パターンが形成されるとともに、前記一方の表面が第３の絶縁層で覆われた第１の絶縁層に第１の電子部品を埋め込む第１の工程と、
前記第１の工程を行った後、前記第１の絶縁層の他方の表面に第２の絶縁層を形成する第２の工程と、
前記第３の絶縁層にビアを形成することにより、前記ビアの底部に前記第１の配線パターンの一部を前記第３の絶縁層側から露出させた後、前記ビアをビア導体で埋めることにより、前記第１の配線パターンの前記一部と、前記第３の絶縁層の前記第１の絶縁層とは反対側の表面に設けられた第３の配線パターンを、前記ビア導体によって接続する第３の工程と、
前記第１及び第２の絶縁層を貫通するキャビティを形成することにより、前記キャビティの底面に前記第１の配線パターンの前記一部を前記第１の絶縁層側から露出させる第４の工程と、を備え、
前記第２の絶縁層の前記第１の絶縁層とは反対側の表面に設けられた第２の配線パターンは、前記キャビティの開口部の周囲において前記第２の絶縁層が露出しないよう、前記キャビティの前記開口部を取り囲むように設けられていることを特徴とする電子部品内蔵回路基板の製造方法。 a first step of embedding a first electronic component in a first insulating layer in which a first wiring pattern is formed on one surface and the one surface is covered with a third insulating layer;
After performing the first step, a second step of forming a second insulating layer on the other surface of the first insulating layer;
forming a via in the third insulating layer to expose a part of the first wiring pattern at the bottom of the via from the third insulating layer side, and then filling the via with a via conductor; The part of the first wiring pattern and the third wiring pattern provided on the surface of the third insulating layer opposite to the first insulating layer are connected by the via conductor. The third step,
a fourth step of exposing the part of the first wiring pattern from the first insulating layer side on the bottom surface of the cavity by forming a cavity penetrating the first and second insulating layers ; , comprising;
A second wiring pattern provided on the surface of the second insulating layer opposite to the first insulating layer is configured to prevent the second insulating layer from being exposed around the opening of the cavity. A method of manufacturing a circuit board with a built-in electronic component, characterized in that the circuit board is provided so as to surround the opening of the cavity. 前記第４の工程は、前記第２の配線パターンをマスクとし、前記第１の配線パターンの前記一部をストッパーとして、前記第１及び第２の絶縁層の一部を除去することにより前記キャビティを形成することを特徴とする請求項８に記載の電子部品内蔵回路基板の製造方法。 In the fourth step, using the second wiring pattern as a mask and using the part of the first wiring pattern as a stopper, parts of the first and second insulating layers are removed to form the cavity. 9. The method of manufacturing a circuit board with a built-in electronic component according to claim 8 , further comprising forming a circuit board with a built-in electronic component. 前記キャビティに、前記第１の電子部品よりも厚い第２の電子部品を収容する第５の工程をさらに備えることを特徴とする請求項８又は９に記載の電子部品内蔵回路基板の製造方法。 10. The method of manufacturing a circuit board with a built-in electronic component according to claim 8, further comprising a fifth step of accommodating a second electronic component thicker than the first electronic component in the cavity.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011187830A (en) 2010-03-10 2011-09-22 Tdk Corp Substrate with built-in electronic component, and method of manufacturing the same
JP2011216740A (en) 2010-03-31 2011-10-27 Ibiden Co Ltd Wiring board and method for manufacturing wiring board
JP2014116548A (en) 2012-12-12 2014-06-26 Ngk Spark Plug Co Ltd Multilayer wiring board and manufacturing method therefor
JP2015133387A (en) 2014-01-10 2015-07-23 新光電気工業株式会社 Wiring board and manufacturing method of the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8963016B2 (en) * 2008-10-31 2015-02-24 Taiyo Yuden Co., Ltd. Printed wiring board and method for manufacturing same
TWI400998B (en) * 2010-08-20 2013-07-01 Nan Ya Printed Circuit Board Printed circuit board and method for fabricating the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011187830A (en) 2010-03-10 2011-09-22 Tdk Corp Substrate with built-in electronic component, and method of manufacturing the same
JP2011216740A (en) 2010-03-31 2011-10-27 Ibiden Co Ltd Wiring board and method for manufacturing wiring board
JP2014116548A (en) 2012-12-12 2014-06-26 Ngk Spark Plug Co Ltd Multilayer wiring board and manufacturing method therefor
JP2015133387A (en) 2014-01-10 2015-07-23 新光電気工業株式会社 Wiring board and manufacturing method of the same

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