九、 【發 【先 裝載 度化 化技 謂在 一體 接， 層。 體層 的對 時， 加工 相機 料取 畫像 層。 出其 另外 孔， 的技 200904267 發明說明： 明所屬之技術領域】 本發明係關於多層配線基板的製造方法。 前技術】 近年來，隨著電氣機器、電子機器等的小 於這些機器的配線基板等方面也被要求小 。爲了因應市場的需求，而正在硏討配線 術。作爲此配線基板之多層化的方法，一 核芯基板之正反兩面將樹脂絕緣層和導體 化，所謂的增層（build up)法。 在這種多層配線基板中，必須考慮到層間 並須對應下層的導體層而精度良好地層積 具體而言，在製造多層配線基板的時候， 的一部分上預先形成會成爲用於下一層之 位標記，在此導體層上形成下一層的樹脂 因爲對位標記係被覆蓋於樹脂絕緣層，所 而使此對位標記從樹脂絕緣層露出以後， 等的攝影手段來拍攝此對位標記。然後， 入於電腦並進行對位標記的畫像辨識，根 ’而在樹脂絕緣層上形成導通孔或形成下 如同這般，藉由雷射加工來露出對位標記 位置的技術係揭露於例如專利文獻1和專 ’在專利文獻3中揭露了以雷射加工使樹 藉以形成下層的導體層露出爲環狀之形態 術。 型化，而在 型化和高密 基板的多層 般是採用所 層交互層積 的電氣連 上層的導體 在下層之導 對位的基準 絕緣層。此 以藉由雷射 藉由CCD照 將此攝影資 據此辨識的 一層的導體 ，用於檢測 利文獻2。 脂絕緣層開 的對位標記 200904267 [專利文獻1]特開2003-60356號公報 [專利文獻2]特開平1 0-2567 37號公報 [專利文獻3]特開2005 -244 1 82號公報 【發明內容】 [本發明欲解決的課題] 不過，如同專利文獻1或專利文獻2藉由雷射加工來 使封位標記露出，或如问專利文獻3藉由雷射加工來形成 對位標記的情況下，因爲變得需要用於此雷射加工的步 驟，多層配線基板的製造成本增大。另外，若未適當設定 雷射的輸出時，均勻地切削對位標記上部之樹脂絕緣層並 進行開孔會很困難，就會發生由於雷射加工而切削到對位 標記本身，或者是樹脂絕緣層的一部分會殘留在此對位標 記上面的問題。因此，正硏討著在不使對位標記露出的狀 態下，介由樹脂絕緣層來讀取對位標記的手法。 具體而言，如第1 8圖所示，以覆蓋圓形之對位標記7 1 的方式而形成樹脂絕緣層72以後，從上方介由樹脂絕緣層 7 2而將位置檢測用光L 1照射於對位標記7 1。然後，根據 此位置檢測用光L 1的反射光L2來進行畫像辨識處理，並 檢測出對位標記7 1。不過，在對位標記7 1的上部，樹脂絕 緣層72的表面會因爲此對位標記71之厚度而上升，位置 檢測用光L 1會因爲其表面的凹凸而漫射。其結果，對位標 記7 1之輪廓變得不清楚，變得很難正確地進行畫像辨識。 在此情況下，因爲對位精度下降，所以在樹脂絕緣層72中 無法在與各導體層之導體電路對應的正確位置上形成導通 孔。因此，無法適當地進行層間的電氣連接，無法謀求導 200904267 體電路的細微化。 而且，因爲專利文獻1' 2會因爲焦點距離長而 度良好地形成對位標記。另外’專利文獻3因爲係 射加工而使對位標記露出，所以還是無法精度良好 對位標記。 本發明係有鑑於上述課題而完成者，其目的爲 種多層配線基板的製造方法，能確實地檢測出對位 將此對位標記作爲位置基準，並於與導體電路對應 位置上形成導通孔。 [解決課題的手段] 作爲用於解決上述課題的手段（手段1)，有一種 線基板的製造方法，該多層配線基板具備：核芯基 具有核芯主面；以及層積配線部，其係層積構成導 之金屬層以及層間樹脂絕緣層而成，且配置於前述 面上，該方法之特徵爲包含：導體電路等形成步驟 前述核芯主面上或者前述層間樹脂絕緣層上形成前 電路，同時在前述金屬層中與前述導體電路不同的 上’形成由第1光反射部與隔著移除圖案而包圍此 反射部的第2光反射部所組成之對位標記；絕緣層 驟’其在前述金屬層上形成覆蓋前述導體電路以及 位標記的前述層間樹脂絕緣層；檢測步驟，其根據 述層間樹脂絕緣層而照射於前述對位標記的位置檢 之反射光’來檢測出前述對位標記；以及雷射開孔 其使用測得之前述對位標記來作爲位置基準並進行 後’對BU述層間樹脂絕緣層照射雷射，並形成使前 無法精 藉由雷 t也形成 提供一 標記， 之正確 多層配 板，其 體電路 核芯主 ，其在 述導體 位置 第1光 形成步 前述對 介由前 測用光 步驟， 對位以 述導體 200904267 電路之一部分露出的導通孔。 因此，藉由手段1的多層配線基板之製造方法，在導 體電路等形成步驟中，在核芯主面上或者層間樹脂絕緣層 上形成導體電路，同時在金屬層中與導體電路不同的位置 上形成對位標記。在絕緣層形成步驟中，在金屬層上形成 層間樹脂絕緣層，並藉由此層間樹脂絕緣層來覆蓋導體電 路以及對位標記。本發明的對位標記係因爲由第1光反射 部與隔著既定寬度之移除圖案而包圍此第1光反射部的第 2光反射部所組成，所以相較於如同習知技術未在對位標 記之周圍形成金屬層圖案的情況，可抑制覆蓋對位標記的 層間樹脂絕緣層之表面的凹凸。因此，在檢測步驟中，會 抑制介由層間樹脂絕緣層而照射於對位標記的位置檢測用 光之漫射。因此，在第1光反射部和包圍此第1光反射部 的第2光反射部之表面上確實地反射位置檢測用光，根據 此反射光而正確地檢測出對位標記的位置。以此方式，在 雷射開孔步驟中，能在與導體電路對應之正確位置上形成 導通孔，能謀求多層配線基板的導體電路之細微化。 位於前述移除圖案之正上方的前述層間樹脂絕緣層之 表面高度、位於前述第1光反射部之正上方的前述層間樹 脂絕緣層之表面高度以及位於前述第2光反射部之正上方 的前述層間樹脂絕緣層之表面高度的不均能儘量小即可， 具體而言，例如5 # m以下爲佳，特別是3 y m以下爲較佳。 以此方式，因爲覆蓋對位標記的層間樹脂絕緣層之表面凹 凸變少，所以能夠確實地防止介由此層間樹脂絕緣層而照 射於對位標記的位置檢測用光之漫射。因此，能確實檢測 200904267 出對位標記的位置。 前述移除圖案的寬度並未被特別限定，但例如: 10#m以上即可，甚至較佳爲50//m以上、150//Π! 此移除圖案的寬度比50#m還要窄時，變得無法充 對位標記的辨識精度。另一方面，移除圖案的寬度 150#m還要寬時，層間樹脂絕緣層之表面高度不均 大。因此，藉由將移除圖案的寬度設爲50/zm以上、 以下，能確實檢測出對位標記的位置。該寬度更佳爲 * 以上、1 2 0 # m以下。 前述第1光反射部的形狀以及前述移除圖案的 未被特別限定，只要是可進行畫像辨識者，就能分 地進行選擇，但較佳爲例如，前述第1光反射部是_ 前述移除圖案同等寬度的環狀。在此情況下，能夠 形成對位標記。此外，因爲移除圖案爲同等寬度， 位標記之輪廓變得鮮明，能藉由畫像辨識來確實檢 位標記的位置。 另外，在前述檢測步驟中，在藉由使用電腦的 別處理來檢測出前述對位標記的情況下，前述位置 光的種類並未被限定，但使用波長比較長的紅色區 即可，特別是紅外光爲較佳。在此情況下，能夠藉 辨識處理來取得更鮮明的畫像。 在形成前述核芯基板的材料方面並未特別被限 考慮成本性、加工性、絕緣性、機器強度等而進行 擇。作爲核芯基板，例如，能舉出樹脂基板、陶瓷 金屬基板等。作爲樹脂基板的具體範例，有EP樹月丨 以下。 分確保 比 會變 1 5 0 〆 m 7 0 y m 形狀並 別任意 1形狀， 輕易地 所以對 測出對 畫像識 檢測用 域的光 由畫像 定，能 適當選 基板、 旨（環氧 -10- 200904267 樹脂）基板、PI樹脂（聚醯亞胺樹脂）基板、BT樹脂（雙馬來 醯亞胺-三阱樹脂）基板、PPE樹脂（聚苯醚樹脂）基板等。除 此之外’也可以使用由這些樹脂和玻璃纖維（玻璃織布和玻 璃不織布）或聚醯亞胺纖維等之有機纖維的複合材料所組 成的基板。或者，也可以使用將環氧樹脂等之熱硬化性樹 脂含浸於連續多孔質PTFE等之三維網目狀氟系樹脂基材 的樹脂-樹脂複合材料所組成之基板等。作爲前述陶瓷基 板的具體範例，則有例如由氧化鋁基板、氧化鈹基板、玻 f 璃陶瓷基板、結晶化玻璃等之低溫燒成材料所組成的基板 %, 等。作爲前述金屬基板的具體範例，則有例如，由銅基板 和銅合金基板、銅以外之金屬單體所組成的基板、銅以外 之金屬的合金所組成的基板等。此外，也可以在前述核芯 基板中形成貫通其上面及下面的複數個鍍通孔等，也可以 在那些複數個鍍通孔內塡入塡充材料。另外，上述核芯基 板可以是在其內部形成配線層的基板，也可以是埋入有晶 片電容器和晶片阻抗等之電子零件的基板。 , 構成前述導體電路的金屬層之形成手法，係能考慮導 1. 電性及與層間樹脂絕緣層的緊密性等而進行適當的選擇。 作爲金屬層的材料範例，能舉出銅、銅合金、鎳、鎳合金、 錫、錫合金等。另外，能以減成法（s u b t r a c t i v e)、半加成法 (semi-additive)、全加成法（full-additive)等之習知的手法來 形成該金屬層。具體而言，能夠採用例如銅箔之飩刻、無 電解鍍銅或者電解鍍銅、無電解鎪鎳或者電解鍍鎳等的手 法。此外，可由濺鍍或CVD等之手法形成金屬層以後進行 蝕刻以形成導體電路，或藉由印刷導電性糊漿等來形成導 200904267 體電路。 前述層間樹脂絕緣層係例如採用具有熱硬化性的樹脂 而形成。作爲熱硬化性樹脂的適當例，則列舉出了 EP樹脂 (環氧樹脂）、PI樹脂（聚醯亞胺樹脂）、BT樹脂（雙馬來醯亞 胺-三阱樹脂）、苯酚樹脂、二甲苯樹脂、聚脂樹脂、矽樹 脂等。即使在這些當中，較佳爲選擇EP樹脂（環氧樹脂）、 PI樹脂（聚醯亞胺樹脂）、BT樹脂（雙馬來醯亞胺·三畊樹 脂）。例如，作爲環氧樹脂，使用所謂的BP(雙酚）型、PN(苯 ^ 酚酚醛清漆）型、CN(甲酚酚醛清漆）型者即可。特別是，以 BP(雙酚）型爲主體者即可，BPA(雙酚A)型和BPF(雙酚F) 型爲最佳。 在此，多層配線基板爲具有至少一個以上之製品區域 以及包圍前述製品區域之框部區域的情況下，前述對位標 記並非形成於製品區域，還是形成於框部區域爲較佳。製 品區域內緊密聚集著多數的導體電路或通孔導體，欲在其 中設置對位標記時就會阻礙製品全體的小型化。相對於 f 此，因爲若是最後不會成爲製品的框部區域，即使在其上 設置對位標記也不會特別阻礙到製品的小型化，另外，形 成對位標記時的配置之自由度也很大。 【實施方式】 以下，根據圖式來詳細說明將本發明具體化之多層配 線基板的一實施形態。第1圖係多層配線基板的槪略平面 圖，第2圖係多層配線基板的截面圖。 如第1圖所示，多層配線基板1 1由平面觀看呈現矩形 狀，且具有複數（在此爲4x4個）個製品區域100，及包圍那 -12- 200904267 些製品區域1 00的框部區域1 〇 1。因爲框部區域1 0 1不會成 爲製品，所以在最後會經過切割步驟而被切除。 如第2圖所示，構成多層配線基板1 1的核芯基板1 2 係由玻璃環氧所組成的略矩形板狀之構件（厚度〇.8mm)’並 具有作爲核芯主面的上面13以及下面14。核芯基板12的 上面13形成有第1增層式（build up)層15 (層積配線部）’核 芯基板12的下面14形成有第2增層式層16(層積配線部）。 在核芯基板12的製品區域100之既定處，係形成有使上面 1 3以及下面1 4連通的多數個鍍通孔1 7。在位於鍍通孔1 7 內的空洞部中，則塡充有由加入銅塡充物之環氧樹脂所組 成的塡充材料18。另外，在核芯基板12的上面13以及下 面1 4係形成有由銅所組成之導體層1 9，各導體層1 9係電 氣連接於鍍通孔1 7 » 在核芯基板12之上面13上形成的第1增層式層15係 具有由環氧樹脂組成之樹脂絕緣層20、2 1 (層間樹脂絕緣層） 及由銅組成之導體層22、23 (金屬層）以各2層層積的構造。 在本實施形態中，各樹脂絕緣層20、21的厚度是40/zm左 右，各導體層22、23的厚度是20/zm左右。 在第2層樹脂絕緣層21的表面上的複數處，構成導體 層23之導體電路的端子襯墊230係形成爲陣列狀。第1層 樹脂絕緣層20內設有複數個導通孔25以及通孔導體26 ’ 第2層樹脂絕緣層2 1內設有複數個導通孔27以及通孔導 體28。介由這些通孔導體26、28’導體層19、22之導體 電路190、220以及端子襯墊230會相互地電氣連接。另外’ 第2層樹脂絕緣層2 1的表面係被防焊部29所大致全體地 -13- 200904267 覆蓋。在防焊部29的既定處，形成使端子襯墊23〇露出的 開口部30。各端子襯墊230係介由未圖示之焊料凸塊而電 氣連接於1C晶片（半導體積體電路元件）的連接端子。 在核芯基板12之下面14上形成的第2增層式層16係 具有和上述第1增層式層15大致相同的構造。亦即，第2 增層式層1 6係具有由環氧樹脂組成之樹脂絕緣層3丨、3 2 及由銅組成之導體層33、34以各2層層積的構造。在第2 層樹脂絕緣層32之下面上的複數處，構成導體層34之導 體電路的BGA用襯墊340係形成爲陣列狀。第1層樹脂絕 緣層31內設有複數個導通孔25以及通孔導體26，第2層 樹脂絕緣層32內設有複數個導通孔27以及通孔導體28。 介由這些通孔導體26、28’導體層19、33之導體電路190、 3 30以及BGA用襯墊340會相互地電氣連接。另外，第2 層樹脂絕緣層3 2的下面係被防焊部3 6所大致全體地覆 蓋。在防焊部36的既定處，形成使BGA用襯墊340露出 的開口部37。BGA用襯墊340的表面上係配設有複數個焊 料凸塊38，用以謀求和未圖示之主板（mother board)進行電 氣連接，藉由各焊料凸塊38,多層配線基板11會被組裝於 未圖本之主板上。 另外，如第1圖以及第2圖所示，在多層配線基板1 1 的框部區域101之既定位置（成爲基板之四個角隅的位置） 中，在核芯基板1 2以及樹脂絕緣層20、3 1上設置對位標 記4 1、4 2。此外，在本實施形態中，對位標記4 1與對位標 記42係被配置於在樹脂絕緣層20、31之厚度方向上重疊 的位置。使用在核芯基板1 2上形成的對位標記4 1，來作爲 -14- 200904267 用以在第1層樹脂絕緣層20、3 1上形成導通孔25的位置 基準。另外，使用在樹脂絕緣層20、3 1上形成的對位標記 42 ’來作爲用以在第2層樹脂絕緣層2 1、32上形成導通孔 27的位置基準。 如第3圖所示，對位標記41係由第1光反射部43及 隔著既定寬度之移除圖案44而包圍此第1光反射部43的 第2光反射部45所組成。在本實施形態中，第1光反射部 43係形成爲具有例如lmm之直徑的圓形狀，移除圖案44 係形成爲同等寬度（100/zm的寬度）的環狀》這些第1光反 射部43和移除圖案44係被配置於同心圓上。此外，對位 標記42也一樣，係由圓形狀之第1光反射部43及隔著環 狀之移除圖案44而包圍此第1光反射部43的第2光反射 部4 5所組成。 在以此方式形成對位標記4 1、42的情況下，覆蓋此對 位標記41、42的樹脂絕緣層20、21、31、32之表面的平 坦度會提升。具體而言，對位標記4 1之位於移除圖案44 正上方的樹脂絕緣層20之表面的高度H1、位於第1光反 射部43正上方的樹脂絕緣層20之表面的高度H2以及位於 第2光反射部45正上方的樹脂絕緣層20之表面的高度H3 的不均係5/zm以下（在本實施形態中爲2/zm〜3/zm左 右）（參照第4圖）。 接著，就上述構成之多層配線基板1 1的製造順序來進 行說明。 首先，在基板準備步驟中，準備了將銅箔47貼附於核 芯基板12之兩面而得的兩面覆銅層積板48 (參照第5圖）。 200904267 然後，使用YAG雷射或者碳酸氣體雷射來進行雷射開孔加 工’在既定位置上預先形成貫通兩面覆銅層積板48的貫通 孔。然後，藉由以往習知的手法來進行無電解鍍銅以及電 解鍍銅來形成鍍通孔1 7以後，在此鍍通孔1 7內塡入塡充 材1 8並使之熱硬化。 在導體電路等形成步驟中，進行基板兩面之銅箱47的 蝕刻，藉以在核芯基板12上圖案化導體層19(導體電路 1 9 0)。具體而言’無電解鍍銅以後，進行曝光以及顯影來 形成既定圖案的抗鍍層。在此狀態下以無電解鍍銅層作爲 共同電極而施行電解鍍銅以後，首先溶解並除去抗鍍層， 進一步以蝕刻來除去不需要的無電解鍍銅層。其結果，在 核芯基板12之製品區域100上形成既定圖案的導體層 19(導體電路190)，並且在框部區域101之既定位置（成爲 四角隅的位置）上形成對位標記4 1 (參照第6圖）。 在絕緣層形成步驟中，在核芯基板12的上面13以及 下面1 4，以分別將由環氧樹脂作爲主要成分之膜狀絕緣樹 脂材料重合的方式來進行配置。然後，利用真空壓接熱壓 力機（未圖示）於真空下對這種層積物進行加壓加熱，藉以 使膜狀絕緣樹脂材料硬化，並在上面13以及下面14各自 形成第1層樹脂絕緣層20、3 1 (參照第7圖）。此時’從膜 狀絕緣樹脂材料滲出的環氧樹脂下降而被塡充於對位標記 41之移除圖案44，但因爲移除圖案44之縫隙只有1〇〇从m 那麼狹窄，所以幾乎不會發生因樹脂對移除圖案44塡充而 造成樹脂絕緣層20、31的厚度不均。 在檢測步驟中，使用環狀的照射器5 1 ’介由樹脂絕緣 -16 - 200904267 層20來向對位標記4 1照射紅外光L 1 (位置檢測用光），根 據其反射光L2來檢測出對位標記4 1 (參照第8圖）。具體而 言，根據來自對位標記41(第1光反射部43以及第2光反 射部45)的反射光L2’藉由CCD照相機52來拍攝此對位標 記41的像。然後，將此CCd照相機52的攝影資料取入至 電腦5 3並進行畫像辨識處理，根據此辨識之畫像來檢測出 對位標記4 1的位置。此外，在此畫像辨識處理中，對拍攝 到的畫像進行二値化處理，根據此處理後的畫像資料來檢 測出對位標記4 1的位置。 在雷射開孔步驟中，使用測得的對位標記4 1來作爲位 置基準，進行雷射照射裝置5 4的對位以後，將雷射L0照 射於核芯基板12之上面13的樹脂絕緣層20(參照第9圖）。 此外，使用碳酸氣體雷射器和YAG雷射等的照射裝置來作 爲雷射照射裝置54。藉由此雷射照射，在樹脂絕緣層20 之既定位置上形成導通孔25，露出導體層19之導體電路 190的一部分。另外，在核芯基板12之下面14的樹脂絕緣 層3 1也同樣地在檢測步驟中檢測出對位標記4 1的位置， 在雷射開孔步驟中照射雷射L0，藉以在既定位置形成導通 孔25。 然後，藉由進行無電解鍍銅，在導通孔25內形成通孔 導體26,同時在樹脂絕緣層20之上面全體形成無電解鍍銅 層。爾後，進行曝光以及顯影來形成既定圖案的抗鍍層。 然後，施行電解鍍銅以後，首先溶解並除去抗鍍層，進一 步以蝕刻來除去不需要的無電解鍍銅層。其結果，在樹脂 絕緣層20、31上之製品區域1〇〇中形成既定圖案的導體層 -17- 200904267 2 2、3 3 (導體電路2 2 0、3 3 0)，同時在框部區域1 0 1形成對 位標記42(參照第1〇圖）。 接著，與上述第1層樹脂絕緣層2 0、3 1的情況相同， 藉由進行絕緣層形成步驟，來形成第2層樹脂絕緣層2 1、 3 2。此外，在檢測步驟中檢測出對位標記4 2的位置，由雷 射開孔步驟而照射雷射L0，藉以在樹脂絕緣層2 1、3 2之 既定位置形成導通孔27 (參照第11圖）。 然後，藉由進行無電解鍍銅，在導通孔27內形成通孔 導體28,同時在樹脂絕緣層21、32之上面全體形成無電解 鍍銅層。爾後，進行曝光以及顯影來形成既定圖案的抗鍍 層。然後，施行電解鍍銅之後，首先溶解並除去抗鍍層， 進一步以蝕刻來除去不需要的無電解鍍銅層。其結果，在 樹脂絕緣層21上之既定位置形成複數個端子襯墊230，同 時在樹脂絕緣層32上之既定位置形成複數個BGA用襯墊 340(參照第12圖）。 此外，在如同上述而形成的核芯基板12之上面以及下 面的表面上塗佈感光性液態樹脂材料並使之硬化，藉以形 成防焊部2 9、3 6。接著，以使玻璃遮罩在防焊部2 9、3 6 的表面上重合的方式來進行配置，進行曝光以及顯影，在 防焊部2 9、3 6上圖案化開口部3 0、3 7 (參照第1 3圖）。 然後’對從各開口部30露出之端子襯墊230或從各開 口部37露出之BGA用襯墊3 40,進行表面粗化處理以及進 行鎳-金電鍍處理。爾後，利用習知的手法來進行焊料凸塊 形成步驟’在BGA用襯墊340的表面上形成焊料凸塊38(參 照第2圖）°具體而言’在防焊部36上載置既定圖案的遮 -18- 200904267 罩，在BGA用襯墊340上印刷焊料糊漿以後，將此焊料糊 漿進行回焊（reflow)。爾後，將以一大張的狀態而一體化的 中間製品，使用切割刀具等的切斷器具而切割分離成各個 小片，藉以完成多層配線基板。 爲了確認本實施形態之製造方法的效果，而測定了核 芯基板12上之導通孔25相對於導體電路190 (襯墊）的位置 精度。第14圖係表示其測定結果56。此外，在此係表示導 通孔25之中心座標相對於襯墊之中心座標的偏移量（錯位 ^ 量）。另外，作爲比較例，如同習知技術，於第15圖表示 使用圓形之對位標記71(直徑爲1mm之尺寸的標記）而形成 導通孔25時的位置精度之測定結果58。如第14圖以及第 1 5圖所示，在本實施形態中，相較於習知技術的比較例， 錯位量的不均減小，並精度良好地形成導通孔25。 第1 6圖係表示在本實施形態中，於檢測步驟所拍攝之 對位標記4 1的畫像6 1，第1 7圖係表示比較例之對位標記 71的畫像6 2。如第16圖所示，在本實施形態中，因爲能 取得對位標記4 1之輪廓爲鮮明的畫像6 1，所以畫像辨識之 對位標記4 1的識別度變得良好。其結果，更正確地檢測出 對位標記4 1的位置，雷射加工之導通孔25的加工精度會 提升。 另外，本案發明人係在上述檢測步驟中，將照射的位 置檢測用光L 1自紅外光換成紅色光（可見光），而拍攝了對 位標記4 1的畫像（圖示省略）。在此情況下，因爲對位標記 4 1的輪廓變得不清楚，所以相較於使用紅外光的情況，其 畫像辨識是困難的。此外，本案發明人將對位標記4 1的移 -19· 200904267 除圖案44之縫隙從100 μ m變更爲200 // m，並拍攝了此對 位標記4 1的畫像（圖示省略）。在此情況下，在絕緣層形成 步驟中，藉由將環氧樹脂塡充於移除圖案44，覆蓋對位標 記41的樹脂絕緣層20、31之表面的高度不均會變大。因 此，對位標記4 1之輪廓不清楚，其辨識精度會惡化。 因此，能藉由本實施形態而獲得以下的效果。 (1) 在本實施形態中，對位標記4 1、42係由第1光反 射部43及隔著移除圖案44而包圍此第1光反射部43的第 2光反射部4 5所組成，所以相較於如同習知技術未在對位 標記7 1之周圍形成導體層的情況（參照第1 8圖），可抑制覆 蓋對位標記41、42的樹脂絕緣層20、21、31、32之表面 的凹凸。因此，在檢測步驟中，能夠抑制介由樹脂絕緣層 20、21、31、32而照射於對位標記41、42的位置檢測用光 L1之漫射。因此，位置檢測用光L1會在第1光反射部4 3 以及第2光反射部4 5的表面上被確實地反射’能根據此反 射光L2而正確地檢測出對位標記4 1、4 2的位置。以此方 式，能在與導體層19、22、33之導體電路190、220、330 對應之正確位置上形成導通孔25、27，能謀求多層配線基 板11之導體電路190、220、3 30的細微化。 (2) 本實施形態的情況下，因爲對位標記4 1、42之移 除圖案44的寬度爲1 00 v m，所以能減少覆蓋此對位標記 41、42的樹脂絕緣層20、21、31、32之表面的凹凸’能夠 提升畫像識別的對位標記4 1、42之識別精度。 (3) 本實施形態的情況下，因爲對位標記4 1、42之第 1光反射部4 3爲圓形狀，移除圖案4 4爲環狀，所以能輕易 -20- 200904267 地形成對位標記4 1、4 2。此外，因爲移除圖案4 4是同等寬 度，所以對位標記4 1、42的輪廓變得鮮明，能藉由畫像辨 識來確實檢測出對位標記4 1、4 2的位置。 (4) 本實施形態的情況下，在檢測步驟中，因爲使用 紅外光來作爲位置檢測用光，所以能藉由畫像辨識來取得 更鮮明的畫像6 1，因而能確實檢測出對位標記4 1、42的位 置。 (5) 本實施形態的情況下，對位標記41、42並非形成 於製品區域1 00，而是形成於包圍此製品區域1 00的框部區 域101。在多層配線基板1 1中，多數導體電路190、220 ' 3 30或通孔導體26、28會緊密聚集於製品區域1〇〇內’欲 在此設置對位標記4 1、42時，會阻礙製品全體的小型化。 相對於此，如同本實施形態，藉由在最後不會成爲製品的 框部區域1 0 1上設置對位標記4 1、42，能謀求製品的小型 化。另外，形成對位標記41、42時的配置之自由度也變大， 成爲實用上較理想者。 此外，本發明之實施形態亦可如同以下進行變更。 •上述實施形態的多層配線基板11係由樹脂材料組成 核芯基板1 2的有機型多層配線基板，但也可以將本發明應 用於由陶瓷材料或金屬材料所組成的多層配線基板。 •在上述實施形態的絕緣層形成步驟中，是使用膜狀 絕緣樹脂材料來形成樹脂絕緣層20、2 1、3 1、3 2者，但除 此之外’也可以藉由進行液態防焊部的塗佈以及乾燥，以 形成樹脂絕緣層2 0、2 1、3 1、3 2。 •上述實施形態的對位標記4卜42係第1光反射部43 -21 - 200904267 爲圓形狀’移除圖案44爲環狀，但並非侷限於此，也可以 變更爲例如四角形狀、三角形狀的第1光反射部43或移除 圖案44。另外，在對位標記41與對位標記42方面，也可 以使那些形狀或尺寸有所差異。此外，在上述實施形態中， 對位標記4 1與對位標記42係形成於在樹脂絕緣層20、3 1 之厚度方向上重疊的位置，但也可以形成爲偏離此位置。 •上述實施形態中，多層配線基板1 1的封裝形態是 BGA(球閘陣列封裝），但並非僅侷限於BGA，也可以是例如 PGA(插針網格陣歹[J )或LGA(平面閘格陣歹!J )等。 接著，除了申請專利範圍所記載之技術思想以外，以 下則列舉由前述實施形態所掌握之技術思想。 【圖式簡單說明】 第1圖係表示將本發明具體化的一實施形態之多層配 線基板的槪略平面圖。 第2圖係表示將本發明具體化的一實施形態之多層配 線基板的主要部分截面圖。 第3圖係表示一實施形態的對位標記之平面圖。 第4圖係表示覆蓋對位標記的樹脂絕緣層表面之高度 不均的截面圖。 第5圖係用於說明一實施形態之多層配線基板的製造 方法的截面圖。 第6圖係用於說明一實施形態之多層配線基板的製造 方法的截面圖。 第7圖係用於說明一實施形態之多層配線基板的製造 方法的截面圖。 -22- 200904267 第8圖係用於說明一實施形態之多層配線基板的製造 方法的截面圖。 第9圖係用於說明一實施形態之多層配線基板的製造 方法的截面圖。 第1 0圖係用於說明一實施形態之多層配線基板的製 造方法的截面圖。 第1 1圖係用於說明一實施形態之多層配線基板的製 造方法的截面圖。 r . 第1 2圖係用於說明一實施形態之多層配線基板的製 造方法的截面圖。 第1 3圖係用於說明一實施形態之多層配線基板的製 造方法的截面圖。 第1 4圖係表示一實施形態的對位精度之測定結果的 說明圖。 第1 5圖係表示比較例的對位精度之測定結果的說明 圖。 第1 6圖係表示於一實施形態的對位標記之畫像的說 ' 明圖。 第1 7圖係表示於比較例的對位標記之畫像的說明圖 第1 8圖係表示以往覆蓋對位標記的樹脂絕緣層表面 之高度不均的截面圖。 【主要元件符號說明】 11 多層配線基板 12 核芯基板 13 作爲核芯主面的上面 23- 200904267 14 作爲核芯主面的下面 15、16 作爲層積配線部的增層式層 19 、 22 、 23 、 33 、 34 作爲金屬層的導體層 20 ' 21 ' 31、32 作爲層間樹脂絕緣層的樹脂 絕緣層 41 ' 4 2 對位標記 43 第1光反射部 44 移除圖案 45 第2光反射部 190 、 220 、 330 導體電路 L0 雷射 LI 位置檢測用光 L2 反射光 HI、H2、H3 層間樹脂絕緣層的表面高度 24-Nine, [fat [first load degree technology is said to be integrated in one layer. When the body layer is right, the processing camera takes the image layer. TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of manufacturing a multilayer wiring substrate. In the past, in recent years, wiring boards such as electric machines and electronic devices that are smaller than these devices have been required to be small. In order to meet the needs of the market, we are begging for wiring. As a method of multilayering the wiring substrate, a resin insulating layer and a conductor are formed on both sides of a core substrate, and a so-called build up method is used. In such a multilayer wiring board, it is necessary to accurately laminate the layers in order to correspond to the conductor layers of the lower layer. Specifically, when a multilayer wiring board is manufactured, a part of it is formed in advance to become a mark for the next layer. The resin of the next layer is formed on the conductor layer because the alignment mark is covered with the resin insulating layer, and the alignment mark is exposed from the resin insulating layer, and the like is photographed by the photographing means. Then, the image recognition of the alignment mark is carried out on the computer, and the root is formed on the resin insulating layer to form a via hole or the like. The technique for exposing the position of the alignment mark by laser processing is disclosed, for example, in the patent. Document 1 and "Special" in Patent Document 3 disclose a morphology in which a conductor layer by which a tree is formed by laser processing to form a lower layer is exposed. The patterning, and the multilayering of the patterned and high-density substrate is the reference insulating layer using the layers of the electrically connected layers of the layers that are alternately laminated in the lower layer. This is used to detect the conductor of the layer which is identified by the laser by the CCD. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 [Problem to be Solved by the Invention] However, as in Patent Document 1 or Patent Document 2, the seal mark is exposed by laser processing, or the alignment mark is formed by laser processing as in Patent Document 3. In this case, since the steps for this laser processing are required, the manufacturing cost of the multilayer wiring substrate is increased. In addition, if the output of the laser is not properly set, it is difficult to uniformly cut the resin insulating layer on the upper portion of the alignment mark and perform the opening, and the alignment mark itself or the resin insulation may occur due to laser processing. A part of the layer will remain in the problem above this alignment mark. Therefore, the method of reading the alignment mark via the resin insulating layer without exposing the alignment mark is being sought. Specifically, as shown in FIG. 18, the resin insulating layer 72 is formed so as to cover the circular alignment mark 7 1 , and then the position detecting light L 1 is irradiated from above through the resin insulating layer 7 2 . In the alignment mark 7 1. Then, image recognition processing is performed based on the reflected light L2 of the position detecting light L1, and the registration mark 71 is detected. However, in the upper portion of the alignment mark 71, the surface of the resin insulating layer 72 rises due to the thickness of the alignment mark 71, and the position detecting light L1 is diffused by the unevenness of the surface. As a result, the outline of the alignment mark 71 becomes unclear, and it becomes difficult to accurately recognize the image. In this case, since the alignment accuracy is lowered, the via holes cannot be formed in the resin insulating layer 72 at the correct positions corresponding to the conductor circuits of the respective conductor layers. Therefore, the electrical connection between the layers cannot be properly performed, and the circuit of the 200904267 body circuit cannot be made fine. Moreover, since Patent Document 1'2, the alignment mark is formed favorably because the focal length is long. Further, in Patent Document 3, since the alignment mark is exposed by the laser processing, the alignment mark is not accurate. The present invention has been made in view of the above problems, and an object of the invention is to provide a method for manufacturing a multilayer wiring board, which can reliably detect the alignment using the alignment mark as a position reference and form a via hole at a position corresponding to the conductor circuit. [Means for Solving the Problem] As a means for solving the above-described problems (means 1), there is a method of manufacturing a wire substrate comprising: a core base having a core main surface; and a laminated wiring portion The laminated metal layer and the interlayer resin insulating layer are formed on the surface, and the method is characterized in that: the conductor circuit or the like forming step forms a front circuit on the core main surface or the interlayer resin insulating layer At the same time, in the metal layer, the upper portion of the metal layer different from the conductor circuit is formed with an alignment mark composed of the first light reflection portion and the second light reflection portion surrounding the reflection portion via the removal pattern; the insulating layer is ' Forming the interlayer resin insulating layer covering the conductor circuit and the bit mark on the metal layer; and detecting a step of detecting the reflected light by irradiating the position of the alignment mark with the interlayer resin insulating layer a bit mark; and a laser opening which uses the aforementioned alignment mark as a position reference and performs a subsequent irradiation of the inter-layer resin insulating layer on the BU And forming a correct multi-layered board that enables the former to be finely formed by providing a mark, the body circuit core of which is the first light forming step in the conductor position, and the step of pre-measuring light is used. A via hole that is partially exposed by one of the conductors of the conductor 200904267. Therefore, in the method of manufacturing a multilayer wiring substrate of the means 1, in the step of forming a conductor circuit or the like, a conductor circuit is formed on the core main surface or the interlayer resin insulating layer while being different from the conductor circuit in the metal layer. Form a registration mark. In the insulating layer forming step, an interlayer resin insulating layer is formed on the metal layer, and the conductor circuit and the alignment mark are covered by the interlayer resin insulating layer. Since the alignment mark of the present invention is composed of the first light reflection portion and the second light reflection portion that surrounds the first light reflection portion with a removal pattern of a predetermined width, it is not compared with the conventional technique. When the metal layer pattern is formed around the alignment mark, irregularities on the surface of the interlayer resin insulating layer covering the alignment mark can be suppressed. Therefore, in the detecting step, the diffusion of the position detecting light irradiated to the alignment mark via the interlayer resin insulating layer is suppressed. Therefore, the position detecting light is reliably reflected on the surface of the first light reflecting portion and the second light reflecting portion surrounding the first light reflecting portion, and the position of the alignment mark is accurately detected based on the reflected light. In this manner, in the laser opening step, the via hole can be formed at the correct position corresponding to the conductor circuit, and the conductor circuit of the multilayer wiring board can be made finer. a surface height of the interlayer resin insulating layer located directly above the removal pattern, a surface height of the interlayer resin insulating layer directly above the first light reflecting portion, and the foregoing directly above the second light reflecting portion The unevenness of the surface height of the interlayer resin insulating layer can be as small as possible. Specifically, for example, 5 # m or less is preferable, and particularly preferably 3 μm or less. In this manner, since the surface unevenness of the interlayer resin insulating layer covering the alignment mark is small, the diffusion of the position detecting light irradiated to the alignment mark by the interlayer resin insulating layer can be surely prevented. Therefore, it is possible to reliably detect the position of the registration mark in 200904267. The width of the aforementioned removal pattern is not particularly limited, but for example: 10#m or more, even more preferably 50//m or more, 150//Π! The width of the removal pattern is narrower than 50#m. At this time, it becomes impossible to charge the identification accuracy of the alignment mark. On the other hand, when the width of the removed pattern 150#m is wider, the surface of the interlayer resin insulating layer is not uniform in height. Therefore, by setting the width of the removal pattern to 50/zm or more, the position of the alignment mark can be surely detected. The width is more preferably * or more and 1 2 0 # m or less. The shape of the first light reflecting portion and the removal pattern are not particularly limited, and may be selected separately if the image is identifiable. For example, the first light reflecting portion is preferably _ In addition to the ring of the same width of the pattern. In this case, a registration mark can be formed. In addition, since the removed pattern has the same width, the outline of the bit mark becomes sharp, and the position of the mark can be surely detected by the image recognition. Further, in the detecting step, when the alignment mark is detected by another processing using a computer, the type of the position light is not limited, but a red area having a relatively long wavelength may be used, in particular Infrared light is preferred. In this case, it is possible to obtain a more vivid portrait by the identification processing. The material for forming the core substrate is not particularly limited in consideration of cost, workability, insulation, machine strength, and the like. Examples of the core substrate include a resin substrate, a ceramic metal substrate, and the like. As a specific example of the resin substrate, there is an EP tree. In the case of the image, the image is determined by the image, and the substrate can be appropriately selected (epoxy-10-). 200904267 Resin) substrate, PI resin (polyimide resin) substrate, BT resin (bismaleimide-tripper resin) substrate, PPE resin (polyphenylene ether resin) substrate, and the like. In addition to this, a substrate composed of a composite material of these resins and glass fibers (glass woven fabric and glass nonwoven fabric) or organic fibers such as polyimide fibers can also be used. Alternatively, a substrate composed of a resin-resin composite material in which a thermosetting resin such as an epoxy resin is impregnated into a three-dimensional mesh-like fluorine resin substrate such as continuous porous PTFE may be used. Specific examples of the ceramic substrate include, for example, a substrate % composed of a low-temperature firing material such as an alumina substrate, a cerium oxide substrate, a glass ceramic substrate, or a crystallized glass. Specific examples of the metal substrate include a substrate composed of a copper substrate, a copper alloy substrate, a metal monomer other than copper, and an alloy of a metal other than copper. Further, a plurality of plated through holes penetrating the upper surface and the lower surface of the core substrate may be formed, or a plurality of plated through holes may be inserted into the plurality of plated through holes. Further, the core substrate may be a substrate in which a wiring layer is formed, or may be a substrate in which electronic components such as a wafer capacitor and a wafer impedance are embedded. The method of forming the metal layer constituting the conductor circuit can be appropriately selected in consideration of conductivity, tightness with the interlayer resin insulating layer, and the like. Examples of the material of the metal layer include copper, a copper alloy, nickel, a nickel alloy, tin, a tin alloy, and the like. Further, the metal layer can be formed by a conventional method such as a subtractive method (s u b t r a c t i v e), a semi-additive method, or a full-additive method. Specifically, for example, etching of copper foil, electroless copper plating or electrolytic copper plating, electroless nickel plating or electrolytic nickel plating can be employed. Further, the metal layer may be formed by sputtering or CVD or the like to be etched to form a conductor circuit, or a conductive paste or the like may be printed to form a conductor circuit. The interlayer resin insulating layer is formed, for example, by using a resin having thermosetting properties. Examples of suitable examples of the thermosetting resin include an EP resin (epoxy resin), a PI resin (polyimine resin), a BT resin (bismaleimide-tripper resin), a phenol resin, and two Toluene resin, polyester resin, enamel resin, and the like. Among these, it is preferred to select an EP resin (epoxy resin), a PI resin (polyimine resin), and a BT resin (bismaleimide·three tillage resin). For example, as the epoxy resin, a so-called BP (bisphenol) type, a PN (phenol novolac) type, and a CN (cresol novolac) type may be used. In particular, the BP (bisphenol) type is preferred, and the BPA (bisphenol A) type and the BPF (bisphenol F) type are preferred. Here, in the case where the multilayer wiring board has at least one product region and a frame portion surrounding the product region, it is preferable that the alignment mark is formed not in the product region or in the frame region. A large number of conductor circuits or via conductors are closely packed in the product area, and the placement of the alignment marks therein hinders the miniaturization of the entire product. With respect to f, since the frame portion of the product is not finally formed, even if the alignment mark is provided thereon, the size of the product is not particularly hindered, and the degree of freedom in the arrangement of the alignment mark is also very high. Big. [Embodiment] Hereinafter, an embodiment of a multilayer wiring board embodying the present invention will be described in detail based on the drawings. Fig. 1 is a schematic plan view of a multilayer wiring board, and Fig. 2 is a cross-sectional view of a multilayer wiring board. As shown in Fig. 1, the multilayer wiring substrate 11 has a rectangular shape when viewed in plan, and has a plurality of (here, 4x4) product regions 100, and a frame region surrounding the product regions 100 of -12-200904267. 1 〇1. Since the frame portion 1 0 1 does not become an article, it is cut off at the end by a cutting step. As shown in Fig. 2, the core substrate 12 constituting the multilayer wiring board 1 1 is a substantially rectangular plate-like member (thickness 〇 8 mm) composed of glass epoxy and has an upper surface as a core main surface 13 And 14 below. The first build-up layer 15 (layered wiring portion) is formed on the upper surface 13 of the core substrate 12. The second build-up layer 16 (layered wiring portion) is formed on the lower surface 14 of the core substrate 12. At a predetermined portion of the product region 100 of the core substrate 12, a plurality of plated through holes 17 that connect the upper surface 13 and the lower surface 14 are formed. In the cavity portion in the plated through hole 17 is filled with a squeezing material 18 composed of an epoxy resin to which a copper ruthenium is added. Further, on the upper surface 13 and the lower surface 14 of the core substrate 12, a conductor layer 19 composed of copper is formed, and each conductor layer 19 is electrically connected to the plated through hole 1 7 » on the upper surface of the core substrate 12 The first build-up layer 15 formed thereon has a resin insulating layer 20, 2 1 (interlayer resin insulating layer) composed of an epoxy resin, and conductor layers 22, 23 (metal layers) composed of copper in two layers. The structure of the product. In the present embodiment, the thickness of each of the resin insulating layers 20 and 21 is about 40/zm, and the thickness of each of the conductor layers 22 and 23 is about 20/zm. The terminal pads 230 constituting the conductor circuits of the conductor layer 23 are formed in an array at a plurality of points on the surface of the second resin insulating layer 21. The first resin insulating layer 20 is provided with a plurality of via holes 25 and via conductors 26'. The second resin insulating layer 2 1 is provided with a plurality of via holes 27 and via conductors 28. The conductor circuits 190, 220 and the terminal pads 230 via the via conductors 26, 28' of the conductor layers 19, 22 are electrically connected to each other. Further, the surface of the second resin insulating layer 21 is covered with the entire portion of the solder resist portion 29 -13-200904267. At a predetermined portion of the solder resist portion 29, an opening portion 30 for exposing the terminal pad 23 is formed. Each of the terminal pads 230 is electrically connected to a connection terminal of a 1C wafer (semiconductor integrated circuit element) via a solder bump (not shown). The second buildup layer 16 formed on the lower surface 14 of the core substrate 12 has substantially the same structure as the first buildup layer 15. In other words, the second build-up layer 16 has a structure in which the resin insulating layers 3A and 32 composed of an epoxy resin and the conductor layers 33 and 34 made of copper are laminated in two layers. The BGA spacers 340 constituting the conductor circuits of the conductor layer 34 are formed in an array at a plurality of planes on the lower surface of the second resin insulating layer 32. A plurality of via holes 25 and via conductors 26 are provided in the first resin insulating layer 31, and a plurality of via holes 27 and via conductors 28 are provided in the second resin insulating layer 32. The conductor circuits 190, 303 and the BGA pads 340 via the via conductors 26, 28' of the conductor layers 19, 33 are electrically connected to each other. Further, the lower surface of the second-layer resin insulating layer 3 2 is substantially covered by the solder resist portion 36. At a predetermined portion of the solder resist portion 36, an opening portion 37 for exposing the BGA spacer 340 is formed. A plurality of solder bumps 38 are disposed on the surface of the BGA pad 340 for electrical connection with a mother board (not shown). By the solder bumps 38, the multilayer wiring substrate 11 is Assembled on the motherboard that is not shown. In addition, as shown in FIG. 1 and FIG. 2, in the predetermined position of the frame portion region 101 of the multilayer wiring substrate 1 (the position of the four corners of the substrate), the core substrate 12 and the resin insulating layer are provided. The alignment marks 4 1 and 4 2 are set on 20 and 3 1 . In the present embodiment, the alignment mark 4 1 and the alignment mark 42 are disposed at positions overlapping each other in the thickness direction of the resin insulating layers 20 and 31. The alignment mark 41 formed on the core substrate 12 is used as a position reference for forming the via holes 25 on the first resin insulating layers 20, 31 by -14-200904267. Further, the alignment mark 42' formed on the resin insulating layers 20, 31 is used as a position reference for forming the via holes 27 on the second resin insulating layers 2, 32. As shown in Fig. 3, the alignment mark 41 is composed of a first light reflection portion 43 and a second light reflection portion 45 that surrounds the first light reflection portion 43 with a predetermined width removal pattern 44 interposed therebetween. In the present embodiment, the first light reflecting portion 43 is formed into a circular shape having a diameter of, for example, 1 mm, and the removal pattern 44 is formed into a ring shape having the same width (width of 100/zm). These first light reflecting portions are formed. 43 and the removal pattern 44 are arranged on concentric circles. Further, the alignment mark 42 is composed of a circular first light reflecting portion 43 and a second light reflecting portion 45 that surrounds the first light reflecting portion 43 via the ring-shaped removing pattern 44. In the case where the alignment marks 4 1 and 42 are formed in this manner, the flatness of the surface of the resin insulating layers 20, 21, 31, 32 covering the alignment marks 41, 42 is increased. Specifically, the height H1 of the surface of the resin insulating layer 20 directly above the removal pattern 44 of the alignment mark 41, the height H2 of the surface of the resin insulating layer 20 directly above the first light reflection portion 43, and the The unevenness of the height H3 of the surface of the resin insulating layer 20 directly above the light reflecting portion 45 is 5/zm or less (in the present embodiment, it is about 2/zm to 3/zm) (see FIG. 4). Next, the manufacturing procedure of the multilayer wiring board 1 1 having the above configuration will be described. First, in the substrate preparation step, a double-sided copper clad laminate 48 obtained by attaching the copper foil 47 to both surfaces of the core substrate 12 is prepared (see Fig. 5). 200904267 Then, laser hole laser processing is performed using a YAG laser or a carbon dioxide gas laser. A through hole penetrating the double-sided copper clad laminate 48 is formed in advance at a predetermined position. Then, electroless copper plating and electrolytic copper plating are performed by a conventionally known method to form a plated through hole 17, and then the ruthenium material 1 is poured into the plated through hole 17 and thermally cured. In the forming step of the conductor circuit or the like, the copper box 47 on both sides of the substrate is etched, whereby the conductor layer 19 (conductor circuit 190) is patterned on the core substrate 12. Specifically, after electroless copper plating, exposure and development are carried out to form a plating resist having a predetermined pattern. In this state, after electrolytic copper plating is performed using the electroless copper plating layer as a common electrode, the plating resist is first dissolved and removed, and the unnecessary electroless copper plating layer is further removed by etching. As a result, the conductor layer 19 (conductor circuit 190) of a predetermined pattern is formed on the product region 100 of the core substrate 12, and the alignment mark 4 1 is formed at a predetermined position (a position which becomes a square corner) of the frame region 101 ( Refer to Figure 6). In the insulating layer forming step, the upper surface 13 and the lower surface 14 of the core substrate 12 are disposed so as to overlap the film-shaped insulating resin materials containing epoxy resin as a main component. Then, the laminate is subjected to pressure heating under vacuum by a vacuum pressure bonding heat press (not shown) to harden the film-shaped insulating resin material, and a first layer of resin is formed on each of the upper surface 13 and the lower surface 14 Insulating layers 20, 3 1 (see Fig. 7). At this time, the epoxy resin oozing out from the film-shaped insulating resin material is lowered to be attached to the removal pattern 44 of the alignment mark 41, but since the gap of the removal pattern 44 is only 1 狭窄 narrow from m, it is hardly The thickness unevenness of the resin insulating layers 20, 31 due to the resin filling the removal pattern 44 may occur. In the detecting step, the annular illuminator 5 1 ' is irradiated with the infrared light L 1 (position detecting light) to the alignment mark 4 1 via the resin insulating-16 - 200904267 layer 20, and is detected based on the reflected light L2. The registration mark 4 1 (refer to Fig. 8). Specifically, the image of the alignment mark 41 is imaged by the CCD camera 52 based on the reflected light L2' from the alignment mark 41 (the first light reflection portion 43 and the second light reflection portion 45). Then, the photographic data of the CCd camera 52 is taken into the computer 53 and image recognition processing is performed, and the position of the registration mark 41 is detected based on the recognized image. Further, in this image recognition processing, the captured image is subjected to binarization processing, and the position of the registration mark 41 is detected based on the processed image data. In the laser opening step, the measured alignment mark 41 is used as the position reference, and after the alignment of the laser irradiation device 5, the laser light is irradiated onto the upper surface 13 of the core substrate 12 by the resin insulation. Layer 20 (refer to Figure 9). Further, an irradiation device such as a carbon dioxide gas laser and a YAG laser is used as the laser irradiation device 54. By this laser irradiation, the via hole 25 is formed at a predetermined position of the resin insulating layer 20, and a part of the conductor circuit 190 of the conductor layer 19 is exposed. Further, the resin insulating layer 31 of the lower surface 14 of the core substrate 12 also detects the position of the alignment mark 41 in the detecting step, and irradiates the laser L0 in the laser opening step, thereby forming at a predetermined position. Via hole 25. Then, by performing electroless copper plating, the via conductors 26 are formed in the via holes 25, and an electroless copper plating layer is formed on the entire upper surface of the resin insulating layer 20. Thereafter, exposure and development are performed to form a plating resist of a predetermined pattern. Then, after electrolytic copper plating is performed, the plating resist is first dissolved and removed, and the unnecessary electroless copper plating layer is further removed by etching. As a result, conductor layers -17-200904267 2 2, 3 3 (conductor circuits 2 2 0, 3 3 0) of a predetermined pattern are formed in the product regions 1A on the resin insulating layers 20, 31, and at the frame region. 1 0 1 forms a registration mark 42 (refer to Fig. 1). Next, in the same manner as in the case of the first resin insulating layers 20 and 31, the second resin insulating layers 2 1 and 3 2 are formed by performing an insulating layer forming step. Further, the position of the alignment mark 42 is detected in the detecting step, and the laser beam L0 is irradiated by the laser opening step, whereby the via hole 27 is formed at a predetermined position of the resin insulating layers 2 1 and 3 2 (refer to FIG. 11). ). Then, by performing electroless copper plating, the via conductors 28 are formed in the via holes 27, and an electroless copper plating layer is formed on the entire upper surfaces of the resin insulating layers 21, 32. Thereafter, exposure and development are carried out to form a plating resist of a predetermined pattern. Then, after electrolytic copper plating is performed, the plating resist is first dissolved and removed, and the unnecessary electroless copper plating layer is further removed by etching. As a result, a plurality of terminal pads 230 are formed at predetermined positions on the resin insulating layer 21, and a plurality of BGA pads 340 are formed at predetermined positions on the resin insulating layer 32 (see Fig. 12). Further, a photosensitive liquid resin material is applied and hardened on the upper surface and the lower surface of the core substrate 12 formed as described above, thereby forming the solder resist portions 29, 36. Next, the glass mask is placed so as to overlap the surfaces of the solder resist portions 29 and 36, and exposure and development are performed, and the openings 3 0 and 3 7 are patterned on the solder resist portions 29 and 36. (Refer to Figure 1 3). Then, the terminal pads 230 exposed from the respective opening portions 30 or the BGA pads 3 40 exposed from the respective opening portions 37 are subjected to surface roughening treatment and nickel-gold plating treatment. Then, a solder bump forming step is formed by a conventional method. A solder bump 38 is formed on the surface of the BGA pad 340 (see FIG. 2). Specifically, 'the predetermined pattern is placed on the solder resist 36. Cover -18- 200904267 Cover, after printing the solder paste on the BGA pad 340, the solder paste is reflowed. Then, the intermediate product integrated in a large state is cut and separated into individual pieces by using a cutting tool such as a cutting blade, thereby completing the multilayer wiring board. In order to confirm the effect of the manufacturing method of the present embodiment, the positional accuracy of the via hole 25 on the core substrate 12 with respect to the conductor circuit 190 (pad) was measured. Fig. 14 shows the measurement result 56. Further, here, the offset (displacement amount) of the center coordinates of the via hole 25 with respect to the center coordinates of the spacer is shown. Further, as a comparative example, as shown in Fig. 15, a measurement result 58 of the positional accuracy when the via hole 25 is formed by using the circular alignment mark 71 (marker having a diameter of 1 mm) is shown in Fig. 15. As shown in FIG. 14 and FIG. 5, in the present embodiment, the unevenness of the amount of misalignment is reduced and the via hole 25 is formed with high precision as compared with the comparative example of the prior art. Fig. 16 shows an image 161 of the alignment mark 4 1 taken in the detection step in the present embodiment, and Fig. 17 shows an image 6 2 of the alignment mark 71 of the comparative example. As shown in Fig. 16, in the present embodiment, since the image 6 having the sharp outline of the alignment mark 4 1 can be obtained, the recognition degree of the alignment mark 4 1 for image recognition becomes good. As a result, the position of the alignment mark 41 is more accurately detected, and the processing accuracy of the laser-processed via hole 25 is improved. Further, in the above-described detecting step, the inventors of the present invention changed the irradiated position detecting light L1 from infrared light to red light (visible light), and took an image of the registration mark 41 (not shown). In this case, since the contour of the alignment mark 4 1 becomes unclear, the image recognition is difficult compared to the case of using infrared light. Further, the inventor of the present invention changed the gap of the pattern mark 44 from the range of 100 μm to 200 // m, and took a portrait (not shown) of the alignment mark 41. In this case, in the insulating layer forming step, by laminating the epoxy resin to the removal pattern 44, the height unevenness of the surface of the resin insulating layers 20, 31 covering the alignment mark 41 becomes large. Therefore, the outline of the alignment mark 4 1 is unclear, and the recognition accuracy thereof is deteriorated. Therefore, the following effects can be obtained by the present embodiment. (1) In the present embodiment, the alignment marks 4 1 and 42 are composed of the first light reflecting portion 43 and the second light reflecting portion 45 that surrounds the first light reflecting portion 43 with the removal pattern 44 interposed therebetween. Therefore, compared with the case where the conductor layer is not formed around the alignment mark 71 as in the prior art (refer to FIG. 18), the resin insulating layers 20, 21, 31 covering the alignment marks 41, 42 can be suppressed. The unevenness of the surface of 32. Therefore, in the detecting step, the diffusion of the position detecting light L1 irradiated to the alignment marks 41 and 42 via the resin insulating layers 20, 21, 31, 32 can be suppressed. Therefore, the position detecting light L1 is reliably reflected on the surfaces of the first light reflecting portion 43 and the second light reflecting portion 45, and the alignment marks 4 1 and 4 can be accurately detected based on the reflected light L2. 2 location. In this manner, the via holes 25 and 27 can be formed at the correct positions corresponding to the conductor circuits 190, 220, and 330 of the conductor layers 19, 22, and 33, and the conductor circuits 190, 220, and 30 of the multilayer wiring substrate 11 can be realized. Subtle. (2) In the case of the present embodiment, since the width of the removal pattern 44 of the alignment marks 4 1 and 42 is 100 volts, the resin insulating layers 20, 21, 31 covering the alignment marks 41, 42 can be reduced. The unevenness on the surface of 32 can improve the recognition accuracy of the alignment marks 4 1 and 42 of the image recognition. (3) In the case of the present embodiment, since the first light reflecting portion 43 of the alignment marks 4 1 and 42 has a circular shape and the removal pattern 4 4 has a ring shape, the alignment can be easily formed -20-200904267. Mark 4 1 , 4 2 . Further, since the removal pattern 4 4 has the same width, the contours of the alignment marks 4 1 and 42 become sharp, and the positions of the alignment marks 4 1 and 4 2 can be surely detected by the image recognition. (4) In the case of the present embodiment, since the infrared light is used as the position detecting light in the detecting step, the more vivid image 6 can be obtained by the image recognition, and the alignment mark 4 can be surely detected. 1, 42 position. (5) In the case of this embodiment, the alignment marks 41 and 42 are formed not in the product region 100 but in the frame region 101 surrounding the product region 100. In the multilayer wiring substrate 1 1, a plurality of conductor circuits 190, 220' 3 30 or via conductors 26, 28 are densely gathered in the product region 1 ' 'When the alignment marks 4 1 and 42 are to be disposed here, it is hindered The miniaturization of the entire product. On the other hand, as in the present embodiment, by providing the alignment marks 4 1 and 42 at the frame portion area 1 0 1 which does not become a product at the end, it is possible to reduce the size of the product. Further, the degree of freedom in the arrangement of the alignment marks 41 and 42 is also increased, which is practically preferable. Further, the embodiment of the present invention may be modified as follows. The multilayer wiring board 11 of the above-described embodiment is an organic type multilayer wiring board in which the core substrate 12 is composed of a resin material. However, the present invention can also be applied to a multilayer wiring board composed of a ceramic material or a metal material. In the insulating layer forming step of the above-described embodiment, the resin insulating layers 20, 21, 31, and 3 are formed using a film-shaped insulating resin material, but otherwise, liquid solder resisting can be performed. The portions are coated and dried to form resin insulating layers 20, 21, 31, and 32. The alignment mark 4 of the above-described embodiment is the first light reflection portion 43 - 21 - 200904267. The circular shape 'removal pattern 44 is annular, but the shape is not limited thereto, and may be changed to, for example, a square shape or a triangular shape. The first light reflecting portion 43 or the removal pattern 44. Further, in terms of the alignment mark 41 and the alignment mark 42, those shapes or sizes may be different. Further, in the above-described embodiment, the alignment mark 4 1 and the alignment mark 42 are formed at positions overlapping in the thickness direction of the resin insulating layers 20 and 3 1 , but they may be formed to be displaced from this position. In the above embodiment, the package form of the multilayer wiring substrate 11 is a BGA (Ball Gate Array Package), but it is not limited to the BGA, and may be, for example, a PGA (Pin Grid Array [J] or LGA (Plane Gate). Grid! J) and so on. Next, in addition to the technical ideas described in the patent application, the technical ideas grasped by the above embodiments will be listed below. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic plan view showing a multilayer wiring board according to an embodiment of the present invention. Fig. 2 is a cross-sectional view showing the main part of a multilayer wiring board according to an embodiment of the present invention. Figure 3 is a plan view showing the alignment mark of an embodiment. Fig. 4 is a cross-sectional view showing the height unevenness of the surface of the resin insulating layer covering the alignment mark. Fig. 5 is a cross-sectional view for explaining a method of manufacturing a multilayer wiring board according to an embodiment. Fig. 6 is a cross-sectional view for explaining a method of manufacturing a multilayer wiring board according to an embodiment. Fig. 7 is a cross-sectional view for explaining a method of manufacturing the multilayer wiring board of the embodiment. -22-200904267 Fig. 8 is a cross-sectional view for explaining a method of manufacturing a multilayer wiring board according to an embodiment. Fig. 9 is a cross-sectional view for explaining a method of manufacturing a multilayer wiring board according to an embodiment. Fig. 10 is a cross-sectional view for explaining a method of manufacturing a multilayer wiring board according to an embodiment. Fig. 1 is a cross-sectional view for explaining a method of manufacturing a multilayer wiring board according to an embodiment. r Fig. 1 is a cross-sectional view for explaining a method of manufacturing a multilayer wiring board according to an embodiment. Fig. 1 is a cross-sectional view for explaining a method of manufacturing a multilayer wiring board according to an embodiment. Fig. 14 is an explanatory view showing the measurement result of the alignment accuracy of the embodiment. Fig. 15 is a view showing the measurement result of the alignment accuracy of the comparative example. Fig. 16 is a diagram showing the image of the alignment mark of one embodiment. Fig. 17 is an explanatory view showing an image of a registration mark of a comparative example. Fig. 18 is a cross-sectional view showing a height unevenness of a surface of a resin insulating layer which conventionally covers an alignment mark. [Description of main component symbols] 11 Multi-layer wiring board 12 The core board 13 is the upper surface of the core main surface 23-200904267 14 The lower surface 15 and 16 which are the main surfaces of the core are the build-up layers 19 and 22 as the laminated wiring portions. 23, 33, 34 Conductor layer 20' 21' 31, 32 as a metal layer Resin insulating layer 41' as an interlayer resin insulating layer 4 2 Alignment mark 43 First light reflecting portion 44 Removal pattern 45 Second light reflecting portion 190, 220, 330 Conductor circuit L0 Laser LI position detection light L2 Reflected light HI, H2, H3 Surface height of interlayer resin insulation layer 24-