JP5148334B2 - Manufacturing method of multilayer wiring board - Google Patents

Description

  The present invention relates to a method for manufacturing a multilayer wiring board.

  In recent years, with the miniaturization of electrical equipment, electronic equipment, etc., miniaturization and high density have been demanded for wiring boards and the like mounted on these equipments. In order to meet such market demand, multilayer circuit board technology has been studied. As a method of multilayering this wiring board, a so-called build-up method is generally employed in which a resin insulating layer and a conductor layer are alternately laminated and integrated on both the front and back surfaces of a so-called core board.

  In this type of multilayer wiring board, a solder resist is formed so as to cover the uppermost conductor layer, and a part of the conductor layer (specifically, for example, a terminal pad for IC connection) is exposed to the solder resist. An opening is provided for this purpose. In the case of forming this multilayer wiring board, an exposure glass mask is placed on the solder resist while performing alignment using the alignment mark formed on the wiring board side as a position reference. And in this state, it exposes through the glass mask for exposure, and by developing further, a soldering resist is drilled and an opening part is formed.

For example, Patent Document 1 discloses a method of manufacturing a wiring substrate in which alignment marks are formed on the wiring substrate to align the glass mask. In the manufacturing method of Patent Document 1, a solder resist is excavated by laser processing to form an alignment mark in a form in which a lower conductor layer is exposed in a ring shape. And the alignment mark is image | photographed by imaging means, such as a CCD camera. The captured data is taken into a computer to perform image recognition of the alignment mark, and after aligning based on the recognized image, a glass mask is placed on the solder resist.
JP-A-2005-244182

  By the way, when the alignment mark is formed by laser processing as in the above-described prior art, a process for the laser processing is required, which increases the manufacturing cost of the multilayer wiring board. If the laser output is not set appropriately, it is difficult to evenly cut and drill the solder resist on the conductor layer, and the conductor layer may be shaved by laser processing, or a solder resist may be formed on the upper surface of the conductor layer. The problem that a part may remain arises. Therefore, a technique for reading the alignment mark through the solder resist without exposing the alignment mark has been studied.

  Specifically, as shown in FIG. 18, an alignment mark 71 (for example, a circular mark having a diameter of 1 mm) is formed at a position different from the conductor circuit in the conductor layer, and a solder resist is formed on the conductor layer. 72 is formed to cover the alignment mark 71. Thereafter, the position detection light L <b> 1 is irradiated onto the alignment mark 71 from above via the solder resist 72. Then, image recognition processing is performed based on the reflected light L2 of the position detection light L1, and the position of the alignment mark 71 is detected.

  However, a general solder resist is colored, and there is also a product (for example, SR-7200 manufactured by Hitachi Chemical Co., Ltd.) whose color is dark according to product performance. When the dark solder resist is used, the reflected light L2 with sufficient intensity cannot be acquired, and it is difficult to accurately detect the position of the alignment mark 71 by image recognition. In this case, since the alignment accuracy is lowered, the exposure glass mask cannot be arranged at an accurate position. Therefore, an opening cannot be formed at a position corresponding to the conductor circuit of each conductor layer, which hinders miniaturization of the conductor circuit.

  The present invention has been made in view of the above problems, and an object of the present invention is to reliably detect the alignment mark, and to open the opening at an accurate position corresponding to the conductor circuit using the alignment mark as a position reference. It is an object of the present invention to provide a method for manufacturing a multilayer wiring board capable of forming a substrate.

Means (Means 1) for solving the above-described problems include a core substrate having a core main surface, a plated metal layer and an interlayer resin insulating layer constituting a conductor circuit, and disposed on the core main surface. A method of manufacturing a multilayer wiring board, comprising: a multilayer wiring board comprising: The conductor circuit is formed by plating on the resin insulating layer, and a frame-shaped conductor portion thicker than the conductor circuit is used as an alignment mark at a position different from the conductor circuit in the plated metal layer. A conductor forming step for forming, a solder resist forming step for forming the colored solder resist covering the conductor circuit and the frame-like conductor portion on the plated metal layer, and the colored solder. A detection step of detecting the frame-shaped conductor portion based on the reflected light of the position detection light applied to the frame-shaped conductor portion via a resist, and a position using the detected frame-shaped conductor portion as a position reference; combined with drilling a solder resist of the color after performing, look including a drilling step of forming the opening, in the solder resist forming step, the thickness of the solder resist of the color that is immediately above the conductive circuit However, there is a method for manufacturing a multilayer wiring board, wherein the thickness is larger than the thickness of the colored solder resist immediately above the frame-like conductor portion .

Therefore, according to the manufacturing method of the multilayer wiring board of means 1, in the conductor forming step, a conductor circuit is formed by plating on the interlayer resin insulating layer, and at a position different from the conductor circuit in the plated metal layer, A frame-shaped conductor portion thicker than the conductor circuit is formed as an alignment mark. In the solder resist forming step, a colored solder resist is formed on the plated metal layer, and the conductor circuit and the frame-shaped conductor portion are covered with the solder resist. Since the alignment mark of the present invention is a frame-shaped conductor portion that is thicker than the conductor circuit, the thickness of the solder resist that covers the frame-shaped conductor portion can be made thinner than the thickness on the conductor circuit side. Therefore, in the detection step, when the frame-shaped conductor portion is irradiated with the position detection light via the solder resist, the intensity of the reflected light can be sufficiently secured, and the position of the frame-shaped conductor portion is determined based on the reflected light. Can be reliably detected. In this way, by performing alignment using the frame-shaped conductor portion as a position reference in the drilling step, an opening can be formed at an accurate position corresponding to the conductor circuit, and the conductor in the multilayer wiring board can be formed. Circuit miniaturization can be achieved.
Here, the “frame-like conductor portion” means a conductor portion having a shape that is formed only by an outline line that is hollow. The shape of the frame-shaped conductor portion in plan view is not particularly limited, and for example, a circular shape (that is, a ring shape), an elliptical shape, a triangular shape, a quadrangular shape, a hexagonal shape, or the like can be adopted. Among these, considering the ease of pattern formation and the ease of alignment work, it is preferable to adopt a circular ring-shaped conductor portion in plan view.

  The frame-like conductor part is preferably thicker than the conductor circuit by 5 μm or more, for example. If it does in this way, the thickness of the soldering resist which covers a frame-shaped conductor part can be made 5 micrometers or more thinner than the conductor circuit part side. Therefore, in the detection step, the intensity of the reflected light of the position detection light can be sufficiently ensured, and the position of the alignment mark can be reliably detected based on the reflected light. In addition, it is more preferable that the thickness of the frame-shaped conductor portion is 5 μm or more and 10 μm or less of the thickness of the conductor circuit.

  The thickness of the colored solder resist around the conductor circuit is preferably 10 μm or more, and the thickness of the colored solder resist immediately above the frame-shaped conductor is preferably 5 μm or less. In this way, the conductor circuit can be reliably protected by a relatively thick solder resist of 10 μm or more. Further, since the solder resist immediately above the frame-like conductor portion is 5 μm or less in thickness and is relatively thin, it is possible to sufficiently secure the intensity of the reflected light for position detection, and the position based on the reflected light. The position of the alignment mark can be detected reliably. Similarly, the thickness of the colored solder resist just above the conductor circuit is larger than the thickness of the colored solder resist just above the frame-like conductor, and the difference is preferably 5 μm or more. In this way, while the conductor circuit can be reliably protected by the relatively thick solder resist, the intensity of the reflected light of the position detection light can be sufficiently secured by the relatively thin solder resist, and based on the reflected light. The position of the alignment mark can be reliably detected.

  The width of the frame-shaped conductor portion is not particularly limited, but is preferably 10 μm or more, and more preferably 50 μm or more and 250 μm or less. The reason is that if the width of the frame-like conductor portion is smaller than 50 μm, the recognition accuracy of the alignment mark cannot be sufficiently secured. Further, if the width of the frame-shaped conductor portion is larger than 250 μm, it is difficult to deposit the plating during the formation of the conductor by plating, and the thickness of the frame-shaped conductor portion cannot be secured sufficiently. The width is more preferably 100 μm or more and 200 μm or less. The width is preferably a constant width.

  The diameter of the central hole of the frame-shaped conductor portion is preferably 500 μm or more and 1500 μm or less, and is preferably 1000 μm or less in consideration of plating deposition. If it does in this way, a frame-shaped conductor part becomes an appropriate magnitude | size and it can fully ensure the recognition accuracy of the frame-shaped conductor part by image recognition.

  In the drilling step, an exposure glass mask is disposed on the colored solder resist while performing alignment using the detected frame-shaped conductor portion as a position reference, and in this state, the exposure glass mask is interposed. It is preferable that the colored solder resist is perforated to form the opening by performing exposure and further development. In this case, by aligning using the frame-shaped conductor as a position reference, the exposure glass mask can be placed at a more accurate position, so an opening is formed at an accurate position corresponding to the conductor circuit. can do.

  In the detection step, the position of the alignment mark is preferably detected by image recognition processing using a computer.

  The material for forming the core substrate is not particularly limited, and can be appropriately selected in consideration of cost, workability, insulation, mechanical strength, and the like. Examples of the core substrate include a resin substrate, a ceramic substrate, and a metal substrate. Specific examples of the resin substrate include an EP resin (epoxy resin) substrate, a PI resin (polyimide resin) substrate, a BT resin (bismaleimide-triazine resin) substrate, and a PPE resin (polyphenylene ether resin) substrate. In addition, a substrate made of a composite material of these resins and organic fibers such as glass fibers (glass woven fabric or glass nonwoven fabric) or polyamide fibers may be used. Alternatively, a substrate made of a resin-resin composite material obtained by impregnating a thermosetting resin such as an epoxy resin with a three-dimensional network fluorine-based resin base material such as continuous porous PTFE may be used. Specific examples of the ceramic substrate include an alumina substrate, a beryllia substrate, a glass ceramic substrate, and a substrate made of a low-temperature fired material such as crystallized glass. Specific examples of the metal substrate include a copper substrate, a copper alloy substrate, a substrate made of a single metal other than copper, and a substrate made of an alloy of a metal other than copper. The core substrate may be formed with a plurality of plated through holes penetrating the upper and lower surfaces thereof, and the plurality of plated through holes may be filled with a filler. The core substrate may be a substrate in which a wiring layer is formed, or a substrate in which electronic components such as a chip capacitor and a chip resistor are embedded.

  Examples of the material of the plated metal layer constituting the conductor circuit include copper, copper alloy, nickel, nickel alloy, tin, tin alloy and the like. The plated metal layer can be formed by a known method such as a semi-additive method or a full additive method. Specifically, for example, techniques such as electroless copper plating, electrolytic copper plating, electroless nickel plating, or electrolytic nickel plating can be used.

  The interlayer resin insulation layer is formed using a thermosetting resin, for example. Preferable examples of the thermosetting resin include EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide-triazine resin), phenol resin, xylene resin, polyester resin, silicon resin and the like. . Among these, it is preferable to select EP resin (epoxy resin), PI resin (polyimide resin), and BT resin (bismaleimide-triazine resin). For example, as the epoxy resin, a so-called BP (bisphenol) type, PN (phenol novolac) type, or CN (cresol novolac) type may be used. In particular, the BP (bisphenol) type is mainly used, and the BPA (bisphenol A) type and BPF (bisphenol F) type are the best.

  The solder resist is made of a resin having insulating properties and heat resistance, and functions as a protective film for protecting the conductor circuit by covering the conductor circuit. In the present invention, for example, a solder resist made of a photocurable resin is used, and specifically, use of an epoxy resin, a polyimide resin, or the like is preferable.

  Here, when the multilayer wiring board has at least one product region and a frame region surrounding the product region, the frame-shaped conductor as the alignment mark is not formed in the product region. Rather, it is preferably formed in the frame region. A large number of conductor circuits are concentrated in the product area, and if a frame-like conductor portion is provided there, the downsizing of the entire product is hindered. On the other hand, if it is a frame region that will not eventually become a product, even if a frame-shaped conductor portion is provided there, it does not hinder downsizing of the product in particular, and when the frame-shaped conductor portion is formed This is because the degree of freedom of the arrangement of is large.

  Hereinafter, an embodiment of a multilayer wiring board embodying the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic plan view of a multilayer wiring board, and FIG. 2 is a cross-sectional view of the multilayer wiring board.

  As shown in FIG. 1, the multilayer wiring board 11 has a rectangular shape in plan view, and includes a plurality (4 × 4 in this case) of product regions 100 and a frame region 101 that surrounds the product regions 100. And have. Since the frame region 101 does not become a product, it is finally cut and removed through a dicing process.

  As shown in FIG. 2, the core substrate 12 constituting the multilayer wiring substrate 11 is a substantially rectangular plate-shaped member (thickness 0.8 mm) made of glass epoxy, and has an upper surface 13 and a lower surface 14 as core main surfaces. have. A first buildup layer 15 (laminated wiring portion) is formed on the upper surface 13 of the core substrate 12, and a second buildup layer 16 (laminated wiring portion) is formed on the lower surface 14 of the core substrate 12. A large number of plated through holes 17 that allow the upper surface 13 and the lower surface 14 to communicate with each other are formed at predetermined locations in the product region 100 of the core substrate 12. A hollow portion in the plated through hole 17 is filled with a filler 18 made of an epoxy resin containing a copper filler. A conductor layer 19 made of copper is patterned on the upper surface 13 and the lower surface 14 of the core substrate 12, and each conductor layer 19 is electrically connected to the plated through hole 17.

  The first buildup layer 15 formed on the upper surface 13 of the core substrate 12 includes resin insulation layers 20 and 21 (interlayer resin insulation layer) made of epoxy resin and conductor layers 22 and 23 (plating metal layer made of copper). ) And two layers. In the present embodiment, the thickness of each of the resin insulation layers 20 and 21 is about 40 μm, and the thickness of each of the conductor layers 22 and 23 is about 20 μm.

  Terminal pads 230 constituting a conductor circuit of the conductor layer 23 are formed in an array at a plurality of locations on the surface of the second resin insulating layer 21. A plurality of via holes 25 and via conductors 26 are provided in the first resin insulation layer 20, and a plurality of via holes 27 and via conductors 28 are provided in the second resin insulation layer 21. Yes. Via these via conductors 26 and 28, the conductor circuits 190 and 220 of the conductor layers 19 and 22 and the terminal pads 230 are electrically connected to each other. Further, the surface of the second resin insulating layer 21 is almost entirely covered with a colored solder resist 29 (specifically, SR-7200 manufactured by Hitachi Chemical Co., Ltd.). An opening 30 for exposing the terminal pad 230 is formed at a predetermined location of the solder resist 29. Each terminal pad 230 is electrically connected to a connection terminal of an IC chip (semiconductor integrated circuit element) via a solder bump (not shown).

  The second buildup layer 16 formed on the lower surface 14 of the core substrate 12 has substantially the same structure as the first buildup layer 15 described above. That is, the second buildup layer 16 has a structure in which two resin insulating layers 31 and 32 made of epoxy resin and two conductor layers 33 and 34 made of copper are laminated. BGA pads 340 constituting the conductor circuit of the conductor layer 34 are formed in an array at a plurality of locations on the lower surface of the second resin insulation layer 32. A plurality of via holes 25 and via conductors 26 are provided in the first resin insulation layer 31, and a plurality of via holes 27 and via conductors 28 are provided in the second resin insulation layer 32. Yes. The conductor circuits 190 and 330 of the conductor layers 19 and 33 and the BGA pad 340 are electrically connected to each other through the via conductors 26 and 28. The lower surface of the second resin insulating layer 32 is almost entirely covered with a solder resist 36. An opening 37 for exposing the BGA pad 340 is formed at a predetermined position of the solder resist 36. On the surface of the BGA pad 340, a plurality of solder bumps 38 for electrical connection with a mother board (not shown) are disposed, and the multilayer wiring board 11 is mounted on the mother board (not shown) by each solder bump 38. Is done.

  Further, as shown in FIGS. 1 and 2, on the surface of the second resin insulating layers 21 and 32 at predetermined positions (positions corresponding to the four corners of the substrate) of the frame region 101 of the multilayer wiring board 11. A ring-shaped conductor 41 (frame-shaped conductor) is provided as an alignment mark. The ring-shaped conductor portion 41 is used as a position reference for forming the openings 30 and 37 in the solder resists 29 and 36.

  In the present embodiment, the width W1 of the ring-shaped conductor portion 41 is 200 μm, and the diameter D1 of the center hole is 1000 μm (see FIG. 3). Further, as shown in FIG. 4, the ring-shaped conductor portion 41 is formed thicker than the terminal pad 230 as a conductor circuit. Specifically, the thickness T1 of the ring-shaped conductor portion 41 is 28 μm, and the thickness T2 of the conductor circuit is 20 μm. Further, the thickness T3 of the solder resists 29 and 36 immediately above the ring-shaped conductor portion 41 is 5 μm or less (specifically, 3 μm to 4 μm), and the solder resist 29 around the terminal pads 230 and the BGA pads 340 is used. , 36 has a thickness T4 + T2 of 10 μm or more (specifically, 15 μm to 30 μm). The thickness T4 of the solder resists 29 and 36 immediately above the terminal pad 230 and the BGA pad 340 is 10 μm or more (specifically, 12 μm to 15 μm).

  Next, a manufacturing procedure of the multilayer wiring board 11 having the above configuration will be described.

  First, in the substrate preparation step, a double-sided copper-clad laminate 48 in which a copper foil 47 is bonded to both surfaces of the core substrate 12 is prepared (see FIG. 5). Then, laser drilling is performed using a YAG laser or a carbon dioxide laser, and a through hole penetrating the double-sided copper-clad laminate 48 is formed in advance at a predetermined position. Then, after forming a plated through hole 17 by performing electroless copper plating and electrolytic copper plating according to a conventionally known method, the plated through hole 17 is filled with a filler 18 and thermally cured. Thereafter, the conductor layer 19 (conductor circuit 190) is patterned on the core substrate 12 by etching the copper foil 47 on both sides of the substrate. Specifically, after electroless copper plating, exposure and development are performed to form a predetermined pattern of plating resist. In this state, after electrolytic copper plating is performed using the electroless copper plating layer as a common electrode, first, the resist is dissolved and removed, and further unnecessary electroless copper plating layer is removed by etching. As a result, a conductor layer 19 (conductor circuit 190) having a predetermined pattern is formed in the product region 100 of the core substrate 12 (see FIG. 6).

  In the insulating layer forming step, a film-like insulating resin material mainly composed of an epoxy resin is disposed on the upper surface 13 and the lower surface 14 of the core substrate 12 so as to overlap each other. Then, such a laminate is pressurized and heated under vacuum with a vacuum press hot press machine (not shown) to cure the film-like insulating resin material so that the upper layer 13 and the lower surface 14 have a first layer of resin insulation. Layers 20 and 31 are formed (see FIG. 7).

  By irradiating a predetermined position of the resin insulating layers 20 and 31 with a laser, the via hole 25 is formed. Then, by performing electroless copper plating, a via conductor 26 is formed in the via hole 25, and an electroless copper plating layer is formed on the entire upper surface of the resin insulating layer 20. Thereafter, exposure and development are performed to form a predetermined pattern of plating resist. Then, after the electrolytic copper plating is performed, the resist is first dissolved and removed, and an unnecessary electroless copper plating layer is removed by etching. As a result, conductor layers 22 and 33 (conductor circuits 220 and 330) having a predetermined pattern are formed on the resin insulating layers 20 and 31 (see FIG. 8).

  Next, as in the case of the first resin insulation layers 20 and 31, the second resin insulation layers 21 and 32 are formed by performing an insulation layer forming step. Furthermore, a via hole 27 is formed by irradiating a predetermined position on the resin insulating layers 21 and 32 with a laser.

  In the subsequent conductor forming step, by performing electroless copper plating, the via conductor 28 is formed in the via hole 27 and the electroless copper plating layer is formed on the entire upper surfaces of the resin insulating layers 21 and 32. Thereafter, exposure and development are performed to form a plating resist 43 having a predetermined pattern, and electrolytic copper plating is performed (see FIG. 9). Here, the thickness of the plating resist 43 is about 30 μm, and a plating layer 44 having a thickness of about 20 μm is formed at a position corresponding to each conductor circuit in the product region 100. In addition, the product region 100 has a pattern corresponding to each conductor circuit, whereas the frame region 101 has only a pattern of the ring-shaped conductor portion 41, and the current density at the time of plating becomes high. Therefore, the frame region 101 is more easily deposited than the product region 100 side, and a plating layer 45 having a thickness of 28 μm is formed at a position corresponding to the ring-shaped conductor portion 41. In particular, in the present embodiment, by forming a ring-shaped conductor portion instead of a circle as in the prior art, the area of the conductor portion is reduced and plating is likely to be deposited, so that the plating layer 45 is formed thick. Is done.

  Thereafter, the resist is first dissolved and removed, and an unnecessary electroless copper plating layer is removed by etching. As a result, a plurality of terminal pads 230 are formed in the product region 100 and the ring-shaped conductor portion 41 is formed in the frame region 101 on the resin insulating layer 21. On the resin insulating layer 32, a plurality of BGA pads 340 are formed in the product region 100, and a ring-shaped conductor portion 41 is formed in the frame region 101 (see FIG. 10).

  In the solder resist forming step, colored solder resists 29 and 36 are formed by applying and curing a photosensitive liquid resin material on the upper and lower surfaces of the core substrate 12 (see FIG. 11). In the present embodiment, a halogen-free photosensitive liquid solder resist (for example, SR-7200 manufactured by Hitachi Chemical Co., Ltd.) is used.

  In the detection process, the ring-shaped conductor 51 is irradiated with infrared light L1 (position detection light) through the solder resist 29 using the ring-shaped irradiator 51, and the ring-shaped conductor is based on the reflected light L2. 41 is detected (see FIG. 12). Specifically, an image of the ring-shaped conductor portion 41 is taken by the CCD camera 52 based on the reflected light L <b> 2 from the ring-shaped conductor portion 41. Then, the photographing data of the CCD camera 52 is taken into the computer 53 and image recognition processing is performed, and the position of the ring-shaped conductor portion 41 is detected based on the recognized image. In this image recognition process, the captured image is binarized, and the position of the ring-shaped conductor portion 41 is detected based on the image data after the processing.

  Next, in the drilling step, using the detected ring-shaped conductor portion 41 as a position reference, the alignment device 54 is driven to perform alignment, and then the exposure glass mask 56 is overlaid on the surface of the solder resist 29. (Refer to FIG. 12). In the exposure glass mask 56, a circular punch pattern 57 (a circular hole in the metal layer constituting the glass mask 56) is formed at a position corresponding to the ring-shaped conductor portion 41, and the center position of the pattern 57 And an exposure glass mask 56 are arranged so that the center position of the ring-shaped conductor portion 41 coincides with that of the ring-shaped conductor portion 41 (see FIG. 13). In this state, the opening 30 is patterned in the solder resist 29 by performing exposure through the glass mask for exposure 56 and further developing (see FIG. 14).

  Similarly, for the solder resist 36 on the lower surface side of the core substrate 12, the position of the ring-shaped conductor portion 41 is detected in the detection process, and an exposure glass mask 56 is disposed on the surface of the solder resist 36 in the drilling process. Then, exposure and development are performed to pattern the opening 37 in the solder resist 36 (see FIG. 14).

  Then, a surface roughening process and a nickel-gold plating process are performed on the terminal pads 230 exposed from the openings 30 and the BGA pads 340 exposed from the openings 37. Thereafter, a solder bump forming step is performed by a well-known method to form solder bumps 38 on the surface of the BGA pad 340 (see FIG. 2). Specifically, a mask having a predetermined pattern is placed on the solder resist 36, a solder paste is printed on the BGA pad 340, and then the solder paste is reflowed. Thereafter, the intermediate product integrated in a large format is cut into individual pieces using a cutting tool such as a dicing blade to complete a multilayer wiring board.

  FIG. 15 shows an image 61 of the ring-shaped conductor portion 41 (alignment mark) photographed in the detection process in the present embodiment, and FIG. 16 includes a circular conductor portion as in the prior art. An image 62 of an alignment mark 71 (a mark having a diameter of 1 mm) is shown as a comparative example. As shown in FIG. 15, in the present embodiment, an image 61 with a clear outline of the ring-shaped conductor portion 41 can be acquired as compared with the comparative example of the prior art. Therefore, the recognizability of the ring-shaped conductor part 41 by image recognition becomes good, and the position of the ring-shaped conductor part 41 is detected more accurately.

  The inventors of the present application changed the width of the ring-shaped conductor portion 41 from 200 μm to 100 μm and photographed an image (not shown) of the ring-shaped conductor portion. Even in this case, an image with a clear outline of the ring-shaped conductor portion 41 can be taken, and the recognition accuracy of the ring-shaped conductor portion 41 can be sufficiently ensured.

  Further, the inventor of the present application changed the diameter of the alignment mark 71 of the comparative example from 1 mm to 0.2 mm, and took an image 63 of the alignment mark (see FIG. 17). In this way, when the size of the alignment mark 71 is reduced, a plating layer thicker than the conductor circuit side can be formed as in the present embodiment, but the size of the alignment mark 71 is reduced. The recognition accuracy could not be secured sufficiently.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the multilayer wiring board 11 of the present embodiment, a ring-shaped conductor 41 as an alignment mark is provided in a frame region 101 without a wiring circuit. When manufacturing this multilayer wiring board 11, the ring-shaped conductor part 41 can be formed thicker than conductor circuits, such as the terminal pad 230 and the BGA pad 340, by performing copper plating in the conductor forming step. As a result, the thickness T3 of the solder resists 29 and 36 covering the ring-shaped conductor portion 41 can be made thinner than the thickness T4 on the conductor circuit side. Therefore, even when the dark solder resists 29 and 36 are used, the intensity of the reflected light L2 of the position detection light L1 irradiated to the ring-shaped conductor portion 41 through the solder resists 29 and 36 is sufficiently secured. The image 61 with a clear outline of the ring-shaped conductor portion 41 can be acquired. Then, the position of the ring-shaped conductor portion 41 can be reliably detected by the image recognition processing, and by performing alignment using the ring-shaped conductor portion 41 as a position reference, the terminal pad 230 and the BGA pad 340 are aligned. The openings 30 and 37 can be formed at corresponding and accurate positions. Therefore, in the multilayer wiring board 11, the conductor circuit including the terminal pad 230 and the BGA pad 340 can be miniaturized.

  (2) In the case of the present embodiment, the solder resists 29 and 36 around the terminal pad 230 and the BGA pad 340 are 10 μm or thicker, and the relatively thick solder resists 29 and 36 ensure the conductor circuit. Can be protected. Further, since the solder resists 29 and 36 immediately above the ring-shaped conductor portion 41 have a thickness of 5 μm or less and are relatively thin, it is possible to sufficiently secure the intensity of the reflected light L2 of the position detection light L1. As a result, the recognition accuracy of the ring-shaped conductor part 41 by image recognition can be improved.

  (3) In the present embodiment, the width W1 of the ring-shaped conductor portion 41 is 200 μm, and the diameter D1 of the center hole is 1000 μm. In this case, when the conductor is formed by plating, the plating is easily deposited, and the thickness T1 of the ring-shaped conductor portion 41 can be sufficiently ensured.

  (4) In the case of the present embodiment, the ring-shaped conductor portion 41 is not formed in the product region 100 but is formed in the frame region 101 surrounding the product region 100. In the multilayer wiring board 11, a large number of conductor circuits such as terminal pads 230 and BGA pads 340 and via conductors 26 and 28 are concentrated in the product region 100, and the ring-shaped conductor portion 41 is provided there. It will hinder downsizing of the entire product. On the other hand, the product size can be reduced by providing the ring-shaped conductor portion 41 in the frame region 101 that is not finally a product as in the present embodiment. Further, the degree of freedom in arrangement when forming the ring-shaped conductor portion 41 is increased, which is practically preferable.

  In addition, you may change embodiment of this invention as follows.

  The multilayer wiring board 11 of the above embodiment is an organic type multilayer wiring board in which the core substrate 12 is made of a resin material, but the present invention may be applied to a multilayer wiring board made of a ceramic material or a metal material.

  In the above embodiment, the package form of the multilayer wiring board 11 is BGA (ball grid array), but is not limited to BGA alone, for example, PGA (pin grid array), LGA (land grid array), etc. Also good.

  Next, in addition to the technical ideas described in the claims, the technical ideas grasped by the embodiments described above are listed below.

  (1) A core substrate having a core main surface, a plated metal layer and an interlayer resin insulation layer constituting a conductor circuit, and a laminated wiring portion disposed on the core main surface, and one of the plated metal layers A method of manufacturing a multilayer wiring board having an opening that exposes a portion and a colored solder resist disposed on the laminated wiring portion, wherein the conductor is formed by plating on the interlayer resin insulating layer Forming a circuit, and forming a ring-shaped conductor portion having a predetermined width and a thicker thickness than the conductor circuit as an alignment mark at a position different from the conductor circuit in the plated metal layer; A solder resist forming step of forming the colored solder resist covering the conductive circuit and the ring-shaped conductor on the plated metal layer, and the colored solder resist. An image recognition process is performed based on the reflected light of the position detection light irradiated on the ring-shaped conductor portion, and a detection step of detecting the ring-shaped conductor portion and using the detected ring-shaped conductor portion as a position reference A method for manufacturing a multilayer wiring board, comprising: a step of drilling the colored solder resist after the alignment and forming the opening.

  (2) In the method (1), the diameter of the center hole of the ring-shaped conductor is 500 μm or more and 1000 μm or less.

  (3) In (1) above, a product region in which the conductor circuit is formed and a frame region surrounding the product region, and the ring-shaped conductor is formed in the frame region. A method for producing a multilayer wiring board, which is characterized.

1 is a schematic plan view showing a multilayer wiring board according to an embodiment embodying the present invention. The principal part sectional view showing the multilayer wiring board of one embodiment which materialized the present invention. The top view which shows the ring-shaped conductor part of one Embodiment. Sectional drawing which shows the thickness of the ring-shaped conductor part, a conductor circuit, and the resin insulating layer which covers them. Sectional drawing for demonstrating the manufacturing method of the multilayer wiring board of one embodiment. Sectional drawing for demonstrating the manufacturing method of the multilayer wiring board of one embodiment. Sectional drawing for demonstrating the manufacturing method of the multilayer wiring board of one embodiment. Sectional drawing for demonstrating the manufacturing method of the multilayer wiring board of one embodiment. Sectional drawing for demonstrating the manufacturing method of the multilayer wiring board of one embodiment. Sectional drawing for demonstrating the manufacturing method of the multilayer wiring board of one embodiment. Sectional drawing for demonstrating the manufacturing method of the multilayer wiring board of one embodiment. Sectional drawing for demonstrating the manufacturing method of the multilayer wiring board of one embodiment. Explanatory drawing for demonstrating the manufacturing method of the multilayer wiring board of one Embodiment. Sectional drawing for demonstrating the manufacturing method of the multilayer wiring board of one embodiment. Explanatory drawing which shows the image of the ring-shaped conductor part in one embodiment. Explanatory drawing which shows the image of the positioning mark in a comparative example. Explanatory drawing which shows the image of the positioning mark in a comparative example. Sectional drawing which shows the detection method of the conventional alignment mark.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Multilayer wiring board 12 ... Core board 13 ... Upper surface as a core main surface 14 ... Lower surface as a core main surface 15, 16 ... Build-up layer as a laminated wiring part 20, 21, 31, 32 ... As an interlayer resin insulation layer Resin insulation layers 22, 23, 33, 34... Conductive layer 29, 36... Solder resist 30, 37... Opening 41 .. Frame-shaped conductor (ring-shaped conductor) as an alignment mark
56 ... Glass mask for exposure 220, 330 ... Conductor circuit 230 ... Terminal pad as conductor circuit 340 ... BGA pad as conductor circuit D1 ... Diameter of center hole L1 ... Light for position detection L2 ... Reflected light T3, T4 ... Solder Resist thickness W1 Width of frame-shaped conductor

Claims (8)

A core substrate having a core main surface, a plated metal layer and an interlayer resin insulating layer constituting a conductor circuit, and a laminated wiring portion disposed on the core main surface and a part of the plated metal layer are exposed. A manufacturing method of a multilayer wiring board comprising a colored solder resist having an opening to be disposed and disposed on the laminated wiring part,
The conductor circuit is formed by plating on the interlayer resin insulation layer, and a frame-shaped conductor portion thicker than the conductor circuit is aligned at a position different from the conductor circuit in the plated metal layer. A conductor forming step to be formed as a mark;
A solder resist forming step of forming the colored solder resist covering the conductor circuit and the frame-shaped conductor on the plated metal layer;
A detection step of detecting the frame-shaped conductor portion based on the reflected light of the position detection light irradiated to the frame-shaped conductor portion via the colored solder resist;
Drilled solder resist of the color after conducting alignment with said detected frame-shaped conductor portion as a position reference, see contains a drilling process for forming the opening,
In the solder resist forming step, the thickness of the colored solder resist just above the conductor circuit is made thicker than the thickness of the colored solder resist just above the frame-shaped conductor portion. > A method for producing a multilayer wiring board, characterized by:   The method for manufacturing a multilayer wiring board according to claim 1, wherein the frame-shaped conductor is a circular ring-shaped conductor in plan view.   The method for manufacturing a multilayer wiring board according to claim 1, wherein the frame-shaped conductor is 5 μm or more thicker than the conductor circuit.   The thickness of the colored solder resist around the conductor circuit is 10 μm or more, and the thickness of the colored solder resist just above the frame-shaped conductor is 5 μm or less. The method for producing a multilayer wiring board according to any one of 1 to 3. The difference between the thickness of the colored solder resist immediately above the conductor circuit and the thickness of the colored solder resist directly above the frame-shaped conductor is 5 μm or more. The method for producing a multilayer wiring board according to any one of 1 to 4.   6. The method of manufacturing a multilayer wiring board according to claim 1, wherein a width of the frame-shaped conductor portion is 10 μm or more.   7. The method for manufacturing a multilayer wiring board according to claim 1, wherein the width of the frame-shaped conductor portion is not less than 50 μm and not more than 250 μm.   In the drilling step, an exposure glass mask is disposed on the colored solder resist while performing alignment using the detected frame-shaped conductor portion as a position reference, and in this state, the exposure glass mask is interposed. The method for manufacturing a multilayer wiring board according to claim 1, wherein the colored solder resist is perforated to form the opening by performing exposure and further development. .