CN112505964B

CN112505964B - Light-emitting substrate, preparation method thereof and display device

Info

Publication number: CN112505964B
Application number: CN202011314977.2A
Authority: CN
Inventors: 张新秀; 谢晓冬; 桑华煜; 钟腾飞; 何敏; 赵雪; 张天宇
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2020-11-20
Filing date: 2020-11-20
Publication date: 2022-08-30
Anticipated expiration: 2040-11-20
Also published as: CN112505964A

Abstract

Disclosed herein are a light emitting substrate, a method of manufacturing the same, and a display device. The light-emitting substrate comprises a substrate and a film layer structure arranged on the substrate, the film layer structure comprises a first wiring layer, a shielding layer and a second wiring layer which are stacked along the direction far away from the substrate, the first wiring layer comprises a first alignment mark, the second wiring layer comprises a second alignment mark, the first alignment mark comprises an overlapping area overlapped with the second alignment mark and a non-overlapping area located on the periphery of the overlapping area, and the shielding layer at least covers the non-overlapping area. The non-overlapping area where the first alignment mark and the second alignment mark are not overlapped is covered by the shielding layer, so that the first alignment mark is prevented from being corroded and oxidized in the formation process of the second wiring layer, bubbling and peeling of a film layer are avoided, and the yield of products is improved.

Description

Light-emitting substrate, preparation method thereof and display device

Technical Field

The application relates to the technical field of display, in particular to a light-emitting substrate, a preparation method thereof and a display device.

Background

In the current era of the explosive growth of communication, display devices, such as mobile phones, personal digital assistants or smart phones, have become indispensable electronic products in modern life. Most of the conventional Display devices are Liquid Crystal Display (LCD) devices, which have many advantages such as thin body, power saving, and no radiation, and thus are widely used. Most of the existing liquid crystal display devices in the market are Backlight liquid crystal displays (lcds), which include a liquid crystal display panel and a Backlight Module (Backlight Module). A Mini light emitting diode (Mini LED) is a small LED with a size of around 100 microns.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

An embodiment of the present invention provides a light emitting substrate, including: the film layer structure comprises a first wiring layer, a shielding layer and a second wiring layer which are stacked along the direction far away from the substrate, the first wiring layer comprises a first alignment mark, the second wiring layer comprises a second alignment mark, the first alignment mark comprises an overlapping area overlapped with the second alignment mark and a non-overlapping area located on the periphery of the overlapping area, and the shielding layer at least covers the non-overlapping area.

In some exemplary embodiments, the shielding layer is provided with a first via hole exposing the overlapping region, and the orthographic projection of the second alignment mark on the substrate includes the orthographic projection of the first via hole on the substrate.

In some exemplary embodiments, an orthographic projection of the second alignment mark on the substrate completely overlaps with an orthographic projection of the first via on the substrate.

In some exemplary embodiments, the first wiring layer further includes a first wiring, the second wiring layer further includes a second wiring, the shielding layer is provided with a second via exposing the first wiring, an orthographic projection of the second via on the substrate includes an orthographic projection of the first wiring on the substrate, and an orthographic projection of the second alignment mark on the substrate includes an orthographic projection of the second via on the substrate overlapping.

In some exemplary embodiments, an orthographic projection of the second alignment mark on the substrate completely overlaps with an orthographic projection of the second via on the substrate.

In some exemplary embodiments, the second wiring covers the first wiring.

In some exemplary embodiments, the first wiring includes a first drive signal line, a first ground line, a first power supply line, and a first addressing line, the second wiring includes a second drive signal line, a second ground line, a second power supply line, and a second addressing line, the first drive signal line corresponds to a position of the second drive signal line and collectively constitutes the drive signal line, the first ground line corresponds to a position of the second ground line and collectively constitutes the ground line, the first power supply line corresponds to a position of the second power supply line and collectively constitutes the power supply line, and the first addressing line corresponds to a position of the second addressing line and collectively constitutes the addressing line.

In some exemplary embodiments, the driving signal lines, the ground lines, the addressing lines, and the power lines include a plurality of groups arranged in a first direction, the driving signal lines, the ground lines, the addressing lines, and the power lines of at least one of the plurality of groups extend in the first direction and are arranged at intervals in a second direction, the first and second alignment marks are arranged between adjacent groups or in an area of the intervals between the driving signal lines, the ground lines, the addressing lines, and the power lines, and the first direction and the second direction intersect.

In some exemplary embodiments, the film structure further includes an insulating layer disposed at a side of the second wiring layer away from the substrate and a pad layer disposed at a side of the insulating layer away from the second wiring layer, the pad layer including a plurality of pad groups, at least one of the plurality of pad groups including a first pad group for binding the driving chip and a second pad group for binding the light emitting cell, the first pad group including a first pad, a second pad, a third pad and a fourth pad, the second pad group including a fifth pad and a sixth pad, the insulating layer being provided thereon with a ground via hole exposing the ground line, a power via hole exposing the power line, a driving via hole exposing the driving signal line and an addressing via hole exposing the addressing line, the first pad being connected with the fifth pad, the sixth pad being connected with the driving signal line through the driving via hole, the second pad being connected with the ground line through the ground via hole, the third pad being connected with the power line through the power via hole, the fourth pad is connected with the addressing line through the addressing through hole.

In some exemplary embodiments, at least one of the plurality of pad groups includes a plurality of second pad groups connected in series, a fifth pad of the second pad group located at the head end is connected to the first pad, and a sixth pad of the second pad group located at the tail end is connected to the driving signal line.

In some exemplary embodiments, the orthographic projections of the pads of the first and second pad groups on the substrate do not overlap with the orthographic projections of the first and second routing lines on the substrate.

In some exemplary embodiments, the film structure further includes a buffer layer disposed on a side of the first wiring layer adjacent to the substrate.

The embodiment of the invention also provides a display device which comprises the light-emitting substrate provided by the embodiment.

The embodiment of the invention also provides a preparation method of the light-emitting substrate, which comprises the following steps:

the method comprises the steps of forming a film layer structure on a substrate, wherein the film layer structure comprises a first wiring layer, a shielding layer and a second wiring layer which are stacked along the direction far away from the substrate, the first wiring layer comprises a first alignment mark, the second wiring layer comprises a second alignment mark, the first alignment mark comprises an overlapping area overlapped with the second alignment mark and a non-overlapping area located on the periphery of the overlapping area, and the shielding layer at least covers the non-overlapping area.

In some exemplary embodiments, forming a film structure on a substrate includes:

forming a first wiring layer on a substrate, the first wiring layer including a first alignment mark and a first wiring;

coating a negative photoresist on one side of the first wiring layer, which is far away from the substrate, and forming a shielding layer after masking, exposing and developing by using a mask plate, wherein a first through hole for exposing an overlapping region of the first alignment mark and a second through hole for exposing the first wiring are arranged on the shielding layer, and the orthographic projection of the second through hole on the substrate comprises the orthographic projection of the first wiring on the substrate;

depositing a metal film on one side of the shielding layer far away from the first wiring layer, coating a positive photoresist on one side of the metal film far away from the shielding layer, and forming a second wiring layer by adopting the same mask plate for forming the shielding layer after a patterning process, wherein the second wiring layer comprises a second alignment mark and second wiring, the orthographic projection of the second alignment mark on the substrate is completely overlapped with the orthographic projection of the first via hole on the substrate, the orthographic projection of the second wiring on the substrate is completely overlapped with the orthographic projection of the second via hole on the substrate, and the second wiring covers the first wiring.

The embodiment of the invention provides a light-emitting substrate, a preparation method thereof and a display device, wherein a non-overlapping area where a first alignment mark and a second alignment mark are not overlapped is covered by a shielding layer, so that the first alignment mark is prevented from being corroded and oxidized in the formation process of a second wiring layer, the bubbling and peeling of a film layer are avoided, and the yield of products is improved.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Other aspects will be apparent upon reading and understanding the attached figures and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.

FIG. 1 is a schematic view of a light-emitting substrate;

FIG. 2a is a diagram of the structure of a first alignment mark and a second alignment mark;

FIG. 2b is a cross-sectional view taken at the location A-A in FIG. 2 a;

FIG. 2c is an electron microscope image of the first alignment mark stripped after etching and oxidation;

fig. 3 is a structural view of a light emitting substrate according to an exemplary embodiment of the present invention;

FIG. 4a is an enlarged view of position B of FIG. 3;

FIG. 4b is a cross-sectional view taken at the location A-A in FIG. 4 a;

FIG. 5 is a cross-sectional view taken at the location A-A in FIG. 3;

fig. 6a is a structural diagram after a first wiring layer is formed in accordance with an exemplary embodiment of the present invention;

FIG. 6b is a cross-sectional view taken at the location A-A in FIG. 6 a;

FIG. 6c is an enlarged view of position B of FIG. 6 a;

FIG. 6d is a cross-sectional view taken at the location A-A in FIG. 6 c;

FIG. 7a is a block diagram of a barrier layer formed in accordance with an exemplary embodiment of the present invention;

FIG. 7b is a cross-sectional view taken at the location A-A in FIG. 7 a;

FIG. 7c is an enlarged view of position B of FIG. 7 a;

FIG. 7d is a cross-sectional view taken at the location A-A in FIG. 7 c;

FIG. 8a is a block diagram of a barrier layer formed in accordance with an exemplary embodiment of the present invention;

FIG. 8b is a cross-sectional view taken at the location A-A in FIG. 8 a;

FIG. 8c is an enlarged view of position B of FIG. 8 a;

FIG. 8d is a cross-sectional view taken at the location A-A in FIG. 8 c;

FIG. 9a is a block diagram after via formation in accordance with an exemplary embodiment of the present invention;

FIG. 9b is a cross-sectional view taken at location A-A of FIG. 9 a;

FIG. 10a is a block diagram after via formation in accordance with an exemplary embodiment of the present invention;

fig. 10b is a cross-sectional view at the position a-a in fig. 10 a.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

In the drawings, the size of constituent elements, the thickness of layers, or regions may be exaggerated for clarity. Thus, any one implementation of the present disclosure is not necessarily limited to the dimensions shown in the figures, and the shapes and sizes of the components in the figures are not intended to reflect actual proportions. Further, the drawings schematically show ideal examples, and any one implementation of the present disclosure is not limited to the shapes, numerical values, or the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", etc. are provided to avoid confusion among the constituent elements, and are not limited in number.

Herein, for convenience, the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate orientations or positional relationships, are used to describe positional relationships of constituent elements with reference to the accompanying drawings, merely for convenience of describing embodiments and simplifying description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present disclosure. The positional relationship of the constituent elements may be appropriately changed according to the directions of the described constituent elements. Therefore, the words described herein are not limited to the words described herein, and may be replaced as appropriate.

Herein, "the forward projection of a includes the forward projection of B," means that the boundary of the forward projection of B falls within the boundary range of the forward projection of a, or the boundary of the forward projection of a overlaps with the boundary of the forward projection of B.

When the light-emitting substrate comprising the Mini-LEDs is applied to the backlight module, the thickness increase of the liquid crystal display device can be reduced while the narrow frame is realized. Since the light emitting substrate includes the driving structure layer, the Mini-LED needs to be bonded and connected with the corresponding pad on the driving structure layer. The inventors have found that, when the drive structure layer is a multilayer structure, the drive structure layer has problems of swelling and interlayer peeling.

Fig. 1 is a schematic structural diagram of a light-emitting substrate. The light emitting substrate 1 includes a substrate 10 and a film structure disposed on the substrate 10. The film structure includes a driving structure layer 20, and a light emitting unit 30 and a driving chip 40 disposed on one side of the driving structure layer 20 away from the substrate 10, where the light emitting unit 30 may be a Mini LED. The driving structure layer 20 includes a wiring layer 21, an insulating layer 22, and a pad layer 23, which are stacked. The light emitting unit 30 and the driving chip 40 are both bound to the pad layer 23. The wiring layer 21 mainly includes a driving signal line (VLED) for driving the light emitting unit 30, a ground line (GND), a power supply line (PWR) for driving the driving chip 40, and an addressing line (ADD). The wiring layer 21 may employ metal. In order to avoid that the light emitting unit 30 and the driving chip 40 at the far end cannot be driven due to voltage drop during voltage transmission, and the driving signal line and the power line need to have higher conductivity, a way of increasing the conductivity of the driving signal line and the power line is to increase the thickness of the wiring layer 21, and in order to meet the requirement of conductivity, the thickness of the wiring layer 21 needs to reach 1.8 micrometers to 2.7 micrometers. Since the thickness of the metal film in one sputtering process can only reach 0.9 μm, the wiring layer 21 needs to be patterned at least twice, that is, the wiring layer 21 may include the first wiring layer 24 and the second wiring layer 25. The pattern of the first wiring layer 24 and the pattern of the second wiring layer 25 are substantially the same, and the functions of the first wiring layer 24 and the second wiring layer 25 are the same. First wiring layer 24 and second wiring layer 25 are approximately 0.9 microns thick. Each of the first wiring layer 24 and the second wiring layer 25 may be a MoNb/Cu multilayer composite structure.

Fig. 2a is a structural diagram of a first alignment mark and a second alignment mark, fig. 2b is a cross-sectional view of a position a-a in fig. 2a, and fig. 2c is an electron microscope image of a film layer peeled after the first alignment mark is etched and oxidized. As shown in fig. 2a, in the patterning process of the second wiring layer 25, alignment and Overlay (Overlay) deviation control needs to be performed with the pattern of the first wiring layer 24, so that a first alignment mark 241 needs to be formed after the first wiring layer 24 is patterned, the first alignment mark 241 may be in a cross shape, a mark aligned with the first alignment mark is provided on a mask used in the patterning process of the second wiring layer 25, the mark forms a second alignment mark 251 of the second wiring layer 25, and the second alignment mark 251 may be in a diamond shape. As shown in fig. 2b, since the second alignment mark 251 cannot cover the first alignment mark 241, MoNb and a portion of copper on the surface of the uncovered first alignment mark 241 are etched away in the wet etching process of the second wiring layer 25, the surface of the first alignment mark 241 becomes uneven and is easily oxidized in air, and as shown in fig. 2c, the subsequent high temperature process easily causes bubbling and film peeling in the peripheral regions of the first alignment mark 241 and the second alignment mark 251, thereby causing product defects. When a large plate is spliced and exposed, the alignment marks at the splicing position of the mask plate are more, and the problems of bubbling and film layer stripping are more serious. Large panel tiling means that the substrate size is large, e.g., 1500 mm × 1100 mm, and the mask size is small, e.g., 750 mm × 1100 mm, so that when the film layer on the large panel needs to be masked and exposed, the mask panel needs to be tiled to match the size of the substrate 10.

The embodiment of the invention provides a light-emitting substrate which comprises a substrate and a film layer structure arranged on the substrate, wherein the film layer structure comprises a first wiring layer, a shielding layer and a second wiring layer which are overlapped far away from the substrate, the first wiring layer comprises a first alignment mark, the second wiring layer comprises a second alignment mark, the first alignment mark comprises an overlapping area overlapped with the second alignment mark and a non-overlapping area located on the periphery of the overlapping area, and the shielding layer at least covers the non-overlapping area.

The embodiment of the invention provides a light-emitting substrate which comprises a substrate and a film layer structure arranged on the substrate, wherein the film layer structure comprises a first wiring layer, a shielding layer and a second wiring layer which are stacked far away from the substrate, the first wiring layer comprises a first alignment mark, the second wiring layer comprises a second alignment mark, and a non-overlapping area where the first alignment mark and the second alignment mark are not overlapped is covered by the shielding layer, so that the first alignment mark is prevented from being corroded and oxidized in the process of forming the second wiring layer, the bubbling and peeling of the film layer are avoided, and the yield of products is improved.

The following describes an exemplary embodiment of a light-emitting substrate according to the present invention with reference to the drawings.

Fig. 3 is a structural view of a light emitting substrate according to an exemplary embodiment of the present invention, fig. 4a is an enlarged view of a position B in fig. 3, and fig. 4B is a cross-sectional view of a position a-a in fig. 4 a. As shown in fig. 3, 4a and 4b, the light emitting substrate 1 includes a substrate 10 and a film structure disposed on the substrate 10, the film structure includes a driving structure layer 20, and a light emitting unit 30 and a driving chip 40 disposed on one side of the driving structure layer 20 away from the substrate 10, the driving structure layer 20 includes a driving circuit, both the light emitting unit 30 and the driving chip 40 are connected to the driving circuit, and the driving chip 40 controls the light emitting unit 30 to be turned on or turned off through the driving circuit. The drive structure layer 20 includes a wiring layer 21, and the wiring layer 21 mainly includes a drive signal line 211, a ground line 212, a power supply line 213, and an addressing line 214, and a bonding pin (not shown in the drawings). The wiring layer 21 includes a first wiring layer 24, a shielding layer 26 and a second wiring layer 25 stacked in a direction away from the substrate 10, the first wiring layer 24 includes a first alignment mark 241, the first alignment mark 241 may be in a # -shape, the second wiring layer 25 includes a second alignment mark 251, the second alignment mark 251 may be in a diamond-shape, centers of the first alignment mark 241 and the second alignment mark 251 are opposite, and sides of the # -shape and sides of the diamond-shape correspondingly intersect. Accordingly, the first alignment mark 241 includes an overlapping region 241a overlapping with the second alignment mark 251 and a non-overlapping region 241b located at the periphery of the overlapping region 241a, and the shielding layer 26 covers at least the non-overlapping region 241 b.

The embodiment of the invention provides a light-emitting substrate 1, which comprises a substrate 10 and a film layer structure arranged on the substrate 10, wherein the film layer structure comprises a first wiring layer 24, a shielding layer 26 and a second wiring layer 25 which are stacked, the first wiring layer 24 comprises a first alignment mark 241, the second wiring layer 25 comprises a second alignment mark 251, and a non-overlapping region 241b where the first alignment mark 241 and the second alignment mark 251 are not overlapped is covered by the shielding layer 26, so that the first alignment mark 241 is prevented from being corroded and oxidized in the formation process of the second wiring layer 25, bubbling and film layer stripping in the subsequent process are avoided, and the yield of products is improved.

In some exemplary embodiments, the shielding layer 26 is provided with a first via hole exposing the overlapping area 241a of the first alignment mark 241, and the orthographic projection of the second alignment mark 251 on the substrate 10 includes the orthographic projection of the first via hole on the substrate 10. In another exemplary embodiment, an orthographic projection of the first via on the substrate 10 completely overlaps with an orthographic projection of the second alignment mark 251 on the substrate 10, i.e., the first via and the second alignment mark 251 are identical in shape and correspond in position. The complete overlap is understood herein to be substantially complete overlap, subject to process variations and process variations.

In some exemplary embodiments, the shielding layer 26 covers the overlapping area 241 a. The shielding layer 26 is made of a transparent material, and the shielding layer 26 covers the overlapping region 241a and the non-overlapping region 241b of the first alignment mark 241, so that the alignment mark on the mask (transferred to the substrate to form the second alignment mark 251) and the first alignment mark 241 are not affected in alignment.

Fig. 5 is a cross-sectional view taken at the position a-a in fig. 3. In some exemplary embodiments, the first wiring layer 24 further includes a first wiring 242, the second wiring layer 25 further includes a second wiring 252, a second via exposing the first wiring 242 is disposed on the shielding layer 26, an orthographic projection of the second via on the substrate 10 includes an orthographic projection of the first wiring 242 on the substrate 10, and an orthographic projection of the second alignment mark 252 on the substrate 10 includes an orthographic projection of the second via on the substrate 10. In another exemplary embodiment, an orthogonal projection of the second wire 252 on the substrate 10 completely overlaps an orthogonal projection of the second via on the substrate 10. The second wiring 252 is connected to the first wiring 242 through the second via hole, and the second wiring 252 covers the first wiring 242.

As shown in fig. 3 and 5, in an exemplary embodiment, the first wiring 242 includes a first driving signal line 243, a first ground line 244, a first power line 245, and a first addressing line 246, the second wiring 252 includes a second driving signal line 253, a second ground line 254, a second power line 255, and a second addressing line 256, the first driving signal line 243 corresponds in position to the second driving signal line 253, the first ground line 244 corresponds in position to the second ground line 254, the first power line 245 corresponds in position to the second power line 255, and the first addressing line 246 corresponds in position to the second addressing line 256. The driving signal line 211 includes a first driving signal line 243 and a second driving signal line 253, the ground line 212 includes a first ground line 244 and a second ground line 254, the power line 213 includes a first power line 245 and a second power line 255, the addressing line 214 includes a first addressing line 246 and a second addressing line 25, in other words, the first driving signal line 243 and the second driving signal line 253 correspond in position and jointly constitute the driving signal line 211, the first ground line 244 and the second ground line 254 correspond in position and jointly constitute the ground line 212, the first power line 245 and the second power line 255 correspond in position and jointly constitute the power line 213, and the first addressing line 246 and the second addressing line 256 correspond in position and jointly constitute the addressing line 214. The first wiring 242 and the second wiring 252 have the same function, and the first wiring 242 and the second wiring 252 can increase the thickness of the wiring, overcome the limitation on the thickness of a coating process, increase the conductivity of the wiring, and reduce the voltage drop generated during voltage transmission.

In some exemplary embodiments, as shown in fig. 3, the driving signal line 211, the ground line 212, the addressing line 214, and the power supply line 213 include a plurality of sets arranged along the first direction X, and the driving signal line 211, the ground line 212, the addressing line 214, and the power supply line 213 of at least one of the plurality of sets of the driving signal line 211, the ground line 212, the addressing line 214, and the power supply line 213 extend along the second direction Y and are arranged at intervals along the first direction X, wherein in the first direction X, an interval between the ground line 212 and the addressing line 214 is greater than an interval between the driving signal line 211 and the ground line 212 and greater than an interval between the addressing line 214 and the power supply line 213, and an interval between the driving signal line 211 and the ground line 212 and an interval between the addressing line 214 and the power supply line 213 are approximately equal. In the second direction Y, the width of the driving signal line 211 is substantially equal to the width of the ground line 212, the width of the addressing line 214 is substantially equal to the width of the power line 213, and the width of the driving signal line 211 is greater than the width of the power line 213. The first and second alignment marks 241 and 251 are disposed between adjacent sets of the driving signal line 211, the ground line 212, the addressing line 214, and the power supply line 213, or in a region spaced between the driving signal line 211, the ground line 212, the addressing line 214, and the power supply line 213.

In some exemplary embodiments, the first alignment mark 241 and the corresponding second alignment mark 251 constitute one pair, and the light emitting substrate 1 includes a plurality of pairs spaced in the second direction Y and/or a plurality of pairs spaced in the first direction X.

In some exemplary embodiments, the light emitting substrate includes a display region and a peripheral region located at a periphery of the display region, and the first alignment mark and the second alignment mark may be disposed at the peripheral region.

In some exemplary embodiments, as shown in fig. 3 and 5, the driving structure layer 20 further includes an insulating layer 22 disposed on a side of the second wiring layer 25 away from the substrate 10 and a pad layer 23 disposed on a side of the insulating layer 22 away from the second wiring layer 25, the pad layer 23 including a plurality of pad groups 23 a. Each set of the driving signal lines 211, the ground lines 212, the addressing lines 214, and the power supply lines 213 may be provided with a plurality of sets of the pad groups 23a in the second direction Y. At least one of the plurality of pad groups 23a includes a first pad group 23a1 for binding the driving chip 40 and a second pad group 23a2 for binding the light emitting cell 30. The first pad group 23a1 includes a first pad 231, a second pad 232, a third pad 233, and a fourth pad 234, the second pad group 23a2 includes a fifth pad 235 and a sixth pad 236, the insulating layer 22 is provided with a ground via hole exposing the ground line 212, a power via hole exposing the power line 213, a driving via hole exposing the driving signal line 211, and an address via hole exposing the address line 214, the first pad 231 is connected to the fifth pad 235, the sixth pad 236 is connected to the driving signal line 211 through the driving via hole, the second pad 232 is connected to the ground line 212 through the ground via hole, the third pad 233 is connected to the power line 213 through the power via hole, and the fourth pad 234 is connected to the address line 214 through the address via hole. In an exemplary embodiment, the pad layer further includes a connection line 237 connecting between pads and connecting the pads with corresponding wirings (the second driving signal line 253, the second ground line 254, the second address line 256, the second power supply line 255, and the like). The orthographic projections of the pads of the first and second pad groups 23a1 and 23a2 on the substrate 10 do not overlap with the orthographic projections of the first and

second routing wires

242 and 252 on the substrate 10. The orthographic projection of the pads of the first pad group 23a1 on the substrate 10 is between the orthographic projections of the ground line 212 and the addressing line 214 on the substrate 10.

In some exemplary embodiments, at least one of the plurality of pad groups 23a includes a plurality of second pad groups 23a2, the plurality of second pad groups 23a2 are connected in series, the fifth pad 235 of the second pad group 23a2 located at the head end is connected to the first pad 231, and the sixth pad 236 of the second pad group 23a2 located at the tail end is connected to the driving signal line 211 through a driving via. In an exemplary embodiment, the plurality of second pad groups 23a2 may include four second pad groups 23a2, the second pad groups 23a2 enclose a rectangle and are located at corner positions of the rectangle, the first pad group 23a1 is located outside one side of the rectangle, one of two second pad groups 23a2 constituting the side is set as the second pad group 23a2 at the head end, one is set as the second pad group 23a2 at the tail end, and the adjacent light emitting cell 30 groups are connected in series by a connection line 237.

In some exemplary embodiments, the driving structure layer 20 further includes a protective layer 27 disposed on a side of the pad layer 23 away from the insulating layer 22, and pad vias exposing pads of the second pad group 23a2 and the first pad group 23a1 are disposed on the protective layer 27. The material of the protective layer 27 includes, but is not limited to, silicon nitride Si _x N _y Silicon oxide SiO _x And silicon carbide SiC.

In some exemplary embodiments, the driving structure layer 20 further includes a buffer layer 28, and the buffer layer 28 is disposed on a side of the wiring layer 21 close to the substrate 10. The material of the buffer layer 28 includes, but is not limited to, silicon nitride Si _x N _y Silicon oxide SiO _x And silicon carbide SiC, the buffer layer 28 can buffer stress generated during formation of the wiring layer 21, preventing stress-induced chipping.

The following is an exemplary description of the manufacturing process of the light emitting substrate. The "patterning process" mentioned in this application refers to processes of coating a photoresist, exposing a mask, developing, etching, and stripping the photoresist for a metal material, an inorganic material, or a transparent conductive material, where the deposition may be any one or more of sputtering, evaporation, and chemical vapor deposition, and the etching may be any one or more of dry etching and wet etching, and this application is not limited. "thin film" refers to a layer of a material deposited, coated, or otherwise formed on a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as "thin film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern".

(1) A first wiring layer 24 pattern is formed. Forming the first wiring layer 24 pattern includes: a buffer film and a first metal thin film are sequentially deposited on the substrate 10, and after a patterning process, as shown in fig. 6a to 6d, a first wiring layer 24 pattern and a buffer layer 28 are formed. The first wiring layer 24 pattern includes a first alignment mark 241 and a first wiring 242, the first wiring 242 includes a plurality of sets of first driving signal lines 243, first ground lines 244, first addressing lines 246, and first power supply lines 245 arranged at intervals in a first direction, and the first driving signal lines 243, the first ground lines 244, the first addressing lines 246, and the first power supply lines 245 of at least one of the plurality of sets extend in a second direction Y and are arranged at intervals in the first direction X. The first alignment mark 241 is disposed between adjacent first driving signal line 243, first ground line 244, first addressing line 246, and first power line 245 groups, and the first alignment mark 241 may be plural and disposed at intervals along the second direction Y. The first alignment mark 241 is a well-shaped mark. In the first direction X, the width of the first driving signal line 243 is substantially equal to the width of the second ground line 254, the width of the first addressing line 246 is substantially equal to the width of the first power supply line 245, and the width of the first driving signal line 243 is greater than the width of the first power supply line 245. The thickness of the first wiring layer 24 is 0.6 micrometers to 0.95 micrometers. Fig. 6a is a structural diagram after a first wiring layer is formed according to an exemplary embodiment of the present invention, fig. 6B is a cross-sectional view of a position a-a in fig. 6a, fig. 6c is an enlarged view of a position B in fig. 6a, and fig. 6d is a cross-sectional view of a position a-a in fig. 6 c.

(2) A masking layer 26 pattern is formed. Forming the pattern of the shielding layer 26 includes: a negative photoresist is coated on the substrate 10 on which the patterns are formed, and after masking, exposure and development are performed using a mask, the exposed portions remain, as shown in fig. 7a to 7d, to form a pattern of the shielding layer 26. The shielding layer 26 is provided thereon with a first via hole k1 exposing an overlapping region 241a where the first alignment mark 241 overlaps with a subsequent second alignment mark 251, and a second via hole k2 exposing the first wiring 242. The orthographic projection of the first via hole k1 on the substrate 10 is a diamond shape. The orthographic projection of the second via k2 on the substrate 10 includes the orthographic projection of the first wiring 242 on the substrate 10. The width D1 of the second via k2 is greater than the line width D2 of the first wire 242. The thickness of the shielding layer is 0.5 to 10 micrometers. Fig. 7a is a structural diagram after forming a blocking layer according to an exemplary embodiment of the present invention, fig. 7B is a cross-sectional view taken at a position a-a in fig. 7a, fig. 7c is an enlarged view taken at a position B in fig. 7a, and fig. 7d is a cross-sectional view taken at a position a-a in fig. 7 c.

In some exemplary embodiments, the light emitting substrate 1 is cut from a light emitting motherboard, or after the substrate 10 forms a driving structure layer, the edge of the substrate 10 needs to be cut. In the cutting process, in order to avoid laser damage, a film layer structure is not arranged within 500 micrometers of the cutting line. Therefore, in the masking and exposure processes of the shielding layer 26, a baffle needs to be arranged at a position corresponding to the cutting line, and the negative photoresist at the position of the baffle is removed after development.

(3) A second wiring layer 25 pattern is formed. Forming the second wiring layer 25 pattern includes: a second metal thin film is deposited on the substrate 10 on which the aforementioned pattern is formed, a positive photoresist is coated, the same mask that forms the blocking layer is used, and after the patterning process, as shown in fig. 8a to 8d, a pattern of a second wiring layer 25 is formed. The second wiring layer 25 pattern includes a second alignment mark 251 and a second wiring 252. Since the same second mask is used for the shielding layer and the second wiring layer, the orthographic projection of the second alignment mark 251 on the substrate 10 completely overlaps with the orthographic projection of the first via hole on the substrate 10. An orthogonal projection of the second wire 252 on the substrate 10 completely overlaps an orthogonal projection of the second via on the substrate 10, and the second wire 252 covers the first wire 242. The second wiring 252 includes a plurality of sets of second driving signal lines 253, second ground lines 254, second addressing lines 256, and second power supply lines 255, and the second driving signal lines 253, the second ground lines 254, the second addressing lines 256, and the second power supply lines 255 of at least one of the plurality of sets of second driving signal lines 253, the second ground lines 254, the second addressing lines 256, and the second power supply lines 255 extend in the second direction Y and are arranged at intervals in the first direction X. The second drive signal line 253 corresponds to the first drive signal line 243 and collectively constitutes the drive signal line 211, the second ground line 254 corresponds to the first ground line 244 and collectively constitutes the ground line 212, the second power supply line 255 corresponds to the first power supply line 245 and collectively constitutes the power supply line 213, and the second addressing line 256 corresponds to the first addressing line 246 and collectively constitutes the addressing line 214. The thickness of the second wiring layer 25 is 0.6 to 0.95 micrometers. Fig. 8a is a structural view after a shielding layer is formed according to an exemplary embodiment of the present invention, fig. 8B is a cross-sectional view of a position a-a in fig. 8a, fig. 8c is an enlarged view of a position B in fig. 8a, and fig. 8d is a cross-sectional view of a position a-a in fig. 8 c.

In some exemplary embodiments, using the second mask, after the patterning process, forming the second wiring layer 25 pattern may include:

and coating a positive photoresist on the second metal film, developing an exposure area of the positive photoresist after exposure and development by using the same mask plate mask for forming the shielding layer to expose the second metal film, etching the exposed second metal film by using a wet etching process, removing the positive photoresist, and forming a second wiring layer 25 pattern. Due to the fact that the shielding layer 26 is arranged between the exposed second metal film and the first wiring layer 24, in the process of etching the exposed second metal film, the first wiring layer 24 is isolated from the etching solution by the shielding layer 26, and therefore the non-overlapping region 241b where the first alignment mark 241 and the second alignment mark 251 are not overlapped is not etched, the first alignment mark 241 is protected, and further the first alignment mark 241 is prevented from being oxidized in the subsequent process.

(4) A plurality of via patterns are formed. Forming a plurality of via patterns includes: an insulating film is deposited on the substrate 10 on which the aforementioned patterns are formed, and after a patterning process, a plurality of via hole patterns are formed as shown in fig. 9a and 9 b. The plurality of via patterns include a driving via k3, an address via k4, a ground via k5, and a power via k 6. The driving via k3 exposes the second driving signal line 253, the ground via k4 exposes the second ground line 254, the power via k5 exposes the second power line 255, and the address via k6 exposes the second address line 256. Fig. 9a is a structural diagram after a via hole is formed according to an exemplary embodiment of the present invention, and fig. 9b is a cross-sectional view at a-a position in fig. 9 a.

(5) A pad layer 23 is patterned. Patterning the pad layer 23 includes: on the substrate 10 with the aforementioned pattern, a third metal film is deposited, and a pattern of a pad layer 23 is formed through a patterning process, as shown in fig. 10a to 10 b. The pad layer 23 pattern includes a plurality of pad groups 23 a. Each set of the driving signal lines 211, the ground lines 212, the addressing lines 214, and the power lines 213 may be provided with a plurality of sets of the pad groups 23a in the second direction Y. At least one of the plurality of pad groups 23a includes a first pad group 23a1 for binding a driving chip in a subsequent process and a plurality of second pad groups 23a2 for binding a light emitting unit in a subsequent process, the first pad group 23a1 includes a first pad 231, a second pad 232, a third pad 233, and a fourth pad 234, the second pad group 23a2 includes a fifth pad 235 and a sixth pad 236, the plurality of second pad groups 23a2 are connected in series, the fifth pad 235 of the second pad group 23a2 at the head end is connected to the first pad 231, the sixth pad 236 of the second pad group 23a2 at the tail end is connected to the driving signal line 211 through a driving via, the second pad 232 is connected to the ground line 212 through a ground via, the third pad 233 is connected to the power line 213 through a power via, and the fourth pad 234 is connected to the addressing line 214 through an addressing via. The pad layer 23 further includes connection pads and connection lines 237 connecting the pads to corresponding wirings (the second drive signal line 253, the second ground line 254, the second address line 256, the second power supply line 255, and the like). The pads of the first pad group 23a1 and the second pad group 23a2 are not overlapped in orthographic projection on the substrate 10 with the wiring of the wiring layer 21. The orthographic projection of the pads of the first pad group 23a1 on the substrate 10 is between the orthographic projections of the ground line 212 and the addressing line 214 on the substrate 10. Fig. 10a is a structural view after a via hole is formed according to an exemplary embodiment of the present invention, and fig. 10b is a cross-sectional view at a-a position in fig. 10 a.

(6) Forming a pad via pattern. Forming the pad via pattern includes: and depositing a protective film on the substrate 10 with the patterns, and forming a pad via hole pattern after a patterning process. The pad via pattern exposes the pads of the second pad group 23a2 and the first pad group 23a 1.

(7) The light emitting unit 30 and the driving chip 40 are bound. The light emitting unit 30 is bonded to the bonding pads of the corresponding second bonding pad group 23a2, and the driving chip 40 is bonded to the bonding pads of the corresponding first bonding pad group 23a1, so as to form the light emitting substrate 1 shown in fig. 3.

In some exemplary embodiments, the first and second routing layers further include a bonding pin, and before forming the pad via, further include: and forming a transparent conductive layer. Forming the transparent conductive layer includes: on the patterned substrate 10, a transparent conductive film is deposited, and a transparent conductive layer is formed through a patterning process. The transparent conductive layer covers the bonding pins. The transparent conductive layer can prevent the bonding pins from being oxidized in the subsequent process.

In some exemplary embodiments, the first, second, and third metal thin films may employ any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, MoNb/Cu, and the like. The transparent conductive film may be Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). The insulating film and the buffer film may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The light emitting unit may employ a Mini LED and a μ LED.

As shown in fig. 6a to 10b, the light emitting substrate 1 formed by the foregoing manufacturing process may include:

a substrate 10;

a buffer layer 28 disposed on the substrate 10;

a first wiring layer 24 disposed on a side of the buffer layer 28 away from the substrate 10, the first wiring layer 24 including a first alignment mark 241 and first wirings 242, the first alignment mark 241 including an overlapping region 241a overlapping with a subsequent second alignment mark 251 and a non-overlapping region 241b outside the overlapping region 241a, the first wirings 242 including a plurality of sets of first driving signal lines 243, first ground lines 244, first power supply lines 245 and first addressing lines 246 arranged at intervals along the first direction X, the first driving signal lines 243, the first ground lines 244, the first power supply lines 245 and the first addressing lines 246 of at least one of the plurality of sets extending along the second direction Y and arranged at intervals along the first direction X;

a shielding layer 26 disposed on a side of the first wiring layer 24 away from the buffer layer 28, wherein a first via k1 exposing the non-overlapping region 241b of the first alignment mark 241 and a second via k2 exposing the first wire 242 are disposed on the shielding layer 26, and an orthographic projection of the second via k2 on the substrate 10 includes an orthographic projection of the first wire 242 on the substrate 10;

a second wiring layer 25 disposed on a side of the shielding layer 26 away from the first wiring layer 24, the second wiring layer 25 including a second alignment mark 251 and a second wiring 252, an orthogonal projection of the second alignment mark 251 on the substrate 10 completely overlapping an orthogonal projection of the first via k1 on the substrate 10, an orthogonal projection of the second wiring 252 on the substrate 10 completely overlapping an orthogonal projection of the second via k2 on the substrate 10, the second wiring 252 covering the first wiring 242, the second wiring 252 including a plurality of sets of second driving signal lines 253, second ground lines 254, second addressing lines 256, and second power supply lines 255 disposed at intervals in the first direction X, the second drive signal lines 253, the second ground lines 254, the second addressing lines 256, and the second power supply lines 255 of at least one of the plurality of sets of the second drive signal lines 253, the second ground lines 254, the second addressing lines 256, and the second power supply lines 255 extend in the second direction Y and are arranged at intervals in the first direction X. The second drive signal line 253 corresponds to the first drive signal line 243 and collectively constitutes the drive signal line 211, the second ground line 254 corresponds to the first ground line 244 and collectively constitutes the ground line 212, the second power supply line 255 corresponds to the first power supply line 245 and collectively constitutes the power supply line 213, and the second address line 256 corresponds to the first address line 246 and collectively constitutes the address line 214;

the insulating layer 22 is arranged on one side of the second wiring layer 25 far away from the shielding layer 26, and a driving via k3 for exposing the second driving signal line 253, a grounding via k4 for exposing the second grounding line 254, a power via k5 for exposing the second power line 255 and an addressing via k6 for exposing the second addressing line 256 are arranged on the insulating layer 22;

and a pad layer 23 disposed on a side of the insulating layer 22 away from the second wiring layer 25, the pad layer 23 including a plurality of pad groups 23 a. Each set of the driving signal lines 211, the ground lines 212, the addressing lines 214, and the power lines 213 may be provided with a plurality of sets of the pad groups 23a in the second direction Y. At least one of the plurality of pad groups 23a includes a first pad group 23a1 and a plurality of second pad groups 23a2, the first pad group 23a1 includes a first pad 231, a second pad 232, a third pad 233, and a fourth pad 234, the second pad group 23a2 includes a fifth pad 235 and a sixth pad 236, the plurality of second pad groups 23a2 are connected in series, the fifth pad 235 of the second pad group 23a2 located at the head end is connected to the first pad 231, the sixth pad 236 of the second pad group 23a2 located at the tail end is connected to the driving signal line 211 through a driving via k3, the second pad 232 is connected to the ground line 212 through a ground via k4, the third pad 233 is connected to the power line 213 through a power via k5, and the fourth pad 234 is connected to the addressing line 214 through an addressing via k 6; the pad is connected to a corresponding pad or a corresponding wiring (the driving signal line 211, the ground line 212, the addressing line 214, the power supply line 213, and the like) by a connection line 237;

the protective layer 27 is arranged on one side of the second wiring layer 25 far away from the insulating layer 22, and a pad via hole for exposing the pads of the second pad group 23a2 and the first pad group 23a1 is arranged on the protective layer 27;

the light emitting cells 30 bound to the pads of the corresponding second pad group 23a2, and the driving chips 40 bound to the pads of the corresponding first pad group 23a 1.

As can be seen from the manufacturing process of the light-emitting substrate 1 according to the exemplary embodiment of the present invention, after the shielding layer 26 is formed, the non-overlapping region 241b where the first alignment mark 241 of the first wiring layer 24 and the second alignment mark 251 of the subsequent second wiring layer 25 do not overlap is covered by the shielding layer 26, and in the process of forming the second wiring layer 25, due to the shielding of the shielding layer 26, the etching solution does not contact the non-overlapping region 241b of the first alignment mark 241, while the overlapping region 241a of the first alignment mark 241 and the second alignment mark 251 forms a photoresist mask for the second wiring layer 25, so that the first alignment mark 241 is not etched by the etching solution, thereby preventing the first alignment mark 241 from being oxidized in the subsequent process, and preventing bubbling and film layer peeling during the subsequent high-temperature process. In addition, the shielding layer 26 and the second wiring layer 25 adopt the same mask plate, and although the process is increased by arranging the shielding layer, a new mask plate does not need to be opened, so that the cost of the mask plate is saved.

the method comprises the steps of forming a film layer structure on a substrate, wherein the film layer structure comprises a first wiring layer, a shielding layer and a second wiring layer which are overlapped along the direction far away from the substrate, the first wiring layer comprises a first alignment mark, the second wiring layer comprises a second alignment mark, the first alignment mark comprises an overlapping area overlapped with the second alignment mark and a non-overlapping area located on the periphery of the overlapping area, and the shielding layer at least covers the non-overlapping area.

The embodiment of the invention also provides a display device which comprises the light-emitting substrate provided by the embodiment. Display devices include, but are not limited to, cell phones, notebooks, tablets, and the like.

In the description of the present invention, it should be noted that the terms "upper", "lower", "one side", "the other side", "one end", "the other end", "side", "opposite", "four corners", "periphery", "mouth" structure ", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the structures referred to have specific orientations, are configured and operated in specific orientations, and thus, are not to be construed as limiting the present invention.

In the description of the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "connected," "directly connected," "indirectly connected," "fixedly connected," "mounted," and "assembled" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; the terms "mounted," "connected," and "fixedly connected" may refer to a direct connection, an indirect connection through intervening media, and a connection between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A light-emitting substrate, comprising: the film layer structure comprises a first wiring layer, a shielding layer and a second wiring layer which are stacked along the direction far away from the substrate, the first wiring layer comprises a first alignment mark, the second wiring layer comprises a second alignment mark, the first alignment mark comprises an overlapping area overlapped with the second alignment mark and a non-overlapping area located on the periphery of the overlapping area, and the shielding layer covers the non-overlapping area and a part of the overlapping area; the shielding layer is provided with a first via hole exposing the overlapping area, and the orthographic projection of the second alignment mark on the substrate comprises the orthographic projection of the first via hole on the substrate.

2. The light-emitting substrate according to claim 1, wherein: the orthographic projection of the second alignment mark on the substrate is completely overlapped with the orthographic projection of the first via hole on the substrate.

3. The luminescent substrate according to claim 1, wherein: the first wiring layer further comprises first wiring, the second wiring layer further comprises second wiring, a second through hole exposing the first wiring is arranged on the shielding layer, the orthographic projection of the second through hole on the substrate comprises the orthographic projection of the first wiring on the substrate, and the orthographic projection of the second alignment mark on the substrate comprises the orthographic projection of the second through hole on the substrate.

4. The light-emitting substrate according to claim 3, wherein: the orthographic projection of the second alignment mark on the substrate is completely overlapped with the orthographic projection of the second via hole on the substrate.

5. The light-emitting substrate according to claim 3, wherein: the second wiring covers the first wiring.

6. The light-emitting substrate according to claim 3, wherein: the first wiring includes first drive signal line, first earth connection, first power cord and first addressing line, the second wiring includes second drive signal line, second earth connection, second power cord and second addressing line, first drive signal line with second drive signal line position corresponds to constitute drive signal line jointly, first earth connection with second earth connection position corresponds to constitute the earth connection jointly, first power cord with second power cord position corresponds to constitute the power cord jointly, first addressing line with second addressing line position corresponds to constitute the addressing line jointly.

7. The light-emitting substrate according to claim 6, wherein: the drive signal line, the earth connection, the addressing line and the power cord include the multiunit that sets up along first direction, and at least a set of drive signal line, earth connection, addressing line and power cord extend and set up along first direction interval along the second direction in a plurality of groups, first counterpoint mark with the second counterpoint mark sets up between the adjacent group, or set up in the region of interval between drive signal line, earth connection, addressing line and the power cord, first direction with the second direction is crossing.

8. The light-emitting substrate according to claim 7, wherein: the film structure further comprises an insulating layer arranged on one side of the second wiring layer away from the substrate and a pad layer arranged on one side of the insulating layer away from the second wiring layer, wherein the pad layer comprises a plurality of pad groups, at least one of the pad groups comprises a first pad group for binding a driving chip and a second pad group for binding a light-emitting unit, the first pad group comprises a first pad, a second pad, a third pad and a fourth pad, the second pad group comprises a fifth pad and a sixth pad, the insulating layer is provided with a ground via hole for exposing the ground wire, a power via hole for exposing the power wire, a driving via hole for exposing the driving signal wire and an addressing via hole for exposing the addressing wire, the first pad is connected with the fifth pad, and the sixth pad is connected with the driving signal wire through the driving via hole, the second welding pad is connected with the grounding wire through the grounding via hole, the third welding pad is connected with the power line through the power supply via hole, and the fourth welding pad is connected with the addressing line through the addressing via hole.

9. The luminescent substrate according to claim 8, wherein: at least one of the plurality of welding pad groups comprises a plurality of second welding pad groups, the plurality of second welding pad groups are connected in series, the fifth welding pad of the second welding pad group positioned at the head end is connected with the first welding pad, and the sixth welding pad of the second welding pad group positioned at the tail end is connected with the driving signal wire.

10. The light-emitting substrate according to claim 8, wherein: the orthographic projections of the welding pads of the first welding pad group and the second welding pad group on the substrate are not overlapped with the orthographic projections of the first wiring and the second wiring on the substrate.

11. The light-emitting substrate according to any one of claims 1 to 10, wherein: the film layer structure further comprises a buffer layer, and the buffer layer is arranged on one side, close to the substrate, of the first wiring layer.

12. A display device comprising the light-emitting substrate according to any one of claims 1 to 11.

13. A method for preparing a light-emitting substrate, comprising:

forming a film layer structure on a substrate, wherein the film layer structure comprises a first wiring layer, a shielding layer and a second wiring layer which are stacked along a direction far away from the substrate, the first wiring layer comprises a first alignment mark, the second wiring layer comprises a second alignment mark, the first alignment mark comprises an overlapping area overlapped with the second alignment mark and a non-overlapping area located on the periphery of the overlapping area, the shielding layer covers the non-overlapping area and a part of the overlapping area, a first through hole exposing the overlapping area is arranged on the shielding layer, and the orthographic projection of the second alignment mark on the substrate comprises the orthographic projection of the first through hole on the substrate.

14. The method of claim 13, wherein forming a layer structure on a substrate comprises:

depositing a metal film on one side, far away from the first wiring layer, of the shielding layer, coating a positive photoresist on one side, far away from the shielding layer, of the metal film, forming a second wiring layer by using the same mask plate for forming the shielding layer after a patterning process, wherein the second wiring layer comprises a second alignment mark and second wiring, the orthographic projection of the second alignment mark on the substrate is completely overlapped with the orthographic projection of the first via hole on the substrate, the orthographic projection of the second wiring on the substrate is completely overlapped with the orthographic projection of the second via hole on the substrate, and the second wiring covers the first wiring.