CN114361188A - Display substrate, preparation method thereof and display device - Google Patents

Abstract

A display substrate comprises a display area and a peripheral area located on the periphery of the display area, wherein the peripheral area comprises a binding area, the binding area comprises a plurality of binding pins, the binding pins comprise at least one first power supply pin and at least one second power supply pin, the first power supply pin is used for transmitting a high power supply signal to the display area, and the second power supply pin is used for transmitting a low power supply signal to the display area; in a plane perpendicular to the display substrate, the display substrate comprises a substrate base plate, and a driving circuit layer and sub-pixels which are arranged on the substrate base plate, wherein the driving circuit layer comprises a semiconductor layer; the peripheral area further comprises at least one ground wire, the ground wire is coupled with the semiconductor layer, and the distance between the ground wire and the binding pins is larger than the width of a gap between every two adjacent binding pins. The flexible circuit board binding device avoids short circuit risks generated when the flexible circuit board is bound to generate deviation, and improves the service life and yield of products.

Description

Display substrate, preparation method thereof and display device

Technical Field

The present disclosure relates to but not limited to the field of display technologies, and in particular, to a display substrate, a method for manufacturing the same, and a display device.

Background

Micro Organic Light-Emitting diodes (Micro-OLEDs) are Micro displays that have been developed in recent years, and silicon-based Organic Light-Emitting diodes (OLEDs) are one of them. The silicon-based OLED has the characteristics of high pixel density (PPI), small volume and high contrast, is manufactured by adopting a mature integrated circuit Complementary Metal Oxide Semiconductor (CMOS) process, realizes active addressing of Pixels, can realize preparation of a plurality of functional circuits including a time sequence control (TCON) circuit, an Over Current Protection (OCP) circuit and the like on a silicon-based substrate, is favorable for reducing the system volume and realizes light weight. Silicon-based OLEDs are widely used in the field of Virtual Reality, Augmented Reality near-eye display, and in particular, in Augmented Reality (AR)/Virtual Reality (VR) head-mounted display devices.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

In a first aspect, an embodiment of the present disclosure provides a display substrate, including a display area and a peripheral area located around the display area, where the display area includes a plurality of sub-pixels, the peripheral area includes a binding area, the binding area includes a plurality of binding pins, the binding pins include at least one first power pin and at least one second power pin, the first power pin is configured to transmit a high power signal to the display area, and the second power pin is configured to transmit a low power signal to the display area;

in a plane perpendicular to the display substrate, the display substrate comprises a substrate, and a driving circuit layer and sub-pixels which are arranged on the substrate, wherein the driving circuit layer comprises a semiconductor layer; the peripheral area further comprises at least one ground wire, the ground wire is coupled with the semiconductor layer, and the distance between the ground wire and the binding pins is larger than the width of a gap between every two adjacent binding pins.

In an exemplary embodiment, the display substrate further includes a plurality of conductive layers disposed on the semiconductor layer;

the ground wire and at least one layer of the plurality of conducting layers are arranged in the same layer;

the plurality of bonding pins and at least one layer of the plurality of conductive layers are arranged in the same layer.

In an exemplary embodiment, the bonding pin is disposed on the same layer as the ground line.

In an exemplary embodiment, the bonding area is located on a first side of the peripheral area, the ground line includes at least a first portion, the first portion is also located on the first side of the peripheral area, and a distance between the first portion and the bonding pin is greater than a width of 50 sub-pixels along the first direction.

In an exemplary embodiment, the binding region is located at a first side of the peripheral region, and the ground line is located at any one, two, or three of the three sides of the peripheral region except the first side.

In an exemplary embodiment, a distance between the ground line and the display area is greater than a width of 50 sub-pixels in the first direction.

In an exemplary embodiment, a width of the bonding pin in the first direction is greater than a width of a gap between two adjacent bonding pins.

In an exemplary embodiment, the sub-pixel includes a first electrode including at least one transparent conductive oxide layer, an organic light emitting layer, and a second electrode;

each binding pin comprises a first sublayer and a second sublayer, the first sublayer and at least one of the plurality of conducting layers are arranged on the same layer, the second sublayer and the transparent conducting oxide layer are arranged on the same layer, the first sublayer and the second sublayer are connected in parallel and electrically, and the second sublayer is positioned on one side, far away from the substrate, of the first sublayer.

In an exemplary embodiment, the plurality of bonding pins are arranged along a first direction, a width of the second sub-layer along the first direction is the same as or approximately the same as a width of the first sub-layer along the first direction, a length of the second sub-layer along a second direction is between 1 and 1.2 times a length of the first sub-layer along the second direction, and the first direction intersects with the second direction.

In an exemplary embodiment, the first electrode further comprises at least one metal conductive layer;

the display substrate further comprises a plurality of test circuits, the test circuits are arranged on one sides, close to the display area, of the binding pins, the test circuits are not connected with the binding pins, and the distance between each test circuit and each binding pin is larger than the width of a gap between every two adjacent binding pins.

In an exemplary embodiment, the display substrate further includes a protection electrode, the protection electrode is disposed on a side of the plurality of test circuits away from the substrate, an orthogonal projection of the protection electrode on the substrate covers an orthogonal projection of the test circuit on the substrate, and the plurality of protection electrodes and the metal conductive layer are disposed in the same layer.

In an exemplary embodiment, the plurality of bonding pins further includes at least two impedance test pins located at both sides of the plurality of bonding pins along the first direction;

the first power supply pin comprises a first sub-pin and a second sub-pin, the second power supply pin comprises a third sub-pin and a fourth sub-pin, the third sub-pin and the fourth sub-pin are respectively adjacent to the impedance test pins on two sides of the plurality of binding pins along the first direction, the first sub-pin is located on one side, away from the impedance test pins, of the third sub-pin, and the second sub-pin is located on one side, away from the impedance test pins, of the fourth sub-pin.

In an exemplary embodiment, the plurality of bonding pins further includes at least one signal pin, the at least one signal pin being located between the first sub-pin and the second sub-pin.

In a second aspect, embodiments of the present disclosure provide a display device including the display substrate as described in any one of the above.

In a third aspect, an embodiment of the present disclosure provides a method for manufacturing a display substrate, where the display substrate includes a display area and a peripheral area located at a periphery of the display area, and the peripheral area includes a binding area, the method including:

forming a driving circuit layer on a substrate, wherein the driving circuit layer of the bonding region comprises a plurality of bonding pins, the plurality of bonding pins comprise at least one first power supply pin and at least one second power supply pin, the first power supply pin is used for transmitting a high power supply signal to the display region, and the second power supply pin is used for transmitting a low power supply signal to the display region; the driving circuit layer of the peripheral area comprises at least one ground wire, the driving circuit layer of the display area comprises a semiconductor layer, the ground wire is coupled with the semiconductor layer, and the distance between the ground wire and the binding pins is greater than the distance between two adjacent binding pins;

and forming sub-pixels on the driving circuit layer.

According to the display substrate, the manufacturing method thereof and the display device provided by the embodiment of the disclosure, the distance between the ground wire and the binding pins is larger than the distance between the two adjacent binding pins, so that the short circuit risk generated when the flexible circuit board is bound and deviated is avoided, the reliable electrical connection can be ensured under the condition that the size of the substrate is not changed, and the display substrate has the advantages of prolonging the service life of a product and improving the yield and the integration level of the product. In addition, no voltage drop exists between the binding pin and the ground wire, and chloride ions are not easy to gather at the binding pin during anodic etching, so that the problem that the binding pin is easy to corrode during anodic etching is solved, the problems that the binding pin is poor in electric connection performance and the reliability of the flexible circuit board module cannot meet requirements are solved, and the defect that the service life of the display substrate is not long in severe environment is overcome.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the present application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

Fig. 1a and 1b are schematic structural diagrams of display substrates in two examples of the embodiment of the disclosure;

FIG. 2 is a schematic diagram illustrating a substrate connected to a flexible circuit board according to an example of the disclosure;

FIG. 3 is a partial cross-sectional view of a display area in an example of an embodiment of the present disclosure;

FIG. 4 is a schematic plan view of a display substrate according to an example of the disclosure;

FIG. 5 is a schematic structural diagram of a binding region in an example of the embodiment of the present disclosure;

FIG. 6 is a cross-sectional comparison of the display area and the AA direction in FIG. 5.

Detailed Description

The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically stated or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate. Here, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having some kind of electrical action" is not particularly limited as long as it can transmit an electrical signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, another element having one or more functions, and the like.

In the drawings, the size of the constituent elements, the thickness of layers, or regions may be exaggerated for clarity. Therefore, one mode of the present disclosure is not necessarily limited to the dimensions, and the shape and size of each component in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

To maintain the following description of the embodiments of the present disclosure clear and concise, a detailed description of some known functions and components have been omitted from the present disclosure. The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

In a conventional silicon-based OLED display substrate, a common ground line is disposed on a side of a Bonding region away from a display region, and the common ground line is used for connecting the entire silicon substrate, but such a design may cause a Short circuit (Short) risk when a Flexible circuit board (FPC) Bonding (Bonding) is shifted. In addition, in the process of preparing the anode, Chlorine (CI) ions exist in an Indium Tin Oxide (ITO) etching solution, and the collected chloride ions corrode the bonding pins, so that the electrical connection characteristics of the bonding pins are deteriorated, which causes an increase in the contact resistance between the FPC and the silicon substrate, even a short circuit, and how to improve the reliability of the FPC module is a problem that needs to be paid attention to in the industry at present.

The embodiment of the disclosure provides a display substrate, which includes a display area and a peripheral area located at the periphery of the display area, wherein the display area includes a plurality of sub-pixels, the peripheral area includes a binding area, the binding area includes a plurality of binding pins, the plurality of binding pins include at least one first power supply pin and at least one second power supply pin, the first power supply pin is used for transmitting a high power supply signal to the display area, and the second power supply pin is used for transmitting a low power supply signal to the display area; in a plane perpendicular to the display substrate, the display substrate comprises a substrate base plate, and a driving circuit layer and sub-pixels which are arranged on the substrate base plate, wherein the driving circuit layer comprises a semiconductor layer; the peripheral area further comprises at least one ground wire, the ground wire is coupled with the semiconductor layer, and the distance between the ground wire and the binding pins is larger than the distance between two adjacent binding pins.

The display substrate provided by the embodiment of the disclosure, by making the distance between the ground wire and the binding pins larger than the distance between the two adjacent binding pins, avoids the short circuit risk generated when the flexible circuit board is bound and generates an offset, can ensure reliable electrical connection under the condition of ensuring that the size of the substrate is unchanged, and has the advantages of prolonging the service life of a product and improving the yield and the integration level of the product. In addition, voltage drop does not exist between the binding pins and the ground wire, and chloride ions are not easy to gather at the binding pins, so that the problem that the binding pins are easy to corrode in ITO anode etching is solved, the problems that the electric connection performance of the binding pins is poor and the reliability of an FPC module cannot meet requirements are solved, and the defect that the service life of a display substrate is not long in a severe environment is overcome.

The display substrate of the present disclosure is explained below with two examples.

Fig. 1a and 1b are schematic structural diagrams of a display substrate in a second example of the embodiment of the disclosure. As shown in fig. 1a and 1b, the display substrate includes a display region 101 and a peripheral region 102 located at the periphery of the display region 101, the peripheral region 102 includes a binding region 103, and the display region 101 includes a plurality of sub-pixels 105 arranged in an array. On a plane perpendicular to the display substrate, the display substrate includes: a silicon-based substrate 11, a driving circuit layer disposed on the silicon-based substrate 11, and a sub-pixel 105 disposed on the driving circuit layer. The binding region 103 includes a plurality of binding pins.

In the structures shown in fig. 1a and 1b, the length of the display substrate along the first direction X is greater than the length of the display substrate along the second direction Y, that is, in this example, the binding region 103 is arranged on one side of the long edge of the display substrate, and a layout mode of a long edge Pin (Pin) is adopted, so that the area on one side of the long edge is large, which is convenient for placing a circuit routing and Pin inserting test (Chip Probing, CP) structure and the like, and is beneficial to the matching design of the optical-mechanical structure.

In the structure shown in fig. 1a and 1b, the plurality of bonding pins include an impedance testing pin 1034, the impedance testing pin 1034 is located on two sides of the bonding region 103 along the first direction X, and the left and right sides are respectively provided with 2 impedance testing pins 1034 for monitoring the electrical contact characteristic between the display substrate and the FPC, which can also improve the mechanical characteristic, resist the external harsh environment, and the moisture in the external environment enters from the side and will first reach the impedance testing pin 1034, thereby prolonging the entering path of the moisture and being beneficial to prolonging the service life. The second power supply pin 1032 and the first power supply pin 1031 are sequentially arranged on the inner side of the impedance test pin 1034, 1 second power supply pin 1032 and 1 first power supply pin 1031 are respectively arranged on two sides of the impedance test pin 1034, the first power supply pin 1031 is used for inputting a high power supply signal VDD to the display region 101, and the second power supply pin 1032 is used for inputting a low power supply signal VSS to the display region 101. A bonding pin between the two first power supply pins 1031 is a signal pin 1033 for transmitting a driving signal.

In some exemplary embodiments, as shown in fig. 1a and 1b, the first power pin 1031 includes a first sub-pin 10311 and a second sub-pin 10312, the second power pin 1032 includes a third sub-pin 10321 and a fourth sub-pin 10322, the third sub-pin 10321 and the fourth sub-pin 10322 are respectively disposed adjacent to the impedance testing pin 1034 on the left and right sides, the first sub-pin 10311 is located on a side of the third sub-pin 10321 away from the impedance testing pin 1034, and the second sub-pin 10312 is located on a side of the fourth sub-pin 10322 away from the impedance testing pin 1034.

In some exemplary embodiments, as shown in fig. 1a and 1b, the peripheral region 102 further includes at least one ground lead 1021, and a distance d1 between the ground lead 1021 and the bonding pin is greater than a gap width d2 between two adjacent bonding pins.

Fig. 2 is a schematic diagram illustrating a flexible circuit board connected to a display substrate according to an example of the disclosure. The silicon substrate 11 is bound and connected with the flexible circuit board 20 through the binding pins of the binding region 103, and the flexible circuit board 20 can realize the electrical connection between the display substrate and an external circuit. A sub-pixel 105 is disposed on the silicon-based substrate 11, the sub-pixel 105 includes a plurality of light emitting elements, the plurality of light emitting elements emit light under the driving of the corresponding first and second electrodes, and the light emitting elements may be OLEDs. The cover glass 18 covers the sub-pixels 105, and light emitted from the plurality of light-emitting elements can be emitted after passing through the cover glass 18, and the cover glass 18 has a function of protecting the light-emitting elements. The size of the cover glass 18 is larger than that of the display area 101, the size of the cover glass 18 is smaller than that of the silicon-based substrate 11, and a certain distance is reserved between the four sides of the cover glass 18 and the silicon-based substrate 11 so as to be convenient for connecting the optical-mechanical structure. To achieve light transmission, the cover glass 18 may be made of a transparent material, such as: a mother glass having a high transmittance.

In this example, the size of the silicon substrate 11 is 11.1mm 9.5mm, the cover glass 18 is retracted 0.1mm and 10.9mm 9.3mm from the single side of the silicon substrate 11, and the size of the display area is retracted 0.5mm from the single side of the cover glass 18.

FIG. 3 is a partial cross-sectional view of a display area in an example of an embodiment of the present disclosure. As shown in fig. 3, the display area 101 includes, in a plane perpendicular to the display substrate: a driving circuit layer (not shown), a sub-pixel 105, a first thin film encapsulation layer 15, a color thin film layer 16, a second thin film encapsulation layer 17, and a cover glass 18, which are sequentially disposed on the silicon substrate 11. The sub-pixel 105 includes a plurality of light emitting elements. The sub-pixel 105 includes: a first electrode 12, an organic light emitting layer 13, and a second electrode 14 sequentially disposed on the driving circuit layer.

The first electrode 12 may be made of Indium Tin Oxide (ITO), and thus has the characteristics of high transmittance, high work function, and the like. The organic light emitting layer 13 may be made of an organic material, and holes and electrons are excited in the organic material to form excitons under the action of a voltage or a current applied to the first electrode 12 of the light emitting device and the second electrode 14 of the light emitting device, and the electrons and the holes are recombined to emit light. The second electrode 14 of the light emitting element may be made of a metal material or an alloy material, such as a metal or an alloy of magnesium or silver. A first thin film encapsulation layer 15 is disposed on an upper side of the second electrode 14, and a color thin film layer 16, which may include RGB color thin films, is disposed corresponding to the organic light emitting layer 13, to realize a color display of emitted light. The second film encapsulation layer 17 and the cover glass 18 are sequentially disposed on the upper side of the color thin film layer 16, and thus the color thin film layer 16 can be protected. The second thin film encapsulation layer 17 can be made of a material with good sealing performance, such as an organic material, or a combination material formed by one or more inorganic materials, such as silicon oxide and silicon nitride. The second film packaging layer 17 is matched with the first film packaging layer 15, so that water vapor and oxygen can be effectively blocked, and the service life of the display substrate can be prolonged.

Fig. 4 is a schematic plan view of a display substrate according to an example of the embodiment of the disclosure, and as shown in fig. 4, an orthographic projection of the organic light emitting layer 13 on the silicon-based substrate 11 is overlaid on an orthographic projection of the first electrode 12 of the light emitting element on the silicon-based substrate 11. The orthographic projection of the color thin film layer 16 on the silicon-based substrate 11 is overlaid on the orthographic projection of the organic light emitting layer 13 on the silicon-based substrate 11. The orthographic projection of the cover glass 18 on the silicon-based substrate 11 is overlaid on the orthographic projection of the color thin film layer 16 on the silicon-based substrate 11. It can also be seen from the orthographic projection that the four sides of the cover glass 18 are reserved with a certain distance from the silicon-based substrate 11 to facilitate the connection of the opto-mechanical structure.

In some exemplary embodiments, the first electrode 12 may include a metal film layer and a transparent metal oxide film layer over the metal film layer. The metal film layer can comprise a first titanium layer, an aluminum layer and a second titanium layer which are sequentially stacked; the transparent metal oxide film layer may be Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

In other exemplary embodiments, the first electrode 12 may include two transparent metal oxide film layers and a metal film layer disposed between the two transparent metal oxide film layers, the transparent metal oxide film layer may be made of indium tin oxide or indium zinc oxide, and the metal film layer may be made of metallic silver.

In some exemplary embodiments, the display substrate further includes a plurality of test circuits (not shown in the figure), the plurality of test circuits are disposed on a side of the plurality of bonding pins near the display area 101, the test circuits are not connected to the bonding pins, and a distance between the test circuits and the bonding pins is greater than a gap width d2 between two adjacent bonding pins.

In some exemplary embodiments, as shown in fig. 1a, 1b and 5, the display substrate further includes a plurality of guard electrodes 104 disposed on a side of the plurality of test circuits away from the silicon-based substrate 11, an orthographic projection of the guard electrodes 104 on the silicon-based substrate 11 covers an orthographic projection of the test circuits on the silicon-based substrate 11, and the plurality of guard electrodes 104 are disposed on a side of the plurality of bonding pins close to the display region 101. The guard electrode 104 may be fabricated on the same layer as the metal film layer in the first electrode 12, and is used to protect the test circuit located below the guard electrode 104 and prevent laser light, Ultraviolet (UV) light, and the like existing in the OLED process from affecting the characteristics of the test circuit.

In some exemplary embodiments, the guard electrode 104 may be fabricated in the same layer as any one or more of the first titanium layer, the aluminum layer, and the second titanium layer.

In some exemplary embodiments, as shown in fig. 1a and 1b, the first and second power supply pins 1031, 1032 are not connected to the ground lead 1021.

In this embodiment, the plurality of binding pins correspond to pins on a Flexible Printed Circuit (FPC) one to one, so that transmission of a driving signal is realized, and a binding contact area is also ensured. The first power pin 1031 and the second power pin 1032 are both bound and connected with corresponding pins on a Flexible Printed Circuit (FPC), and the FPC can electrically connect the display substrate with an external circuit, so that a power signal can be provided through the external circuit.

In some exemplary embodiments, the process of forming the silicon-based substrate 11 may employ a related art mature ic (integrated circuit) wafer process.

In some exemplary embodiments, the driving circuit layer may be fabricated on the silicon substrate 11 through a silicon Semiconductor process (e.g., a Complementary Metal Oxide Semiconductor (CMOS) process), the driving circuit layer may include a plurality of circuit units, the circuit units may include at least a pixel driving circuit, the pixel driving circuit is located in the display region, the pixel driving circuit is connected to the scan signal line and the data signal line, respectively, the pixel driving circuit may include a plurality of transistors and a storage capacitor, the transistors may include a control electrode, a first electrode and a second electrode, the control electrode, the first electrode and the second electrode may be connected to corresponding connection electrodes through tungsten-filled vias (i.e., tungsten vias, W-via), respectively, and may be electrically connected to other structures (e.g., traces, etc.) through the connection electrodes.

In some exemplary embodiments, the driving circuit layer may include a semiconductor layer (not shown in the drawings), and the ground line 1021 is coupled to the semiconductor layer. In this embodiment, the ground line 1021 is coupled to the semiconductor layer, whereby the potential of the entire display substrate is controlled to be equal to the potential of the ground line.

In some example embodiments, the display substrate may include a plurality of conductive layers (not shown) disposed on the semiconductor layer;

the ground wire 1021 and at least one layer of the plurality of conducting layers are arranged in the same layer;

the plurality of bonding pins and at least one layer of the plurality of conductive layers are arranged in the same layer.

In some exemplary embodiments, the binding pins are disposed on the same layer as the ground lead 1021.

In some exemplary embodiments, the display substrate includes a first semiconductor layer, a first conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially stacked on the silicon-based substrate 11, the first semiconductor layer includes active layers of a plurality of polysilicon transistors, the first conductive layer includes gate electrodes of the plurality of polysilicon transistors and a first plate of the storage capacitor, the second conductive layer includes a second plate of the storage capacitor, the second semiconductor layer includes active layers of a plurality of oxide transistors, the third conductive layer includes gate electrodes of the plurality of oxide transistors, the fourth conductive layer includes first and second poles of the plurality of polysilicon transistors, the first and second poles of the plurality of oxide transistors, and the fifth conductive layer includes a power line or a data signal line.

In some example embodiments, the ground line 1021 may be disposed in the same layer as the fifth conductive layer.

In some exemplary embodiments, the plurality of bonding pins may have a single-layer structure, and the plurality of bonding pins may be disposed in the same layer as at least one of the plurality of conductive layers. For example, the plurality of bonding pins may be disposed in the same layer as the fifth conductive layer.

In some exemplary embodiments, as shown in fig. 1b, the binding region 103 is located at a first side of the peripheral region 102, the ground line 1021 includes at least a first portion, the first portion is also located at the first side of the peripheral region 102, and a distance d1 between the ground line 1021 and the binding pin is greater than a width of 50 sub-pixels along the first direction X.

It should be noted that the width d4 of each sub-pixel 105 along the first direction X may be between 3um and 8 um. In some exemplary embodiments, the distance d1 between the ground 1021 and the binding pin may be between the width of 100 sub-pixels in the first direction X and the width of 150 sub-pixels in the first direction X, i.e., d1 may be between 100 × d4 and 150 × d 4. For example, the distance d1 between the ground 1021 and the bonding pin may be the width of 120 sub-pixels along the first direction X, i.e., d1 may be between 120 × 3um and 120 × 8 um.

In some exemplary embodiments, as shown in fig. 1a, the binding area 103 is located at a first side of the peripheral area 102, and the ground wire 1021 is located at any one, two, or three of the three sides of the peripheral area 102 except the first side.

Illustratively, the first side of the peripheral region 102 may be located on a side of the peripheral region 102 along an opposite direction of the second reverse direction Y; the second side of the peripheral region 102 may be located at a side of the peripheral region 102 along the second reverse direction Y; the third side of the peripheral region 102 may be located on a side of the peripheral region 102 in an opposite direction of the first reverse direction X; the fourth side of the peripheral region 102 may be located at a side of the peripheral region 102 along the first reverse direction X.

In some exemplary embodiments, as shown in fig. 1a and 1b, a distance d3 between the ground line 1021 and the display area 101 is greater than a width of 50 sub-pixels in the first direction X.

It should be noted that the width d4 of each sub-pixel 105 along the first direction X may be between 3um and 8 um. In some exemplary embodiments, the distance d1 between the ground lines 1021 and the display region 101 may be between the width of 100 sub-pixels in the first direction X and the width of 150 sub-pixels in the first direction X, i.e., d3 may be between 100 × d4 and 150 × d 4. For example, the distance d3 between the ground line 1021 and the display area 101 may be the width of 120 sub-pixels along the first direction X, i.e. d3 may be between 120 × 3um and 120 × 8 um.

In some exemplary embodiments, as shown in fig. 1a and 1b, the width W of a bonding pin in the first direction X is greater than the gap width d2 between two adjacent bonding pins.

In some exemplary embodiments, the sub-pixel may include a first electrode 12, an organic light emitting layer 13, and a second electrode 14, the first electrode 12 including at least one transparent conductive oxide layer. Illustratively, the material of the transparent conductive oxide layer may be Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

In some exemplary embodiments, the first electrode 12 may be an anode and the second electrode 14 may be a cathode.

In some exemplary embodiments, as shown in fig. 5 and 6, the plurality of bonding pins may have a double-layer structure, each bonding pin includes a first sub-layer 103a and a second sub-layer 103b, the first sub-layer 103a is disposed in the same layer as at least one of the plurality of conductive layers, the second sub-layer 103b is disposed in the same layer as the transparent conductive oxide layer, the first sub-layer 103a is electrically connected to the second sub-layer 103b in parallel, and the second sub-layer 103b is located on a side of the first sub-layer 103a away from the silicon substrate 11.

The display substrate of this embodiment, when making the positive pole of display area 101, binding region 103, will binding the pin through transparent conductive oxide layer film and cover, bind the pin just so and be difficult to corroded by chloride ion, promoted and bound pin and FPC's electric connection performance, guaranteed FPC module tolerance under different environment, promoted the yield of product.

In the binding process of the silicon-based OLED display module, the matching of the binding machine is considered, the binding pins need to ensure sufficient yield and reliability in the binding process of the display module, and the FPC and the binding pins in the FPC module need sufficient contact area and have certain area requirements on the binding pins.

In some exemplary embodiments, the plurality of bonding pins are arranged along the first direction X, the width W2 of the second sub-layer 103b along the first direction X is the same as or approximately the same as the width W1 of the first sub-layer 103a along the first direction X, the length L2 of the second sub-layer 103b along the second direction Y is between 1 and 1.2 times the length L1 of the first sub-layer 103a along the second direction Y, and the first direction X intersects with the second direction Y.

It should be noted that "approximately the same" in the present disclosure means that a certain process tolerance range is allowed between the width W2 of the second sub-layer 103b along the first direction X and the width W1 of the first sub-layer 103a along the first direction X, and for example, the process tolerance range may be between 0 and 15 um.

In some exemplary embodiments, the first direction X and the second direction Y are perpendicular to each other.

Illustratively, the width W1 of the first sub-layer 103a along the first direction X is 70um, the length L1 of the first sub-layer 103a along the second direction Y is 600um, the width W2 of the second sub-layer 103b along the first direction X is the same as the width W1 of the first sub-layer 103a along the first direction X, and the length L2 of the second sub-layer 103b along the second direction Y is 10um to 80um longer than the length L1 of the first sub-layer 103a along the second direction Y.

In some exemplary embodiments, the material of the first sub-layer 103a may be metallic copper or aluminum.

The present disclosure also provides a method for manufacturing a display substrate, so as to manufacture the display substrate provided in the above embodiment. In some exemplary embodiments, a display substrate having a display area and a peripheral area located at a periphery of the display area, the peripheral area including a binding area, may be prepared by a method including:

forming a driving circuit layer on a substrate, wherein the driving circuit layer in a binding region comprises a plurality of binding pins, the plurality of binding pins comprise at least one first power supply pin and at least one second power supply pin, the first power supply pin is used for transmitting a high power supply signal to a display region, and the second power supply pin is used for transmitting a low power supply signal to the display region; the driving circuit layer of the peripheral area comprises at least one ground wire, the driving circuit layer of the display area comprises a semiconductor layer, the ground wire is coupled with the semiconductor layer, and the distance between the ground wire and the binding pins is greater than the distance between two adjacent binding pins;

the sub-pixels are formed on the driving circuit layer.

The following is an exemplary description through a process of manufacturing a display substrate. The "patterning process" referred to in the present disclosure includes processes of coating a photoresist, mask exposure, development, etching, stripping a photoresist, and the like, for a metal material, an inorganic material, or a transparent conductive material, and processes of coating an organic material, mask exposure, development, and the like, for an organic material. The deposition can be any one or more of sputtering, evaporation and chemical vapor deposition, the coating can be any one or more of spraying, spin coating and ink-jet printing, and the etching can be any one or more of dry etching and wet etching, and the disclosure is not limited. "thin film" refers to a layer of a material deposited, coated, or otherwise formed on a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as "thin film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The term "a and B are disposed in the same layer" in the present disclosure means that a and B are formed simultaneously by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display device. In the exemplary embodiment of the present disclosure, "the forward projection of B is located within the range of the forward projection of a" or "the forward projection of a includes the forward projection of B" means that the boundary of the forward projection of B falls within the boundary range of the forward projection of a, or the boundary of the forward projection of a overlaps with the boundary of the forward projection of B.

In an exemplary embodiment, the process of preparing the display substrate may include the steps of:

(11) a substrate base is formed, which may be, for example, a silicon-based substrate. The substrate may be formed by ic (integrated circuit) chip processing, which is well-known in the art and will not be described herein.

(12) And forming a driving circuit layer. The driving circuit layer may be fabricated on the substrate through a silicon Semiconductor process (e.g., a Complementary Metal Oxide Semiconductor (CMOS) process), and may include a plurality of circuit units, and the circuit units may include at least a pixel driving circuit, and the pixel driving circuit may be connected to the scan signal line and the data signal line, respectively, and may include a plurality of transistors and a storage capacitor, and the transistors may include a control electrode, a first electrode, and a second electrode, and the control electrode, the first electrode, and the second electrode may be connected to corresponding connection electrodes through vias filled with tungsten Metal (i.e., tungsten vias, W-via), and may be connected to other electrical structures (e.g., traces, etc.) through the connection electrodes.

(13) A first insulating layer is formed. In an exemplary embodiment, the forming of the first insulation layer pattern includes: and depositing a first insulating film on the substrate base plate on which the patterns are formed, and patterning the first insulating film through a patterning process to form a first insulating layer pattern covering the driving circuit layer.

(14) A first electrode is formed. In an exemplary embodiment, the forming of the first electrode pattern includes: and depositing a first electrode material film on the substrate base plate on which the patterns are formed, and patterning the first electrode material film through a patterning process to form a first electrode layer pattern arranged on the first insulating layer.

In some exemplary embodiments, the material of the first electrode may employ a metal or a metal oxide.

In some exemplary embodiments, the first electrode may have a stacked structure.

In some exemplary embodiments, the first electrode may include a metal film layer and a transparent metal oxide film layer over the metal film layer. The metal film layer may include a first titanium layer, an aluminum layer, and a second titanium layer sequentially stacked on the first insulating layer; the transparent metal oxide film layer may be Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

In other exemplary embodiments, the first electrode may include two transparent metal oxide film layers and a metal film layer disposed between the two transparent metal oxide film layers, the transparent metal oxide film layer may be made of Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), and the metal film layer may be made of metallic silver.

(15) A pixel definition layer is formed. In an exemplary embodiment, forming the pixel defining layer pattern includes: a pixel definition film is coated on the substrate base plate with the structure, a Pixel Definition Layer (PDL) pattern is formed through the processes of masking, exposing and developing, and a pixel opening is formed in the pixel definition layer in the display area and exposes at least part of the surface of the first electrode.

(16) An organic light emitting layer and a second electrode pattern are formed.

In some exemplary embodiments, the subsequent preparation process may include: and forming a first packaging layer, a color film structure layer, a second packaging layer, a cover plate layer and the like.

In an exemplary embodiment, the first Encapsulation layer and the second Encapsulation layer may adopt a Thin Film Encapsulation (TFE) method, which may ensure that external moisture cannot enter the sub-pixels, and the cover plate layer may adopt glass, or adopt plastic colorless polyimide, etc.

In an exemplary embodiment, the color filter structure layer may include a Black Matrix (BM) and a Color Filter (CF), the color filter may be located corresponding to the light emitting device, the black matrix may be located between adjacent color filters, and the color filter is configured to filter white light emitted from the light emitting device into red (R) light, green (G) light, and blue (B) light, forming red, green, and blue sub-pixels.

The embodiment of the disclosure also provides a display device, which includes the display substrate in any one of the embodiments. In some exemplary embodiments, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator, etc. However, the embodiments of the present disclosure are not limited thereto.

In the description of the embodiments of the present disclosure, the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing and simplifying the disclosure, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the disclosure.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the terms of the appended claims.

Claims (15)

1. A display substrate comprises a display area and a peripheral area located at the periphery of the display area, wherein the display area comprises a plurality of sub-pixels, the peripheral area comprises a binding area, the binding area comprises a plurality of binding pins, the plurality of binding pins comprise at least one first power supply pin and at least one second power supply pin, the first power supply pin is used for transmitting a high power supply signal to the display area, and the second power supply pin is used for transmitting a low power supply signal to the display area;

in a plane perpendicular to the display substrate, the display substrate comprises a substrate base plate and a driving circuit layer arranged on the substrate base plate, wherein the driving circuit layer comprises a semiconductor layer; the peripheral area further comprises at least one ground wire, the ground wire is coupled with the semiconductor layer, and the distance between the ground wire and the binding pins is larger than the width of a gap between every two adjacent binding pins.

2. The display substrate according to claim 1, further comprising a plurality of conductive layers disposed on the semiconductor layer;

the ground wire and at least one layer of the plurality of conducting layers are arranged in the same layer;

the plurality of bonding pins and at least one layer of the plurality of conductive layers are arranged in the same layer.

3. The display substrate of claim 1, wherein the bonding pins are disposed on the same layer as the ground lines.

4. The display substrate of claim 1, wherein the bonding area is located on a first side of the peripheral area, the ground line comprises at least a first portion, the first portion is also located on the first side of the peripheral area, and a distance between the first portion and the bonding pin is greater than 50 sub-pixels along the width of the first direction.

5. The display substrate of claim 1, wherein the bonding area is located on a first side of the peripheral area, and the ground line is located on any one, two, or three sides of the peripheral area except the first side.

6. The display substrate of claim 1, wherein the distance between the ground line and the display area is greater than the width of 50 of the sub-pixels along the first direction.

7. The display substrate according to claim 1, wherein the width of the bonding pin along the first direction is greater than the width of the gap between two adjacent bonding pins.

8. The display substrate according to claim 1, wherein the sub-pixel comprises a first electrode, an organic light emitting layer, and a second electrode, the first electrode comprising at least one transparent conductive oxide layer;

each binding pin comprises a first sublayer and a second sublayer, the first sublayer and at least one of the plurality of conducting layers are arranged on the same layer, the second sublayer and the transparent conducting oxide layer are arranged on the same layer, the first sublayer and the second sublayer are connected in parallel and electrically, and the second sublayer is positioned on one side, far away from the substrate, of the first sublayer.

9. The display substrate of claim 8, wherein the plurality of bonding pins are arranged along a first direction, the width of the second sub-layer along the first direction is the same or approximately the same as the width of the first sub-layer along the first direction, the length of the second sub-layer along a second direction is between 1 and 1.2 times the length of the first sub-layer along the second direction, and the first direction intersects with the second direction.

10. The display substrate according to claim 1, further comprising a plurality of test circuits disposed on a side of the plurality of bonding pins near the display area, wherein the test circuits are not connected to the bonding pins, and a distance between the test circuits and the bonding pins is greater than a gap width between two adjacent bonding pins.

11. The display substrate of claim 10, wherein the first electrode further comprises at least one metal conductive layer;

the display substrate further comprises a protective electrode, the protective electrode is arranged on one side, away from the substrate, of the plurality of test circuits, the orthographic projection of the protective electrode on the substrate covers the orthographic projection of the test circuits on the substrate, and the plurality of protective electrodes and the metal conducting layer are arranged on the same layer.

12. The display substrate of claim 1, wherein the plurality of bonding pins further comprises at least two impedance test pins located on both sides of the plurality of bonding pins along the first direction;

the first power supply pin comprises a first sub-pin and a second sub-pin, the second power supply pin comprises a third sub-pin and a fourth sub-pin, the third sub-pin and the fourth sub-pin are respectively adjacent to the impedance test pins on two sides of the plurality of binding pins along the first direction, the first sub-pin is located on one side, away from the impedance test pins, of the third sub-pin, and the second sub-pin is located on one side, away from the impedance test pins, of the fourth sub-pin.

13. The display substrate of claim 12, wherein the plurality of bonding pins further comprises at least one signal pin, the at least one signal pin being located between the first sub-pin and the second sub-pin.

14. A display device comprising the display substrate according to any one of claims 1 to 13.

15. A preparation method of a display substrate, wherein the display substrate comprises a display area and a peripheral area located at the periphery of the display area, and the peripheral area comprises a binding area, the preparation method comprises the following steps:

forming a driving circuit layer on a substrate, wherein the driving circuit layer of the bonding region comprises a plurality of bonding pins, the plurality of bonding pins comprise at least one first power supply pin and at least one second power supply pin, the first power supply pin is used for transmitting a high power supply signal to the display region, and the second power supply pin is used for transmitting a low power supply signal to the display region; the driving circuit layer of the peripheral area comprises at least one ground wire, the driving circuit layer of the display area comprises a semiconductor layer, the ground wire is coupled with the semiconductor layer, and the distance between the ground wire and the binding pins is greater than the distance between two adjacent binding pins;

and forming sub-pixels on the driving circuit layer.

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