CN216980567U

CN216980567U - Display substrate and display device

Info

Publication number: CN216980567U
Application number: CN202220274820.XU
Authority: CN
Inventors: 张有为; 程一鸣
Original assignee: Nanjing Boe Display Technology Co ltd; BOE Technology Group Co Ltd
Current assignee: Nanjing Boe Display Technology Co ltd; BOE Technology Group Co Ltd
Priority date: 2022-02-10
Filing date: 2022-02-10
Publication date: 2022-07-15
Anticipated expiration: 2032-02-10

Abstract

Display substrate and preparation method, display device thereof, display substrate includes: the substrate comprises a display area and a binding area at least positioned on one side of the display area; and the pixel definition layer is positioned on one side of the substrate and positioned in the display area and the binding area, wherein the shortest distance between the surface, away from the substrate, of the pixel definition layer positioned in the binding area and the substrate is smaller than the shortest distance between the surface, away from the substrate, of the pixel definition layer positioned in the display area and the substrate. According to the scheme provided by the embodiment, the thickness of the pixel definition layer in the binding region is reduced, the section difference between the pixel definition layer and the binding pad is reduced, and the yield of subsequent IC binding can be improved.

Description

Display substrate and display device

Technical Field

Embodiments of the present disclosure relate to, but not limited to, display technologies, and particularly, to a display substrate and a display device.

Background

In the self-luminous display technology, whether the display technology is an Organic Light Emitting Diode (OLED) or a Quantum dot Light Emitting Diode (QLED), whether the display technology is a printing process or an evaporation process, a hole design needs to be made in a Pixel, so that the subsequent OLED/QLED evaporation or printing of a related Light Emitting material enters the hole, which is commonly referred to as a Pixel Definition Layer (PDL) in the industry. Bank thickness is required in vapor deposition or printing designs.

SUMMERY OF THE UTILITY MODEL

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides a display substrate and a display device, and the binding yield is improved.

In one aspect, an embodiment of the present disclosure provides a display substrate, including:

the substrate comprises a display area and a binding area at least positioned on one side of the display area;

and the pixel definition layer is positioned on one side of the substrate and positioned in the display area and the binding area, wherein the shortest distance between the surface, away from the substrate, of the pixel definition layer positioned in the binding area and the substrate is smaller than the shortest distance between the surface, away from the substrate, of the pixel definition layer positioned in the display area and the substrate.

In another aspect, an embodiment of the present disclosure provides a method for manufacturing a display substrate, including:

forming a pixel definition layer provided with a pixel opening on one side of a substrate, wherein the substrate comprises a display area and a binding area at least positioned on one side of the display area, the pixel definition layer is arranged in the display area and the binding area, and the pixel opening is arranged in the display area;

coating photoresist on one side of the pixel defining layer, which is far away from the substrate, and carrying out half-tone mask exposure, development and ashing treatment, so that no photoresist is arranged at the bottom of the pixel opening after development, and at least part of the side wall of the pixel opening is covered with the photoresist after ashing treatment; the exposure degree of the photoresist covering the pixel defining layer positioned in the display area is different from the exposure degree of the photoresist covering the pixel defining layer positioned in the binding area, so that after ashing treatment, the shortest distance between the surface of the pixel defining layer positioned in the binding area, which is far away from one side of the substrate, and the substrate is smaller than the shortest distance between the surface of the pixel defining layer positioned in the display area, which is far away from one side of the substrate, and the substrate;

and stripping the photoresist.

In another aspect, an embodiment of the present disclosure provides a display device, including the display substrate.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the disclosure. The objectives and other advantages of the disclosure may be realized and attained by the structure particularly pointed out in the written description and drawings.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

FIG. 1 is a schematic plan view of a display substrate provided in accordance with an exemplary embodiment;

FIG. 2 is a cross-sectional view of the display substrate AA shown in FIG. 1;

FIG. 3 is a schematic illustration after forming a gate electrode and a first electrode provided in an exemplary embodiment;

FIG. 4 is a schematic illustration of an exemplary embodiment after formation of an active layer;

FIG. 5 is a schematic illustration after forming a source electrode, a drain electrode, and a second electrode provided by an exemplary embodiment;

FIG. 6 is a schematic diagram illustrating an exemplary embodiment of a second insulating layer after formation;

FIG. 7 is a schematic illustration after formation of a planarization layer, in accordance with an exemplary embodiment;

FIG. 8 is a schematic illustration after forming an anode and a third electrode as provided by an exemplary embodiment;

FIG. 9 is a schematic diagram illustrating a pixel definition layer formed in accordance with an exemplary embodiment;

FIG. 10 is a schematic illustration of an ashing process in accordance with an exemplary embodiment;

FIG. 11 is a schematic view of a display substrate according to another exemplary embodiment;

FIG. 12 is a schematic view of a display substrate provided in accordance with yet another exemplary embodiment;

FIG. 13 is a schematic illustration of a display substrate according to yet another exemplary embodiment;

fig. 14 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the case of conflict, the embodiments of the present disclosure and the features of the embodiments may be arbitrarily combined with each other.

The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs.

In the drawings, the size of each component, the thickness of layers, or regions may be exaggerated for clarity. Therefore, the embodiments of the present disclosure are not necessarily limited to the dimensions, and the shapes and sizes of the respective components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or numerical values shown in the drawings.

The ordinal numbers such as "first", "second", "third", etc., in this disclosure are provided to avoid confusion among the constituent elements, and do not indicate any order, number, or importance.

In the present disclosure, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain positional relationship of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the disclosure are not limited thereto, and may be replaced as appropriate.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically stated or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood as a specific case by a person of ordinary skill in the art.

In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Thus, in the present disclosure, "source electrode" and "drain electrode" may be interchanged with each other.

In the present disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present disclosure, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" means a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which an angle is 85 ° or more and 95 ° or less.

In the present disclosure, "film" and "layer" may be interchanged with one another. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

At present, an evaporation process is mainly adopted for OLED luminescent materials, a luminescent layer printing technology is regarded as the development of OLED & QLED directions, and aiming at the flowing property of ink, the existing printing technology has a plurality of difficulties, wherein the roughness of a pixel defining layer is one of the difficulties, and the improvement of the roughness of the pixel defining layer is to ensure that no glue residue exists in an opening of the pixel defining layer.

In the OLED process, oxygen plasma (O) is used₂Plasma) ashing organic material, losing part of the film thickness of PDL layer, and the evaporation process has low requirement on the surface property of material in PDL hole, butIn the printing process of the QLED luminescent material ink, the ink has higher requirements on the hydrophobicity of the surface of the material, and the hydrophobic layer on the surface of the PDL layer is ashed and the hydrophobicity is reduced by the traditional method for removing the glue residue, so that the subsequent ink-jet effect is influenced. In an exemplary embodiment, before the ashing process, the photoresist is used for protecting the pixel defining layer on the side wall of the pixel opening, so that the damage of the hydrophobicity of the side wall during the ashing process is avoided, the ink jetting effect is improved, the removal of the residual glue in the pixel opening can be realized through the ashing process, and the roughness of the pixel opening is improved.

In addition, since there is no flat layer in the binding (binding) region outside the display region, when the target film thickness of the PDL layer is 2.0um, the PDL layer thickness in the binding region is about 2.9um due to the fluidity of the paste, and the large step difference may cause the binding integrated circuit (binding IC) in the subsequent stage to fail. In an exemplary embodiment, yield of Integrated Circuit (IC) bonding may be improved by reducing a thickness of a PDL layer of the bonding region.

Fig. 1 is a schematic plan view of a display substrate according to an exemplary embodiment. As shown in fig. 1, the display substrate includes a base 1, and the base 1 includes a display area 100 and a bonding area 200 at least located at one side of the display area 100. The display area 100 includes a plurality of sub-pixels 110 distributed in an array, and the bonding area 200 includes a plurality of bonding pads 210. At least one of the plurality of sub-pixels 110 includes a thin film transistor, a planarization layer, and a light emitting element sequentially disposed on a substrate 1. The flat layer is positioned on one side of the thin film transistor, which is far away from the substrate, so as to cover the thin film transistor; the light emitting element is positioned on one side of the flat layer, which is far away from the substrate, and the light emitting element comprises an anode. The sub-pixels 110 are connected to the bonding pad 210 through the data line 300, and then connected to an external driving circuit through the bonding pad 210, only a portion of the sub-pixels are shown in fig. 1 to be connected to the bonding pad 210 through the data line 300, and the rest of the sub-pixels are similar.

Fig. 2 is a sectional view taken along the line a-a in fig. 1. As shown in fig. 2, the display substrate provided in this embodiment includes: the substrate 1, the substrate 1 includes a display area 100 and a binding area 200 at least at one side of the display area 100. In a plane perpendicular to the base 1 of the display substrate, the display substrate comprises: the light-emitting diode comprises a substrate 1, a gate electrode 2 and a first electrode 3 which are arranged on the substrate 1, a first insulating layer 4 which is arranged on one side, far away from the substrate 1, of the gate electrode 2 and the first electrode 3, an active layer 5 which is arranged on one side, far away from the substrate 1, of the first insulating layer 4, a source drain electrode layer which is arranged on one side, far away from the substrate 1, of the active layer 5, wherein the source drain electrode layer can comprise a source electrode 6, a drain electrode 7 and a second electrode 8, a second insulating layer 9 which is arranged on one side, far away from the substrate 1, of the source drain electrode layer, a flat layer 10 which is arranged on one side, far away from the substrate 1, of the second insulating layer 9, an anode 11 and a third electrode 12 which are arranged on one side, far away from the substrate 1, and a pixel defining layer 13 which is arranged on one side, of the anode 11 and the third electrode 12, far away from the substrate. The planarization layer 10 includes a first planarization layer via hole P1, the anode 11 is electrically connected to the drain electrode 7 through a first planarization layer via hole P1, the second electrode 8 is electrically connected to the first electrode 3 through a first via hole K1, and the third electrode 12 is electrically connected to the second electrode 8 through a second via hole K2.

Wherein the gate electrode 2, the source electrode 6, the drain electrode 7, the planarization layer 10, and the anode electrode 11 may be disposed in the display area 100, the first electrode 3, the second electrode 8, and the third electrode 12 may be disposed in the binding area 200, and the first insulating layer 4, the second insulating layer 9, and the pixel defining layer 13 may be disposed in the display area 100 and the binding area 200. The gate electrode 2, the active layer 5, the source electrode 6, and the drain electrode 7 constitute the thin film transistor. In another exemplary embodiment, it may be that the anode 11 is electrically connected to the source electrode 6 through the first planarization layer via hole P1.

In an exemplary embodiment, the shortest distance d1 between the surface of the pixel defining layer 13 of the binding region 200 on the side away from the substrate 1 and the substrate 1 is less than the shortest distance d2 between the surface of the pixel defining layer 13 of the display region 100 on the side away from the substrate 1 and the substrate 1. The scheme provided by the embodiment reduces the thickness of the pixel defining layer 13 in the bonding region, reduces the step difference between the pixel defining layer 13 and the third electrode 12, and can improve the yield of subsequent IC bonding. In the present disclosure, the pixel defining layer 13 located in the display area 100 refers to: the pixel defining layer 13 located in the display area 100 is orthographically projected in a plane parallel to the substrate 1. The pixel definition layer 13 located in the binding region 200 refers to: the pixel defining layer 13 at the binding region 200 is orthographically projected on a plane parallel to the substrate 1.

In an exemplary embodiment, 1.5 ≦ d2/d1 ≦ 1.9. Here, for example only, d2/d1 may have other values.

The following further illustrates the technical solution of this embodiment by the manufacturing process of the display substrate of this embodiment. The "patterning process" in this embodiment includes processes such as depositing a film, coating a photoresist, masking, exposing, developing, etching, and stripping the photoresist, and is a well-known fabrication process in the related art. The "photolithography process" referred to in this embodiment includes coating film coating, mask exposure, and development, and is a well-established production process in the related art. The deposition may be performed by a known process such as sputtering, evaporation, chemical vapor deposition, etc., the coating may be performed by a known coating process, and the etching may be performed by a known method, which is not particularly limited herein. In the description of the present embodiment, it is to be understood that "thin film" refers to a layer of a material deposited or coated on a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process or a photolithography process throughout the fabrication process. If a patterning process or a photolithography process is required for the "thin film" in the entire manufacturing process, the "thin film" is referred to as a "thin film" before the patterning process, and the "layer" after the patterning process. The "layer" after the patterning process or the photolithography process includes at least one "pattern". The "a and B are disposed in the same layer" in the present disclosure means that a and B are simultaneously formed by the same patterning process.

(1) And coating a flexible material on the glass carrier plate, and curing to form a film to form the substrate 1. The substrate 1 includes a display area 100 and a binding area 200. In the embodiments of the present disclosure, the substrate 1 may be a flexible substrate. The flexible material can be polyimide PI, polyethylene terephthalate PET or polymer soft film with surface treatment. In the exemplary embodiment, the substrate 1 may have a single-layer structure or a stacked-layer structure of a plurality of layers. The substrate of the stacked structure may include: flexible material/inorganic material/flexible material, flexible material/inorganic material/amorphous silicon/flexible material/inorganic material, etc., and the inorganic material may be Barrier (Barrier) film, such as silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate. Taking PI/Barrier/PI/Barrier stack structure as an example, the preparation process may include: the method comprises the steps of firstly coating a layer of polyimide on a glass carrier, depositing a layer of barrier film after curing and film forming, then coating a layer of polyimide on the barrier film, and depositing a layer of barrier film after curing and film forming to form the flexible substrate with a laminated structure.

(2) A first metal film is deposited on a substrate 1, and the first metal film is patterned through a patterning process to form a gate electrode 2 and a first electrode 3 disposed on the substrate 1, wherein the gate electrode 2 is formed in a display region 100 and the first electrode 3 is formed in a bonding region 200, as shown in fig. 3.

(3) Depositing a first insulating film and an active layer film in sequence, patterning the first insulating film through a patterning process to form a first insulating layer 4 pattern provided with a first via hole K1, patterning the active layer film to form an active layer 5 pattern, forming the active layer 5 in the display area 100, exposing the first electrode 3 through the first via hole K1, and covering the display area 100 and the bonding area 200 with the first insulating layer 4, as shown in fig. 4.

(4) Depositing a second metal film, patterning the second metal film through a patterning process to form a source electrode 6, a drain electrode 7 and a second electrode 8, wherein the second electrode 8 is electrically connected with the first electrode 3 through the first via hole K1, the source electrode 6 and the drain electrode 7 are formed in the display area 100, the second electrode 8 is formed in the binding area 200, and at least part of the source electrode 6 and the drain electrode 7 are arranged on the surface of the active layer 5 to realize the electrical connection with the active layer 5; as shown in fig. 5.

(5) Depositing a second insulating film covering the display area 100 and the binding area 200, as shown in fig. 6;

(6) coating a flat film, patterning to form a flat layer (PLN)10 and a second insulating layer 9 pattern, wherein a first flat layer via hole P1 is formed in the flat layer 10, a first flat layer via hole P1 is formed in the display area 100, the flat film and a second insulating film in the first flat layer via hole P1 are etched away to expose the surface of the drain electrode 7, a second via hole K2 is formed in the second insulating layer 9, and the second via hole K2 exposes the second electrode 8; as shown in fig. 7, the planarization layer 10 is formed in the display area 100, and the binding area 200 is free of the planarization layer 10. In an exemplary embodiment, the flat film may be made of an organic material such as polyimide or the like;

in an exemplary embodiment, the orthographic projection of the second electrode 8 is outside the orthographic projection of the second insulating layer 9 on a plane parallel to the substrate 1. However, the embodiments of the present disclosure are not limited thereto, and an orthogonal projection of the second electrode 8 may be partially located outside an orthogonal projection of the second insulating layer 9 on a plane parallel to the substrate 1, for example, an orthogonal projection of the second via K2 may be located inside an orthogonal projection of the second electrode 8.

(7) Depositing a transparent conductive film on the substrate on which the pattern is formed, patterning the transparent conductive film through a patterning process, forming a pattern of an anode 11 and a third electrode 12 on the planarization layer 10, wherein the anode 11 is formed in the display area 100, the third electrode 12 is formed in the bonding area 200, the anode 11 is connected to the drain electrode 7 through a first planarization via hole P1 formed in the planarization layer 10, and the third electrode 12 is connected to the second electrode 8 through a second via hole K2, as shown in fig. 8. The transparent conductive film may be indium tin oxide ITO or indium zinc oxide IZO. In an exemplary embodiment, the anode 11 may be a multilayer structure of ITO/Ag/ITO, IZO/Ag/IZO, and a transparent conductive film, an Ag film, and a transparent conductive film may be sequentially deposited and then patterned to form the anode 11.

In an exemplary embodiment, an orthographic projection of the second via K2 on the substrate 1 overlaps with an orthographic projection of the first via K1 on the substrate 1.

(8) A pixel definition film is coated on the substrate on which the pattern is formed, a Pixel Definition Layer (PDL)13 pattern is formed through a mask, exposure, and development process, a pixel opening and a binding opening are formed on the pixel definition layer 13, the pixel opening is formed in the display area 100, the binding opening is formed in the binding area 200, the pixel definition film in the pixel opening is developed away to expose the surface of the anode 11, and the binding opening exposes the third electrode 12, as shown in fig. 9. After the process, the pixel opening and the binding opening have glue residue 14.

In an exemplary embodiment, an orthographic projection of the bottom of the binding opening may be located within an orthographic projection of the third electrode 12 on a plane parallel to the substrate 1. In the solution provided in this embodiment, the sidewall of the third electrode 12 is covered by the pixel defining layer 13, so that the sidewall of the third electrode 12 can be prevented from being damaged in the subsequent process, for example, when the third electrode 12 contains Ag, the Ag can be prevented from being oxidized in the subsequent ashing process using oxygen.

In addition, the third electrode 12 can be used to protect the second electrode 8, so as to prevent the second electrode 8 from being oxidized in the subsequent ashing process.

The pixel defining layer can be made of polyimide, acrylic or polyethylene terephthalate.

(9) Coating photoresist on the substrate 1 with the aforementioned pattern, and performing halftone Mask (HTM) exposure, development and ashing, wherein, during the halftone Mask exposure, there are multiple exposure degrees, so that after development, the bottom of the pixel opening (the surface of the anode 11 away from the substrate 1) and the bottom of the binding opening (the surface of the third electrode 12 away from the substrate 1) have no photoresist, and the thickness of the photoresist covering the pixel defining layer 13 of the display area 100 is greater than the thickness of the photoresist covering the pixel defining layer 13 of the binding area 200 (after development, the pixel defining layer 13 of the binding area 200 may be covered with photoresist, or may not be covered with photoresist); and after the ashing process is performed, the sidewall of the pixel opening is at least partially covered with the photoresist, and after the ashing process is performed, the thickness of the pixel defining layer of the binding region 200 is reduced after the ashing process (i.e. after the ashing process, the thickness of the pixel defining layer of the binding region 200 is less than the thickness of the pixel defining layer 13 of the binding region 200 before the ashing process), and the shortest distance d1 between the surface of the pixel defining layer 13 of the binding region 200, which is away from the substrate 1, and the substrate 1 is less than the shortest distance d2 between the surface of the pixel defining layer 13 of the display region 100, which is away from the substrate 1, and the substrate 1. The glue residue in the pixel opening and the binding opening is removed.

According to the scheme provided by the embodiment, the side wall of the pixel opening is protected by the photoresist, so that the hydrophobic layer on the surface of the pixel definition layer of the side wall can not be ashed during ashing treatment, and the subsequent ink jet effect can not be influenced. In addition, the glue residue can be removed, and the roughness of the pixel is improved. In addition, the thickness of the pixel defining layer of the bonding region 200 can be reduced, and the yield of subsequent IC bonding can be improved.

In an exemplary embodiment, the pixel defining layer 13 of the display area 100 before the ashing process may include: an opening portion 131 constituting a side wall of the pixel opening and a flat portion 132 excluding the opening portion 131, the method further comprising a step of making a thickness of the flat portion 132 after the ashing process at least partially in a direction perpendicular to the substrate be equal to a thickness before the ashing process. That is, after the ashing process, the flat portion 132 is covered with the photoresist except for the sidewall of the pixel opening (the opening portion 131), and the flat portion 132 is protected so that the pixel defining layer of the display area 100 is not etched away in the ashing process. As shown in fig. 10, after the ashing process, the surface of the pixel defining layer of the display area 100 is covered with the photoresist 15, so as to prevent the pixel defining layer of the display area 100 from being etched away during the ashing process. In an exemplary embodiment, only the sidewall of the pixel opening in the display area 100 may be covered with the photoresist and the flat portion 132 may not be covered with the photoresist after the ashing process, and at this time, the thickness of the flat portion 132 in a direction perpendicular to the substrate may be reduced during the ashing process. According to the scheme provided by the embodiment, the side wall of the pixel opening area is protected by the photoresist, and the hydrophobic layer on the surface of the side wall cannot be ashed, so that the subsequent ink jet effect cannot be influenced.

In an exemplary embodiment, when performing halftone mask exposure, the area 101 where the bottom of the pixel opening is located and the area 201 where the bottom of the binding opening is located may be completely exposed, the area 101 of the display area 100 except the area 101 where the bottom of the pixel opening is located is not exposed, and the part of the area 201 of the binding area 200 except the bottom of the binding opening is exposed, so that after development, the area 101 and the area 102 do not have photoresist, and the thickness of the photoresist covered by the area of the display area 100 except the area 101 is greater than the thickness of the photoresist covered by the area of the binding area 200 except the area 201, so that in subsequent ashing processing, the thickness of the pixel definition layer of the binding area 200 is reduced, and the thickness of at least part of the pixel definition layer of the display area 100 is unchanged.

In an exemplary embodiment, as shown in fig. 10, the thickness d3 of the pixel defining layer 13 in the binding region 200 in a direction perpendicular to the substrate 1 may be 0.8um to 1 um. When d3 is within the value range, the step difference between the pixel definition layer 13 and the third electrode 12 is small, which can improve the yield of the subsequent Integrated Circuit (IC) bonding. However, the disclosed embodiment is not limited thereto, and the thickness d3 may have other values.

In an exemplary embodiment, as shown in fig. 10, a thickness d4 of the pixel defining layer 13 in the display area 100 along a direction perpendicular to the substrate 1 is, for example, 2um to 3 um.

In an exemplary embodiment, the ashing process may be performed using an oxygen plasma, but the disclosed embodiments are not limited thereto and may be performed using other gases.

(10) The photoresist 15 is stripped.

The photoresist 15 may be removed using an organic or inorganic solvent using a wet stripping process, as shown in fig. 1.

In an exemplary embodiment, the first insulating film and the second insulating film may be silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or the like, and may have a single-layer structure or a multi-layer composite structure. The first metal film and the second metal film may be made of a metal material, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), molybdenum-titanium alloy (MTD), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), or the like, and may have a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo. The active layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), Indium Zinc Tin Oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene and the like.

In the subsequent process, an organic light emitting layer, a cathode, an encapsulation layer, and the like may be sequentially formed in the display area 100, thereby completing the preparation of the display substrate of the embodiment.

The organic light emitting layer may include a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer stacked on the organic light emitting layer, the cathode may be made of one of metal materials such as magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy of the above metals, and the encapsulation layer may be made of a stacked structure of inorganic material/organic material/inorganic material.

The structure shown in this example and the process for making it are merely exemplary. In practical implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the active layer may be disposed on a side of the gate electrode close to the substrate, that is, the display region 100 may include the active layer, the gate electrode, the source electrode, the drain electrode, and the like, which are sequentially disposed.

Fig. 11 is a schematic view of a display substrate according to another exemplary embodiment. As shown in fig. 11, the display substrate provided in this embodiment includes a base 1, where the base 1 includes a display area 100 and a binding area 200 at least located on one side of the display area 100, and along a plane perpendicular to the base 1, the display substrate includes: the light-emitting diode comprises a substrate 1, a gate electrode 2 and a first electrode 3 which are arranged on one side of the substrate 1 far away from the substrate, a first insulating layer 4 which is arranged on one side of the gate electrode 2 and the first electrode 3 far away from the substrate 1, an active layer 5 which is arranged on one side of the first insulating layer 4 far away from the substrate 1, a source drain electrode layer which is arranged on one side of the active layer 5 far away from the substrate 1, wherein the source drain electrode layer comprises a source electrode 6, a drain electrode 7 and a second electrode 8, a second insulating layer 9 which is arranged on one side of the source drain electrode layer far away from the substrate 1, a flat layer 10 which is arranged on one side of the second insulating layer 9 far away from the substrate 1, an anode 11 and a third electrode 12 which are arranged on one side of the flat layer 10 far away from the substrate 1, and a pixel defining layer 13 which is arranged on one side of the anode 11 and the third electrode 12 far away from the substrate 1. The anode 11 is electrically connected to the drain electrode 7 through a first planarization via hole P1, the second electrode 8 is electrically connected to the first electrode 3 through a first via hole K1, and the third electrode 12 is electrically connected to the second electrode 8 through a second via hole K2. The shortest distance d1 between the surface of the pixel definition layer 13 of the binding region 200 on the side away from the substrate 1 and the substrate 1 is smaller than the shortest distance d2 between the surface of the pixel definition layer 13 of the display region 100 on the side away from the substrate 1 and the substrate 1.

Wherein, on a plane parallel to the substrate 1, there is an overlap between an orthogonal projection of the second electrode 8 and an orthogonal projection of the second insulating layer 9, that is, the second electrode 8 is partially exposed by the second via K2. In the former embodiment, the orthographic projection of the second electrode 8 is located outside the orthographic projection of the second insulating layer 9 on the plane parallel to the substrate 1, and the second electrode 8 is entirely exposed by the second via K2.

Fig. 12 is a schematic view of a display substrate according to another exemplary embodiment. As shown in fig. 12, the display substrate provided in this embodiment includes a base 1, where the base 1 includes a display area 100 and a binding area 200 at least located on one side of the display area 100, and along a plane perpendicular to the base 1, the display substrate includes: the light-emitting diode comprises a substrate 1, a gate electrode 2 and a first electrode 3 which are arranged on the substrate 1, a first insulating layer 4 which is arranged on one side, far away from the substrate 1, of the gate electrode 2 and the first electrode 3, an active layer 5 which is arranged on one side, far away from the substrate 1, of the first insulating layer 4, a source drain electrode layer which is arranged on one side, far away from the substrate 1, of the active layer 5, wherein the source drain electrode layer can comprise a source electrode 6, a drain electrode 7 and a second electrode 8, a second insulating layer 9 which is arranged on one side, far away from the substrate 1, of the source drain electrode layer, a flat layer 10 which is arranged on one side, far away from the substrate 1, of the second insulating layer 9, an anode 11 and a third electrode 12 which are arranged on one side, far away from the substrate 1, and a pixel defining layer 13 which is arranged on one side, of the anode 11 and the third electrode 12, far away from the substrate. The anode 11 is electrically connected to the drain electrode 7 through a first planarization via hole P1, the third electrode 12 is electrically connected to the second electrode 8 through a third via hole K3, and the third electrode 12 is electrically connected to the first electrode 3 through a fourth via hole K4. The first electrode 3 is disposed in the bonding region 200, the second electrode 8 and the third electrode 12 are at least partially disposed in the bonding region 200, and the second electrode 8 and the third electrode 12 may be partially disposed in the display region 100. The shortest distance d1 between the surface of the pixel defining layer 13 of the binding region 200 on the side away from the substrate 1 and the substrate 1 is less than the shortest distance d2 between the surface of the pixel defining layer 13 of the display region 100 on the side away from the substrate 1 and the substrate 1.

According to the scheme provided by the embodiment, the third via hole K3 and the fourth via hole K4 can be formed through a one-time composition process, and compared with the previous embodiment, the first via hole K1 and the second via hole K2 need to be formed through two-time composition processes, so that the one-time composition process can be reduced, the process is simplified, and the cost is reduced.

The following briefly describes the process of manufacturing the display substrate shown in fig. 12, and some details can be referred to the foregoing embodiments and are not repeated.

The preparation process of the display substrate provided by the embodiment includes:

(1) a flexible material is coated on a glass carrier, and is cured to form a film, so as to form a substrate 1, wherein the substrate 1 comprises a display area 100 and a binding area 200.

(2) A first metal film is deposited on a substrate 1, and the first metal film is patterned through a patterning process to form a gate electrode 2 and a first electrode 3 disposed on the substrate 1, wherein the gate electrode 2 is formed in a display region 100, and the first electrode 3 is formed in a bonding region 200.

(3) Depositing a first insulating film and an active layer film in sequence, patterning the active layer film through a patterning process to form a first insulating layer 4 and an active layer 5 pattern, wherein the active layer 5 is formed in the display area 100, and the first insulating layer 4 covers the display area 100 and the binding area 200.

(4) Depositing a second metal film, and patterning the second metal film through a patterning process to form a source electrode 6, a drain electrode 7 and a second electrode 8, wherein the source electrode 6 and the drain electrode 7 are formed in the display area 100, at least part of the second electrode 8 is formed in the binding area 200, and at least part of the source electrode 6 and the drain electrode 7 is arranged on the surface of the active layer 5 to realize the electrical connection with the active layer 5.

In an exemplary embodiment, the second electrode 8 is positioned at a side of the first electrode 3 adjacent to the display area 100.

(5) Depositing a second insulating film covering the display area 100 and the binding area 200, as shown in fig. 5;

(6) coating a flat film, patterning to form a flat layer (PLN)10 and a second insulating layer 9 pattern, wherein a first flat layer through hole P1 is formed in the flat layer 10, a first flat layer through hole P1 is formed in the display area 100, the flat film and the second insulating film in the first flat layer through hole P1 are etched away to expose the surface of the drain electrode 7, a third through hole K3 and a fourth through hole K4 are formed in the second insulating layer 9, the third through hole K3 exposes the second electrode 8, the fourth through hole K4 exposes the first electrode 3, the flat layer 10 is formed in the display area 100, and the binding area 200 is free of the flat layer 10.

(7) Depositing a transparent conductive film on the substrate on which the pattern is formed, patterning the transparent conductive film through a patterning process, forming a pattern of an anode 11 and a third electrode 12 on the flat layer 10, wherein the anode 11 is formed in the display area 100, the third electrode 12 is at least partially formed in the bonding area 200, the anode 11 is electrically connected to the drain electrode 7 through a first flat layer via hole P1 formed in the flat layer 10, the third electrode 12 is electrically connected to the second electrode 8 through a third via hole K3, and is electrically connected to the first electrode 3 through a fourth via hole K4.

(8) A pixel definition film is coated on the substrate on which the pattern is formed, a Pixel Definition Layer (PDL)13 pattern is formed through a mask, exposure, and development process, a pixel opening and a binding opening are formed on the pixel definition layer 13, the pixel opening is formed in the display area 100, the binding opening is formed in the binding area 200, the pixel definition film in the pixel opening is developed away to expose the surface of the anode 11, and the binding opening exposes the third electrode 12, as shown in fig. 8. After the process, the pixel opening and the binding opening have glue residue 14.

(9) Coating photoresist on the substrate 1 with the patterns, and performing exposure, development and ashing treatment on a halftone mask, wherein when the exposure of the halftone mask is performed, there are multiple exposure degrees, so that after development, the bottom of a pixel opening (the surface of the anode 11 away from the substrate 1 side) and the bottom of a binding opening (the surface of the third electrode 12 away from the substrate 1 side) are free of photoresist, and the thickness of the photoresist covering the pixel defining layer 13 of the display area 100 is greater than that of the photoresist covering the pixel defining layer 13 of the binding area 200 (after development, the photoresist may be covered on the pixel defining layer 13 of the binding area 200, or the photoresist may not be covered); and after the ashing process is performed, the sidewall of the pixel opening is at least partially covered with the photoresist, and after the ashing process is performed, the thickness of the pixel defining layer of the binding region 200 is reduced after the ashing process (i.e. after the ashing process, the thickness of the pixel defining layer of the binding region 200 is less than the thickness of the pixel defining layer 13 of the binding region 200 before the ashing process), and the shortest distance d1 between the surface of the pixel defining layer 13 of the binding region 200, which is located on the side away from the substrate 1, and the substrate 1 is less than the shortest distance d2 between the surface of the pixel defining layer 13 of the display region 100, which is located on the side away from the substrate 1, and the substrate 1. The glue residue in the pixel opening and the binding opening is removed.

(10) The photoresist 15 is stripped.

Fig. 13 is a schematic view of a display substrate according to another exemplary embodiment. The display substrate provided by this embodiment may include a substrate 1, where the substrate 1 includes a display area 100 and a binding area 200 at least located on one side of the display area 100, and the display area 100 may include a plurality of sub-pixels, and at least one of the sub-pixels includes a thin film transistor, a planarization layer, and a light emitting element sequentially disposed on the substrate. The flat layer is positioned on one side of the thin film transistor, which is far away from the substrate, so as to cover the thin film transistor; the light emitting element is positioned on one side of the flat layer, which is far away from the substrate, and the light emitting element comprises an anode. The thin film transistor includes an active layer on the substrate, a gate electrode on a side of the active layer away from the substrate, and a source electrode and a drain electrode on a side of the gate electrode away from the substrate, and one of the source electrode and the drain electrode is electrically connected to an anode of the light emitting element through the first planarization layer via hole. As shown in fig. 13, the display substrate provided in this embodiment may include: the transistor comprises a substrate 1, an active layer 5 arranged on the substrate 1, a fourth insulating layer 16 arranged on one side of the active layer 5 far away from the substrate 1, a gate electrode 2 and a first electrode 3 arranged on one side of the fourth insulating layer 16 far away from the substrate 1, a first insulating layer 4 arranged on one side of the gate electrode 2 and the first electrode 3 far away from the substrate 1, a source drain electrode layer arranged on one side of the first insulating layer 4 far away from the substrate 1, the source and drain electrode layer can comprise a source electrode 6, a drain electrode 7 and a second electrode 8, a second insulating layer 9 arranged on one side of the source and drain electrode layer, which is far away from the substrate 1, a flat layer 10 arranged on one side of the second insulating layer 9, which is far away from the substrate 1, an anode 11 and a third electrode 12 arranged on one side of the flat layer 10, which is far away from the substrate 1, and a pixel defining layer 13 arranged on one side of the anode 11 and the third electrode 12, which is far away from the substrate. The planar layer 10 includes a first planar layer via hole P1, the anode 11 is electrically connected to the drain electrode 7 through a first planar layer via hole P1, the second electrode 8 is electrically connected to the first electrode 3 through a first via hole K1, the third electrode 12 is electrically connected to the second electrode 8 through a second via hole K2, and the source electrode 6 and the drain electrode 7 are electrically connected to the active layer 5. The shortest distance d1 between the surface of the pixel defining layer 13 of the binding region 200 on the side away from the substrate 1 and the substrate 1 is less than the shortest distance d2 between the surface of the pixel defining layer 13 of the display region 100 on the side away from the substrate 1 and the substrate 1. In this embodiment, the thin film transistor includes an active layer 5, a gate electrode 2, a source electrode 6, and a drain electrode 7, which are sequentially provided on a substrate 1. In the preparation of the display substrate described in this embodiment, after the active layer 5 and the fourth insulating layer 16 are formed, the following preparation may refer to the foregoing embodiments, and details are not repeated.

Fig. 14 is a flowchart of a method for manufacturing a display substrate according to an exemplary embodiment of the present disclosure. As shown in fig. 14, a method for manufacturing a display substrate provided in an embodiment of the present disclosure may include:

1401, forming a pixel defining layer provided with a pixel opening on a substrate;

step 1402, coating photoresist on one side of the pixel defining layer, which is far away from the substrate, and performing mask exposure, development and ashing treatment to ensure that no photoresist exists at the bottom of the pixel opening after development, and at least part of the side wall of the pixel opening is covered with the photoresist after ashing treatment;

step 1403, the photoresist is stripped.

In the preparation method of the display substrate provided by the embodiment, the photoresist is used for protecting the side wall of the pixel opening, and the surface of the side wall of the pixel opening is prevented from being damaged in hydrophobic property in ashing treatment, so that the subsequent ink-jet printing effect is improved, in addition, the residual photoresist in the pixel opening can be removed, and the pixel roughness is improved.

In an exemplary embodiment, the substrate includes a display area and a binding area at least at one side of the display area, the pixel defining layer is disposed at the display area and the binding area, and the pixel opening is disposed at the display area;

the mask exposure is halftone mask exposure, wherein the exposure degree of the photoresist covering the pixel definition layer in the display area is different from the exposure degree of the photoresist covering the pixel definition layer in the binding area, so that after ashing treatment, the shortest distance between the surface of the pixel definition layer in the binding area, which is far away from the substrate, and the substrate is smaller than the shortest distance between the surface of the pixel definition layer in the display area, which is far away from the substrate, and the substrate.

In an exemplary embodiment, the pixel defining layer positioned in the display region before the ashing process includes: an opening portion constituting a side wall of the pixel opening and a flat portion excluding the opening portion, the method further comprising a step of making a thickness of the flat portion after the ashing process at least partially in a direction perpendicular to the substrate coincide with a thickness before the ashing process.

In an exemplary embodiment, the forming of the pixel defining layer provided with the pixel opening on the substrate includes:

forming a pixel defining layer provided with the pixel opening and a binding opening on the substrate, the binding opening being disposed in the binding region;

the method further comprises making the bottom of the binding opening free of photoresist after developing.

In an exemplary embodiment, before forming the pixel defining layer provided with the pixel opening on the substrate, the method further includes:

forming a first electrode on the substrate, the first electrode being formed at the bonding region;

forming a first insulating layer provided with a first through hole on one side of the first electrode, which is far away from the substrate, wherein the first through hole exposes the first electrode;

forming a second electrode on one side, far away from the substrate, of the first insulating layer, wherein the second electrode is electrically connected with the first electrode through the first via hole, and the second electrode is formed in the binding region;

forming a second insulating layer on one side of the second electrode, which is far away from the substrate;

forming a flat layer on one side of the second insulating layer, which is far away from the substrate, and forming a second through hole for exposing the second electrode;

and forming a third electrode on one side of the flat layer, which is far away from the substrate, wherein the third electrode is formed in the binding region, the third electrode is electrically connected with the second electrode through the second via hole, and the binding opening exposes the third electrode.

forming a first insulating layer on one side of the first electrode, which is far away from the substrate;

forming a second electrode on one side of the first insulating layer far away from the substrate; the second electrode is at least partially formed in the bonding region;

forming a flat layer on one side of the second insulating layer, which is far away from the substrate, and forming a third via hole for exposing the second electrode and a fourth via hole for exposing the first electrode;

and forming a third electrode on one side of the flat layer, which is far away from the substrate, wherein the third electrode is at least partially formed in the binding region, the third electrode is electrically connected with the second electrode through the third via hole, the third electrode is electrically connected with the first electrode through the fourth via hole, and the binding opening exposes the third electrode.

forming a gate electrode between the substrate and the first insulating layer, wherein the gate electrode is formed in the display region, and the gate electrode and the first electrode are formed through the same patterning process;

forming a source electrode and a drain electrode between the first insulating layer and the second insulating layer; the source electrode and the drain electrode are formed in the display area, and the source electrode, the drain electrode and the second electrode are formed through the same composition process;

and forming an anode on one side of the flat layer far away from the substrate, wherein the anode is formed in the display area, the pixel opening exposes the anode, and the anode and the third electrode are formed by the same composition process.

The embodiment of the disclosure provides a display substrate, and the display substrate is prepared by using the preparation method of the display substrate in any one of the embodiments. According to the display substrate provided by the embodiment, the pixel definition layer on the side wall of the pixel opening is protected, so that the phenomenon that the hydrophobicity of the surface of the pixel definition layer on the side wall of the pixel opening is damaged during ashing treatment is avoided, the ink-jet printing effect is improved, the adhesive residues can be removed, and the roughness of the pixel is improved.

In an exemplary embodiment, the display substrate includes a display area and a binding area at least located at one side of the display area, the pixel definition layer is disposed in the display area and the binding area, and a shortest distance between a surface of the pixel definition layer located at the binding area and the base is smaller than a shortest distance between a surface of the pixel definition layer located at the display area and the base. In the display substrate provided by this embodiment, the thickness of the pixel definition layer in the binding region is smaller than that of the pixel definition layer in the display region, so that a step difference between the pixel definition layer and the electrode in the binding opening can be reduced, and the binding yield can be improved.

In an exemplary embodiment, the pixel defining layer at the binding region has a thickness of 0.8 to 1 micrometer in a direction perpendicular to the substrate.

In an exemplary embodiment, the display substrate further includes a first electrode, a second electrode and a third electrode sequentially disposed on the substrate, the first electrode, the second electrode and the third electrode are disposed in the bonding region, the second electrode is electrically connected to the first electrode through a first via hole, and the third electrode is electrically connected to the second electrode through a second via hole.

In an exemplary embodiment, the display substrate further includes a first electrode, a second electrode and a third electrode sequentially disposed on the substrate, the first electrode is disposed in the bonding region, the second electrode and the third electrode are at least partially disposed in the bonding region, the third electrode is electrically connected to the second electrode through a third via, and the third electrode is electrically connected to the first electrode through a fourth via.

In an exemplary embodiment, the pixel defining layer further includes a binding opening exposing the third electrode, and an orthogonal projection of a bottom of the binding opening may be located within an orthogonal projection of the third electrode on a plane parallel to the substrate.

The embodiment of the disclosure also provides a display device, which includes the display substrate of the foregoing embodiment. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the purpose of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the terms of the appended claims.

Claims

1. A display substrate, comprising:

2. The display substrate according to claim 1, wherein the shortest distance between the surface of the pixel definition layer in the binding region on the side away from the base and the base is d1, and the shortest distance between the surface of the pixel definition layer in the display region on the side away from the base and the base is d2, 1.5 ≦ d2/d1 ≦ 1.9.

3. The display substrate according to claim 1, wherein the thickness of the pixel defining layer in the binding region in a direction perpendicular to the substrate is 0.8 to 1 μm.

4. The display substrate according to claim 1, further comprising a first electrode, a second electrode and a third electrode sequentially disposed on the substrate, wherein the first electrode, the second electrode and the third electrode are disposed in the bonding region, the second electrode is electrically connected to the first electrode through a first via, and the third electrode is electrically connected to the second electrode through a second via.

5. The display substrate according to claim 1, further comprising a first electrode, a second electrode and a third electrode sequentially disposed on the substrate, wherein the first electrode is disposed in the bonding region, the second electrode and the third electrode are at least partially disposed in the bonding region, the third electrode is electrically connected to the second electrode through a third via, and the third electrode is electrically connected to the first electrode through a fourth via.

6. A display substrate according to claim 4 or 5, wherein the pixel defining layer further comprises a binding opening exposing the third electrode, and wherein an orthogonal projection of a bottom of the binding opening is located within an orthogonal projection of the third electrode in a plane parallel to the base.

7. The display substrate according to claim 4 or 5, further comprising a plurality of sub-pixels in the display region, wherein at least one of the plurality of sub-pixels comprises a thin film transistor, a planarization layer, and a light emitting element;

the flat layer is positioned on one side of the thin film transistor, which is far away from the substrate, so as to cover the thin film transistor;

the light-emitting element is positioned on one side, away from the substrate, of the flat layer and comprises an anode;

the planar layer comprises a first planar layer via;

the thin film transistor comprises a gate electrode positioned on the substrate, an active layer positioned on one side of the gate electrode, which is far away from the substrate, and a source electrode and a drain electrode positioned on one side of the active layer, which is far away from the substrate, wherein one of the source electrode and the drain electrode is electrically connected with the anode of the light-emitting element through the first flat layer via hole;

the third electrode and the anode are arranged in the same layer.

8. The display substrate according to claim 7, wherein the first electrode is disposed on the same layer as the gate electrode;

the second electrode is provided in the same layer as the source electrode or the drain electrode.

9. The display substrate according to claim 4 or 5, wherein the display substrate further comprises a plurality of sub-pixels located in the display region, at least one of the plurality of sub-pixels comprising a thin film transistor, a planarization layer, and a light emitting element;

the planar layer comprises a first planar layer via;

the thin film transistor comprises an active layer positioned on the substrate, a gate electrode positioned on one side of the active layer away from the substrate, and a source electrode and a drain electrode positioned on one side of the gate electrode away from the substrate, wherein one of the source electrode and the drain electrode is electrically connected with the anode of the light-emitting element through the first flat layer via hole;

the third electrode and the anode are arranged at the same layer, and the first electrode and the gate electrode are arranged at the same layer; the second electrode is disposed in the same layer as the source electrode or the drain electrode.

10. A display device comprising the display substrate according to any one of claims 1 to 9.