JPH06333931A - Manufacture of fine electrode of semiconductor device - Google Patents
Manufacture of fine electrode of semiconductor deviceInfo
- Publication number
- JPH06333931A JPH06333931A JP5118585A JP11858593A JPH06333931A JP H06333931 A JPH06333931 A JP H06333931A JP 5118585 A JP5118585 A JP 5118585A JP 11858593 A JP11858593 A JP 11858593A JP H06333931 A JPH06333931 A JP H06333931A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- film
- resist
- diameter
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、組み込まれた素子等
に対応して形成される突起電極、すなわちフリップチッ
プＩＣ等の半導体装置における微細電極の製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a protruding electrode formed corresponding to an incorporated element, that is, a fine electrode in a semiconductor device such as a flip chip IC.
【０００２】[0002]
【従来の技術】突起電極を備えた半導体装置は、フェー
ス・ダウン・ボンディング用のフリップチップあるいは
テープ・キャリア・ボンディング用のＩＣチップ等にお
いて用いられている。半導体装置においては素子の集積
密度が著しく増大する傾向にあり、必然的にチップ内に
多数の突起電極を配列形成する必要が生ずる。したがっ
て、突起電極それぞれの相互間隔を狭くする必要が生ず
るもので、この様な要求を満足させるためには、突起電
極を柱状に形成した微細電極とすることが要求される。2. Description of the Related Art A semiconductor device having a protruding electrode is used in a flip chip for face down bonding, an IC chip for tape carrier bonding or the like. In a semiconductor device, the integration density of elements tends to remarkably increase, and inevitably it becomes necessary to form a large number of protruding electrodes in a chip. Therefore, it becomes necessary to reduce the mutual distance between the protruding electrodes, and in order to satisfy such requirements, it is necessary to form the protruding electrodes in the form of columnar fine electrodes.
【０００３】この様な微細電極は例えば次のようにして
製造される。すなわち、素子の形成された半導体ウエハ
上にアルミニウム配線を施し、この配線上にウエハを保
護するために、電極取り出しのための配線層に至る開口
を形成したパッシベーション膜を形成する。そして、こ
のパッシベーション膜の上に導電層を蒸着形成した後
に、例えば５０μｍ程度の厚さのフィルムレジストをラ
ミネートし、アライナーによって露光した後、現像して
突起電極を形成しようとする位置に導電層に至るホト穴
を形成し、Ｃu メッキを行ってホト穴内にＣu を埋め込
み、このＣu 埋め込み部分にはんだメッキを施す。その
後、フィルムレジストを剥離液によって除去し、はんだ
をリフローすることによってフリップチップ用のはんだ
バンプ（電極）が形成される。Such a fine electrode is manufactured as follows, for example. That is, aluminum wiring is provided on a semiconductor wafer on which elements are formed, and in order to protect the wafer, a passivation film having an opening reaching a wiring layer for taking out electrodes is formed on the wiring. Then, after forming a conductive layer on the passivation film by vapor deposition, a film resist having a thickness of, for example, about 50 μm is laminated, exposed by an aligner, and developed to form a conductive layer at a position where a protruding electrode is to be formed. A photo hole is formed all the way through, Cu plating is performed, Cu is embedded in the photo hole, and solder plating is applied to the Cu embedded portion. After that, the film resist is removed by a peeling solution and the solder is reflowed to form solder bumps (electrodes) for flip chips.
【０００４】この様にしてはんだバンプ用の微細電極が
形成されるものであるが、フイルムレジストに対してホ
ト穴を形成するレジスト現像工程において、フィルムレ
ジストの膜厚が５０μｍと厚いものであるため、図９に
示すようにレジスト50に形成されたホト穴51の下部に幅
Ｌのテーリンク部52が形成され、ホト穴51はレジスト50
の上部に比べて下部の径が約１０のμｍ程度狭くなっ
て、レジスト50のホト穴51の形状が適正化されない。In this way, fine electrodes for solder bumps are formed, but since the film resist is as thick as 50 μm in the resist developing step of forming photo holes in the film resist. As shown in FIG. 9, a tail link portion 52 having a width L is formed below the photo hole 51 formed in the resist 50, and the photo hole 51 is formed in the resist 50.
Since the diameter of the lower part is narrowed by about 10 μm as compared with the upper part, the shape of the photo hole 51 of the resist 50 cannot be optimized.
【０００５】したがって、この様なテーリング部52の形
成されたホト穴51部にＣu メッキを施しても、形成され
た柱状電極の下部の径が上部に比較してくびれるように
細くなり、突起電極としての機能が充分に発揮できない
状況となる。図１０はレジスト50に形成されたホト穴51
用のマスクの径に対するホト穴51の上部の径と下部の径
との関係を示したもので、常に１０μｍ程度の差があ
る。Therefore, even if the photo-hole 51 formed with such a tailing portion 52 is plated with Cu, the diameter of the lower portion of the formed columnar electrode becomes narrower than that of the upper portion, and the protruding electrode becomes smaller. As a result, it will not be able to fully exercise its function as. FIG. 10 shows a photo hole 51 formed in the resist 50.
The relationship between the diameter of the upper portion and the diameter of the lower portion of the photo hole 51 with respect to the diameter of the mask for use with the mask is shown. There is always a difference of about 10 μm.
【０００６】[0006]
【発明が解決しようとする課題】この発明は上記のよう
な点に鑑みなされたもので、柱状突起電極を形成するに
際して、この電極の上部の径と下部の径が常に等しく設
定されるように、レジストに形成されたホト穴の径が上
部と下部で一致させられるようにするもので、確実に形
状が適正化されたホト穴によって、特に下部にくびれ等
が存在しない微細化に適する突起電極が確実に形成され
るようにする半導体装置における微細電極の製造方法を
提供しようとするものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and when forming a columnar projection electrode, the upper diameter and the lower diameter of the electrode are always set to be equal. The diameter of the photo hole formed in the resist is made to match between the upper part and the lower part, and the photo hole whose shape is surely optimized is suitable for miniaturization in which there is no constriction in the lower part. An object of the present invention is to provide a method for manufacturing a fine electrode in a semiconductor device, which ensures that the above are formed.
【０００７】[0007]
【課題を解決するための手段】この発明に係る半導体装
置における微細電極の製造方法は、半導体基板に形成さ
れた素子部に対応して前記基板表面に配線層を形成し、
この配線層上に前記配線層に貫通する開口を形成した絶
縁物保護層を形成するもので、この保護層上に前記開口
を介して前記配線層に接続される導電膜を形成すると共
に、その上に微細電極の高さに相当する膜厚のレジスト
膜を形成する。そして、前記レジスト膜に前記絶縁物保
護層の開口部に対応してホト穴を形成し、リアクティブ
イオンエッチング（ＲＩＥ）によって酸素ガスのラジカ
ルをプラズマ中で生成して前記ホト穴を異方性エッチン
グした後、このホト穴にメッキ金属を埋め込み、前記レ
ジスト膜を除去して柱状電極を形成する。A method of manufacturing a fine electrode in a semiconductor device according to the present invention comprises forming a wiring layer on the surface of a substrate corresponding to an element portion formed on a semiconductor substrate,
An insulating protective layer having an opening penetrating the wiring layer is formed on the wiring layer, and a conductive film connected to the wiring layer through the opening is formed on the protective layer. A resist film having a film thickness corresponding to the height of the fine electrodes is formed thereon. Then, photoholes are formed in the resist film corresponding to the openings of the insulator protection layer, and radicals of oxygen gas are generated in plasma by reactive ion etching (RIE) to anisotropy the photoholes. After etching, a plating metal is embedded in the photohole and the resist film is removed to form a columnar electrode.
【０００８】[0008]
【作用】この様な微細電極の製造方法において、最初に
レジストにホト穴が形成された状態においては、このホ
ト穴の下部にテーリング部が存在していて、このホト穴
の上部の径と下部の径とに差がある。しかし、その後Ｒ
ＩＥによって異方性エッチングを行うことにより、ホト
穴下部のテーリング部が除去され、したがってこのホト
穴内にＣu メッキによってＣu を埋め込みレジストを除
去すれば、上部径と下部径が一致した状態の柱状電極が
形成されるようになる。すなわち、形状の適正化された
突起電極が確実に形成されるようになるもので、特に微
細化したはんだバンプ電極が高密度化可能にして容易に
形成されるようになる。In such a method of manufacturing a fine electrode, when the photohole is first formed in the resist, there is a tailing portion at the lower part of the photohole, and the diameter and the upper part of the photohole are smaller than the tailing part. There is a difference with the diameter of. But then R
By performing anisotropic etching by IE, the tailing part under the photo hole is removed. Therefore, if the resist is filled with Cu by Cu plating in the photo hole, the columnar electrode with the upper diameter and the lower diameter matched. Will be formed. That is, the bump electrode having an appropriate shape can be surely formed, and the solder bump electrode, which is particularly miniaturized, can be easily formed with high density.
【０００９】[0009]
【実施例】以下、図面を参照してこの発明の一実施例を
説明する。図１（Ａ）に示すように、まず半導体ウエハ
11に素子12が形成されているもので、この半導体ウエハ
11の表面上にアルミニウム配線層13が形成される。次
に、（Ｂ）図で示すようにこのアルミニウム配線層13の
上に、ウエハ11を保護する目的でパッシベーション膜14
を形成しているもので、このパッシベーション膜14には
配線層13に至る開口15が形成される。このパッシベーシ
ョン膜14の表面の全面には、（Ｃ）図のようにＴi 膜16
1 およびＣu 膜162 による導電層16が蒸着あるいはスパ
ッタによって形成される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 1A, first, a semiconductor wafer
This is a semiconductor wafer in which an element 12 is formed on an 11
An aluminum wiring layer 13 is formed on the surface of 11. Then, a passivation film 14 is formed on the aluminum wiring layer 13 for the purpose of protecting the wafer 11 as shown in FIG.
The opening 15 reaching the wiring layer 13 is formed in the passivation film 14. A Ti film 16 is formed on the entire surface of the passivation film 14 as shown in FIG.
The conductive layer 16 of 1 and Cu film 162 is formed by vapor deposition or sputtering.
【００１０】次に図２の（Ａ）で示すように、この様に
して形成された導電層16上にアクリル系のレジスト膜17
を形成する。厚膜液状のレジストの場合は塗布によって
レジスト膜18が形成されるようにするものであり、また
ドライフィムレジストの場合は加熱ローラによってラミ
ネートすることによりレジスト膜18が形成される。この
様にレジスト膜17が形成されたならば、アライナー（Ca
non PLA600FA・CanonPLA501FA）によって露光し、現像
液によって現像することによって、開口15の位置に対応
してホト穴18を形成する。Next, as shown in FIG. 2A, an acrylic resist film 17 is formed on the conductive layer 16 thus formed.
To form. In the case of a thick film liquid resist, the resist film 18 is formed by coating, and in the case of a dry film resist, the resist film 18 is formed by laminating with a heating roller. If the resist film 17 is formed in this way, the aligner (Ca
non-PLA600FA / CanonPLA501FA), and by developing with a developing solution, a photo hole 18 is formed corresponding to the position of the opening 15.
【００１１】このホト穴18の形成工程において使用され
る現像液は、レジスト膜17が溶剤現像タイプであるなら
ば、１−１−１トリクロロエタン等、アルカリ現像タイ
プならば１％炭酸ナトリウム溶液等である。The developing solution used in the step of forming the photohole 18 is 1-1-1 trichloroethane or the like if the resist film 17 is of the solvent developing type, and 1% sodium carbonate solution or the like if it is of the alkaline developing type. is there.
【００１２】この様にしてホト穴18が形成されたなら
ば、同図の（Ｂ）で示すようにレジストの残渣を除去す
るためにアッシング処理を行った後Ｃｕメッキ19を施
し、さらにその後にはんだメッキ20を施す。そして、レ
ジスト膜17を剥離液（溶剤現像タイプのレジストの場合
は塩化メチレン、アルカリ現像大部の場合は２％水酸化
カリウム溶液）で除去し、さらに同図の（Ｃ）で示すよ
うに蒸着されたＣu 膜162をＣu エッチング液で除去す
ると共に、Ｔi 膜161 をＴi エッチング液でエッチング
して、Ｃu メッキ19およびはんだメッキ20を露出させ
る。After the photoholes 18 are formed in this way, as shown in FIG. 3B, ashing is performed to remove the residue of the resist, and then Cu plating 19 is applied. Apply solder plating 20. Then, the resist film 17 is removed with a stripping solution (methylene chloride in the case of a solvent developing type resist, and a 2% potassium hydroxide solution in the case of a large amount of alkali developing), and vapor deposition is performed as shown in FIG. The Cu film 162 thus formed is removed with a Cu etching solution, and the Ti film 161 is etched with a Ti etching solution to expose the Cu plating 19 and the solder plating 20.
【００１３】ここで使用されたＣu 膜162 およびＴi 膜
161 のエッチング液は、はんだのエッチング速度に対し
てＣu およびＴi のエッチング速度が充分に大きいもの
であるため、はんだメッキ20は殆ど溶けない。そして、
最後に（Ｄ）図で示すようにはんだメッキ20部をリフロ
ーさせて、はんだバンプが形成されるようにする。Cu film 162 and Ti film used herein
Since the etching solution of 161 has a sufficiently high etching rate of Cu and Ti with respect to the etching rate of solder, the solder plating 20 is hardly melted. And
Finally, as shown in FIG. 3D, 20 parts of the solder plating are reflowed so that solder bumps are formed.
【００１４】この様にした電極を形成するに際して、レ
ジスト膜17に対してホト穴18を形成する現像工程におい
てレジスト膜17が５０μｍと通常のレジスト膜に比べて
２５〜５０倍と厚いものであるため、現像液がホト穴18
の下部まで到達し難いものであるため、あるいは露光用
の光が斜めに入射するものであるため、ホト穴18の下部
にレジストがテーリングして、図９で示したようにテー
リング部が形成されてレジスト形状が適正化されない。
実際にホト穴18の径を上部および下部で測定してみる
と、下部の径が約１０μｍ狭くなっている。When forming the electrode as described above, the resist film 17 is 50 μm thick in the developing step of forming the photoholes 18 in the resist film 17, which is 25 to 50 times thicker than the ordinary resist film. Therefore, the developer is
Since it is difficult to reach the bottom of the photomask, or the light for exposure is obliquely incident, the resist tails to the bottom of the photohole 18 and the tailing part is formed as shown in FIG. Resist shape is not optimized.
When actually measuring the diameter of the photohole 18 at the upper and lower portions, the diameter at the lower portion is narrowed by about 10 μm.
【００１５】この様な現象が存在するため、これまでは
Ｏ2 プラズマアッシングによってホト穴18の径の適正化
を図っているが、プラズマアッシングにおいては異方性
エッチングであるため、その形状がそのまま維持される
ようになり、ホト穴18の上部の径と下部の径とを同等に
することができなかった。Due to the existence of such a phenomenon, the diameter of the photohole 18 has been optimized by O 2 plasma ashing until now. However, since the plasma ashing is anisotropic etching, its shape remains unchanged. As a result, the diameter of the upper part of the photo hole 18 and the diameter of the lower part of the photo hole 18 could not be made equal.
【００１６】そこでこの実施例においては、ＲＩＥ（リ
アクティブイオンエッチング）装置によって厚膜状のレ
ジスト膜17のテーリング部分の除去を行うもので、図３
はこのＲＩＥ装置30を示している。この装置30は、処理
すべき半導体基板11を載置したカソード31が設定された
チャンバ32を備えるもので、このチャンバ32内に所定の
Ｏ2 ガスが導入され、また排気されるようにしている。
そして、カソード31に平行に対向するようにしてアノー
ド33が設定され、カソード31とアノード33との間にはＲ
Ｆ（高周波ラジオフレケンシー）パワー34が接続される
もので、チャンバ32内にプラズマ（１０-3〜１０-4Tor
r）が形成されるようにする。Therefore, in this embodiment, the tailing portion of the thick resist film 17 is removed by an RIE (reactive ion etching) apparatus.
Indicates the RIE device 30. The apparatus 30 includes a chamber 32 in which a cathode 31 on which a semiconductor substrate 11 to be processed is placed is set, and a predetermined O 2 gas is introduced into the chamber 32 and exhausted. .
The anode 33 is set so as to face the cathode 31 in parallel, and R is provided between the cathode 31 and the anode 33.
An F (high frequency radio frequency) power 34 is connected, and a plasma (10 -3 to 10 -4 Torr) is stored in the chamber 32.
r) is formed.
【００１７】このＲＩＥ装置30は平行平板型のチャンバ
32を構成するもので、ＲＦパワー34の周波数は１３．５
６ＭＨz で１００±１０ワットに設定され、チャンバ32
内に導入されるＯ2 の流量は５０±２ＳＣＣＭ（真空度
０．７５±０．０５Torr）とされるもので、処理時間は
１０分である。This RIE device 30 is a parallel plate type chamber.
The frequency of RF power 34 is 13.5.
Set to 100 ± 10 watts at 6 MHz, chamber 32
The flow rate of O 2 introduced into the inside is 50 ± 2 SCCM (degree of vacuum 0.75 ± 0.05 Torr), and the processing time is 10 minutes.
【００１８】この様な処理条件によって膜厚５０μｍの
レジスト膜17において直径６０μｍの微細ホト穴まで穴
あけが可能とされるものであり、このホト穴の上部径と
下部径はほぼ同寸法となっている。これによって、直径
が６０μｍで電極高さが６０μｍのようなバンプも精度
良く形成可能とされる。By such processing conditions, it is possible to make a hole up to a fine photohole having a diameter of 60 μm in the resist film 17 having a film thickness of 50 μm, and the upper diameter and the lower diameter of this photohole are substantially the same. There is. As a result, bumps having a diameter of 60 μm and an electrode height of 60 μm can be accurately formed.
【００１９】以下に最適条件を決めるまでの実験結果を
説明する。まず、ＲＩＥ装置30による処理の原理につい
て検討すると、チャンバ32内に酸素ガスを導入している
ものであり、このＯ2 はプラズマ中で解離して反応性の
高い状態にあるＯ原子（ラジカル：＊で表記する）を発
生する。このＯ2 ラジカルと主成分であるアクリル樹脂
が反応してレジスト膜17はエッチングされるものと考え
られる。この反応を図で示すと図４のようになる。The experimental results until the optimum conditions are determined will be described below. First, when the principle of processing by the RIE apparatus 30 is examined, oxygen gas is introduced into the chamber 32, and this O 2 is dissociated in the plasma and O atoms in a highly reactive state (radical: (Indicated by *) occurs. It is considered that the resist film 17 is etched by the reaction between the O 2 radical and the acrylic resin as the main component. This reaction is illustrated in FIG.
【００２０】カソード31とアノード33との間に印加され
るＲＦパワーとホト穴18（スルーホール）の径およびレ
ジスト膜17の膜厚との関係について検討すると、まずレ
ジスト膜厚の減少をできる限り少なくすると共にレジス
ト残渣を除去するために、ＲＦ出力と共にスルーホール
の径とレジスト膜厚の関係を把握するようにした。その
結果、出力が大きくなるにつれて（ガス流量は固定で処
理時間一定の場合）エッチレートは大きくなる傾向にあ
る。またスルーホールの形状も１００ワット以上におい
てかなり急峻になってくるもので、さらに２００ワット
ではスルーホールの上部径と下部径とがほぼ一致するよ
うになる。Examining the relationship between the RF power applied between the cathode 31 and the anode 33 and the diameter of the photohole 18 (through hole) and the film thickness of the resist film 17, the resist film thickness can be reduced as much as possible. In order to reduce the amount and remove the resist residue, the relation between the diameter of the through hole and the resist film thickness was grasped together with the RF output. As a result, the etch rate tends to increase as the output increases (when the gas flow rate is fixed and the processing time is constant). Also, the shape of the through hole becomes considerably steep at 100 watts or more, and at 200 watts, the upper diameter and the lower diameter of the through hole become almost the same.
【００２１】以下に示す表１ないし表３は出力とスルー
ホール径およびレジスト膜厚の関係についての実験結果
を示す。The following Tables 1 to 3 show the experimental results on the relationship between the output, the through hole diameter and the resist film thickness.
【００２２】[0022]
【表１】 [Table 1]
【表２】 [Table 2]
【表３】 図５は出力（ＲＦパワー）とスルーホールの径およびレ
ジスト膜厚の関係の実験結果を示すもので、（Ａ）はス
ルーホール径と出力パワーとの関係を処理時間に関連し
て示し、（Ｂ）はレジスト膜厚と出力パワーとの関係を
同じく処理時間との関係で示している。[Table 3] FIG. 5 shows the experimental results of the relationship between the output (RF power), the diameter of the through hole, and the resist film thickness. (A) shows the relationship between the diameter of the through hole and the output power in relation to the processing time. B) shows the relationship between the resist film thickness and the output power in the same manner as the processing time.
【００２３】以上の結果から判断して、レジスト膜厚の
減少を考慮すると出力は１００ワット以下でなければな
らない。そこで、処理時間１０分でＯ2 流量が５０ＣＣ
Ｍで出力１００ワット以下としたものの電極強度を、テ
ンションゲージによって把握すると、表４で示すように
なった。Judging from the above results, the output must be 100 watts or less in consideration of the reduction of the resist film thickness. Therefore, the O 2 flow rate was 50 CC in 10 minutes.
Table 4 shows the electrode strength when the output was 100 watts or less at M and was grasped by a tension gauge.
【００２４】[0024]
【表４】 この結果より、出力５０ワットによってエッチングした
場合、Ｃu −Ｃu 間で剥離して強度不足を生じている
が、これは図６で示すようにエッチングを行った後にお
いてもレジスト残渣が残っているために、このレジスト
残渣の上のＣu メッキに強度不足が生じたものと考えら
れる。また、出力７５ワットと１００ワットとの間に強
度の差があるのは、はんだをメッキするスルーホールの
径に差があるために電極面積に差ができ、その結果強度
差となったものと考えられる。[Table 4] From this result, when etching is performed with an output of 50 watts, peeling occurs between Cu and Cu, resulting in insufficient strength. This is because the resist residue remains after etching as shown in FIG. In addition, it is considered that the Cu plating on the resist residue had insufficient strength. In addition, there is a difference in strength between the output of 75 watts and 100 watts, because there is a difference in the electrode area due to the difference in the diameter of the through-hole for plating the solder, and as a result, the difference in strength results. Conceivable.
【００２５】この様な実験結果に基づき、出力が１００
ワットが最適であることが理解できるものであるが、次
にこの出力を固定して、Ｏ2 流量とスルーホールの径お
よびレジスト膜厚の関係を把握すると、次の表５で示す
結果を得た。Based on the result of such an experiment, the output is 100
Although it can be understood that the watt is optimum, when this output is fixed and the relationship between the O 2 flow rate, the diameter of the through hole, and the resist film thickness is grasped, the results shown in Table 5 below are obtained. It was
【００２６】[0026]
【表５】 図７の（Ａ）はＯ2 流量とスルーホールの径との関係を
示し、同図の（Ｂ）はＯ2 流量とレジスト膜厚との関係
を示すもので、以上の結果からＯ2 流量が少ないとスル
ーホールの径が大きく、レジスト膜厚が薄くなる傾向に
あるもので、レジストのエッチングが進む方向にある。
またＯ2 流量が多い場合には、エッチングが思った程進
まないもので、Ｏ2 の流量が少ないとイオンによるエッ
チングが進むが、Ｏ2 の流量が多いとイオンによるエッ
チングよりも酸素ガスが多く流れ込むため、レジストと
酸素ラジカルとの反応が起こり易くなるもので、レジス
トの灰化反応が進むため、エッチングが思ったほど進ま
ないものと考えられる。以上の結果を踏まえてＯ2 の流
量は５０ＳＣＣＭとすれば効果的である。[Table 5] (A) in FIG. 7 shows the relationship between the diameter of the O 2 flow rate and the through-hole, in FIG (B) is shows the relationship between the O 2 flow rate and the resist film thickness, O 2 flow from the above results If the amount is small, the diameter of the through hole tends to be large and the resist film thickness tends to be thin, and the etching of the resist tends to proceed.
Further, when the O 2 flow rate is high, the etching does not proceed as expected. When the O 2 flow rate is low, the etching proceeds by the ions, but when the O 2 flow rate is high, the oxygen gas is larger than the etching by the ions. It is considered that the reaction between the resist and oxygen radicals easily occurs because of the flow-in, and the ashing reaction of the resist proceeds, so that the etching does not proceed as expected. Based on the above results, it is effective to set the flow rate of O 2 to 50 SCCM.
【００２７】最後にスルーホール径とレジスト膜厚との
関係を見る。以上の結果から出力とＯ2 流量が決定した
ので、出力を１００ワットに固定し、Ｏ2 の流量を５０
ＳＣＣＭに固定して、処理時間とスルーホール径および
レジスト膜厚の関係を把握すると、次の表６および図７
で示すようになった。その結果、処理時間が３分あるい
は５分の場合のスルーホールにおいてレジスト残渣が残
っているので、処理時間は１０分が適性である。Finally, the relationship between the through hole diameter and the resist film thickness will be examined. Since the output and O 2 flow rate were determined from the above results, the output was fixed at 100 watts and the O 2 flow rate was set at 50
When the relationship between the processing time, the through hole diameter, and the resist film thickness is grasped by fixing it to SCCM, the following Table 6 and FIG.
It came to show in. As a result, the resist residue remains in the through holes when the processing time is 3 minutes or 5 minutes, so that 10 minutes is suitable for the processing time.
【００２８】[0028]
【表６】 [Table 6]
【００２９】[0029]
【発明の効果】以上のようにこの発明に係る半導体装置
におけるバンプ等の突出する微細電極の製造方法によれ
ば、柱状の突起電極を形成するに際して、この電極の上
部の径と下部の径が常に等しく設定されるように、レジ
ストに形成されたホト穴の径が上部と下部で一致させら
れるもので、形状が適正化されたホト穴によって、特に
下部にくびれ等が存在しない微細化に適する突起電極が
確実に形成されるものである。As described above, according to the method for manufacturing a protruding fine electrode such as a bump in the semiconductor device according to the present invention, when the columnar protruding electrode is formed, the upper diameter and the lower diameter of this electrode are The diameters of the photo holes formed in the resist are made to match at the upper and lower parts so that they are always set to the same value, and the photo holes whose shape has been optimized are particularly suitable for miniaturization in which there are no constrictions at the lower part. The protruding electrode is surely formed.
【図１】（Ａ）〜（Ｃ）はこの発明の一実施例に係る半
導体装置における微細電極の製造過程を順次説明する断
面図。1A to 1C are cross-sectional views sequentially illustrating a process of manufacturing a fine electrode in a semiconductor device according to an embodiment of the present invention.
【図２】（Ａ）〜（Ｄ）は図１に続く製造過程を順次説
明する断面図。2A to 2D are cross-sectional views sequentially illustrating the manufacturing process subsequent to FIG.
【図３】上記製造過程で使用されるＲＩＥ装置を説明す
る図。FIG. 3 is a diagram illustrating an RIE device used in the above manufacturing process.
【図４】上記ＲＩＥ装置における処理の反応について説
明する図。FIG. 4 is a diagram illustrating a reaction of processing in the RIE device.
【図５】（Ａ）および（Ｂ）は、スルーホール径および
レジスト膜厚と出力パワーとの関係を説明する実験結果
を示す図。5A and 5B are diagrams showing experimental results for explaining the relationship between the through hole diameter, the resist film thickness, and the output power.
【図６】（Ａ）はＲＩＥ装置で処理したときのレジスト
残渣の状況を説明する図、（Ｂ）はそのときの電極構造
を説明する図。FIG. 6A is a diagram illustrating a state of resist residue when processed by an RIE apparatus, and FIG. 6B is a diagram illustrating an electrode structure at that time.
【図７】（Ａ）および（Ｂ）はそれぞれＯ2 流量とスル
ーホール径およびレジスト膜厚との関係を説明する図。FIGS. 7A and 7B are views for explaining the relationship between the O 2 flow rate, the through hole diameter, and the resist film thickness, respectively.
【図８】（Ａ）および（Ｂ）はそれぞれ処理時間とスル
ーホール径およびレジスト膜厚との関係を説明する図。FIGS. 8A and 8B are views for explaining the relationship between the processing time, the through hole diameter, and the resist film thickness, respectively.
【図９】従来の製造方法におけるレジスト膜に形成した
ホト穴の形状を説明する図。FIG. 9 is a view for explaining the shape of a photohole formed in a resist film in a conventional manufacturing method.
【図１０】図９におけるホト穴の上部径と下部径との関
係をマスク径に対応して示す図。FIG. 10 is a view showing the relationship between the upper diameter and the lower diameter of the photohole in FIG. 9 corresponding to the mask diameter.
11…半導体基板、12…素子、13…アルミニウム配線、14
…パッシベーション膜（保護層）、15…開口、16…導電
層、17…レジスト膜、18…ホト穴、19…Ｃu メッキ、20
…はんだメッキ。11 ... Semiconductor substrate, 12 ... Element, 13 ... Aluminum wiring, 14
... passivation film (protective layer), 15 ... opening, 16 ... conductive layer, 17 ... resist film, 18 ... photo hole, 19 ... Cu plating, 20
… Solder plating.
Claims (1)
て、前記基板表面に配線層を形成する第１の工程と、 前記配線層上に前記配線層に貫通する開口を形成した絶
縁物保護層を形成する第２の工程と、 前記保護層上に前記開口を介して前記配線層に接続され
る導電膜を形成する第３の工程と、 前記導電膜上に形成しようとする微細電極の高さに相当
する膜厚のレジスト膜を形成する第４の工程と、 前記レジスト膜に前記絶縁物保護層の開口部に対応し
て、前記導電膜に至るホト穴を形成する第５の工程と、 リアクティブイオンエッチングによって酸素ガスのラジ
カルをプラズマ中で生成し、前記ホト穴を電界で加速衝
撃することで異方性エッチングする第６の工程と、 前記異方性エッチングされた前記ホト穴にメッキ金属を
埋め込み、前記レジスト膜を除去して柱状電極を形成す
る第７の工程とを具備し、 前記第６の工程によって前記第５の工程で形成されたホ
ト穴の底部に形成されたテーリング部が除去されるよう
にしたことを特徴とする半導体装置における微細電極の
製造方法。1. A first step of forming a wiring layer on a surface of the substrate corresponding to an element portion formed on a semiconductor substrate, and an insulator having an opening penetrating the wiring layer on the wiring layer. A second step of forming a protective layer; a third step of forming a conductive film connected to the wiring layer through the opening on the protective layer; and a fine electrode to be formed on the conductive film. A fourth step of forming a resist film having a film thickness corresponding to the height of, and a fifth step of forming a photohole reaching the conductive film in the resist film, corresponding to the opening of the insulator protection layer. A sixth step of anisotropically etching by generating radicals of oxygen gas in plasma by reactive ion etching and accelerating and bombarding the photohole with an electric field; and the anisotropically etched photomask. Embed plated metal in the hole, in front A seventh step of removing the resist film to form a columnar electrode, and removing the tailing portion formed at the bottom of the photohole formed in the fifth step by the sixth step. A method of manufacturing a fine electrode in a semiconductor device, characterized in that.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5118585A JPH06333931A (en) | 1993-05-20 | 1993-05-20 | Manufacture of fine electrode of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5118585A JPH06333931A (en) | 1993-05-20 | 1993-05-20 | Manufacture of fine electrode of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06333931A true JPH06333931A (en) | 1994-12-02 |
Family
ID=14740233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5118585A Pending JPH06333931A (en) | 1993-05-20 | 1993-05-20 | Manufacture of fine electrode of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06333931A (en) |
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