KR101297015B1 - Method of manufacturing fan-out semiconductor package using lead frame, semiconductor package thereof, and package on package thereof - Google Patents

Method of manufacturing fan-out semiconductor package using lead frame, semiconductor package thereof, and package on package thereof Download PDF

Info

Publication number
KR101297015B1
KR101297015B1 KR1020110113649A KR20110113649A KR101297015B1 KR 101297015 B1 KR101297015 B1 KR 101297015B1 KR 1020110113649 A KR1020110113649 A KR 1020110113649A KR 20110113649 A KR20110113649 A KR 20110113649A KR 101297015 B1 KR101297015 B1 KR 101297015B1
Authority
KR
South Korea
Prior art keywords
lead frame
package
semiconductor chip
semiconductor package
semiconductor
Prior art date
Application number
KR1020110113649A
Other languages
Korean (ko)
Other versions
KR20130048810A (en
Inventor
세이 헤안 소흐
유엔 지엔 시에우
권용태
Original Assignee
주식회사 네패스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 네패스 filed Critical 주식회사 네패스
Priority to KR1020110113649A priority Critical patent/KR101297015B1/en
Publication of KR20130048810A publication Critical patent/KR20130048810A/en
Application granted granted Critical
Publication of KR101297015B1 publication Critical patent/KR101297015B1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24175Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861Lead-frames fixed on or encapsulated in insulating substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

 Disclosed are a method of manufacturing a fan-out semiconductor package using a lead frame, a semiconductor package, and a package on package. To this end, the present invention is to install the lead frame to the outside of the semiconductor chip to implement the semiconductor package of the fan out structure. Therefore, the lead frame can be used as a signal lead to planar and three dimensional to simplify complex circuit design, thereby reducing the number of metal layers to be formed, and to use the lead frame as a planar connection terminal or three-dimensional vertical connection terminal inside a semiconductor package. have.

Description

METHOD OF MANUFACTURING FAN-OUT SEMICONDUCTOR PACKAGE USING LEAD FRAME, SEMICONDUCTOR PACKAGE THEREOF, AND PACKAGE THE PACKAGE THEREOF}

The present invention relates to a method for manufacturing a fan-out semiconductor package using a leadframe, and to a semiconductor package and a package-on-package according to the present invention, and more particularly to a circuit pattern or via for achieving fan-out of the leadframe. via) A method for manufacturing a fan-out semiconductor package used as a connection path, a semiconductor package, and a package on package (POP), which is a structure in which the semiconductor package is stacked up and down. .

Semiconductor devices have been continuously reduced in size by reducing line widths and simplifying the design of circuits included therein. In addition, continuous research and development has been conducted to include more functional electronic circuits in one semiconductor device. Accordingly, the size of the semiconductor chip has been gradually reduced, and the size and spacing of the bond pad, which is an external connection terminal included in the semiconductor chip, have evolved to a more compact fine-pitch type.

However, in a semiconductor package manufacturing process using a semiconductor chip, a narrow spaced bond pad formed on the semiconductor chip needs to be further expanded to have a large size of external connection terminals such as solder balls or bumps. Can be attached. To meet these needs, various types of fan-out semiconductor packages have been introduced that can effectively expand the placement of bond pads included in semiconductor chips.

In the semiconductor package, a fan-out structure means that a redistribution pattern connected to a bond pad is extended and relocated wider than the size of the semiconductor chip. A fan-in structure is a semiconductor chip. The bond pad is relocated within the size limit of. Korean Patent Publication No. 2011-0077213 discloses a semiconductor package of a fan-out type. However, this technique has a disadvantage in that there is a limit in simplifying the manufacturing process.

The present invention reduces the number of layers in which the redistribution metal pattern is formed by using a lead frame, and uses a signal lead of the lead frame as a planar or vertical connection passage, thereby simplifying the process of manufacturing a semiconductor package and reducing manufacturing cost. Another object of the present invention is to provide a fan-out semiconductor package manufacturing method using a lead frame, which can further improve product performance.

The present invention reduces the number of layers in which the redistribution metal pattern is formed by using a lead frame, and uses a signal lead of the lead frame as a planar or vertical connection passage, thereby simplifying the process of manufacturing a semiconductor package and reducing manufacturing cost. It is another object of the present invention to provide a fan-out semiconductor package using a lead frame that can further improve product performance.

The present invention reduces the number of layers in which the redistribution metal pattern is formed by using a lead frame, and uses a signal lead of the lead frame as a planar or vertical connection passage, thereby simplifying the process of manufacturing a semiconductor package and reducing manufacturing cost. Another aim is to provide a package-on-package (POP) using leadframe to further improve product performance.

According to an embodiment of the present invention, there is provided a lead frame in a strip state having an opening in which a semiconductor chip can be seated at a center thereof and having a plurality of signal leads in a periphery thereof, and attaching the lead frame to a first base and Mounting a semiconductor chip on the first base through an opening of the semiconductor chip; sealing the semiconductor chip and the lead frame on the first base with an encapsulant and removing the first base; Forming an insulating film thereon and patterning the lead of the encapsulant and the bond pads of the semiconductor chip; forming a redistribution metal pattern connecting the exposed signal leads and the bond pads; Forming a redistribution metal pad exposing a portion of the redistribution metal pattern, and conducting conductive lead to the exposed redistribution metal pad A method of manufacturing a fan-out semiconductor package using a lead frame includes attaching a terminal and performing a singulation process of separating a unit semiconductor package from the lead frame strip and separating individual signal lines. .

According to another aspect of the invention, the present invention, the lead frame of the strip state is provided with an opening in which the semiconductor chip can be seated in the center and a plurality of signal leads in the periphery, the projection lead is provided with a protrusion by half etching Preparing a lead, attaching the lead frame to the first base, mounting the semiconductor chip on the first base through the opening of the lead frame, and only the protrusion of the lead frame and the bottom surface of the semiconductor chip. And exposing the signal lead of the lead frame and the bond pad of the semiconductor chip to the outside by performing a molding process of exposing the substrate, removing the first base, and forming an insulating layer pattern on the entire opposite surface on which the protrusion is formed. And a lower metal pattern connecting the signal lead of the lead frame and the bond pad of the semiconductor chip. Forming an insulating film pattern on the entire surface of the resultant product on which the lower metal pattern is formed, and forming a lower metal pad connected to the lower metal pattern and exposed to the outside by the insulating film pattern; and a conductive connection on the lower metal pad. A method of manufacturing a fan-out semiconductor package using a lead frame includes attaching a terminal and performing a singulation process of separating a unit semiconductor package from the lead frame strip and separating individual signal lines. do.

According to another aspect of the present invention, the present invention provides a step of preparing a lead frame in a strip state having an opening in which a semiconductor chip can be seated in the center and a signal lead in the form of a protrusion by half etching; Attaching the lead frame to a first base, mounting a semiconductor chip on the first base through an opening of the lead frame, forming an encapsulant that completely seals the semiconductor chip and the lead frame; Polishing the half-etched portion of the encapsulant and the leadframe to separate and expose the signal leads, and to remove the first base; and to form an insulating film pattern on the entire surface of the resultant in which the first base is removed. Exposing the signal leads and bond pads of the semiconductor chip; Forming a lower metal pattern connecting the pads, forming an insulating layer pattern on the entire surface of the resultant product on which the lower metal pattern is formed, and forming a lower metal pad connected to the lower metal pattern and exposed to the outside by the insulating layer pattern; And attaching a conductive connection terminal on the lower metal pad, and performing a singulation process of separating a unit semiconductor package from the leadframe strip and separating individual signal lines. A method of manufacturing an out-of- semiconductor package is provided.

According to another aspect of the invention, the present invention, a semiconductor chip, an encapsulant surrounding the bottom and the outer surface of the semiconductor chip, a plurality of signal leads of a lead frame material located inside the encapsulant, and A lead frame including a redistribution metal pattern connecting a bond pad and a plurality of signal leads of the lead frame material, a redistribution metal pad connected to the redistribution metal pattern, and a conductive connection terminal attached to the redistribution metal pad It provides a fan-out semiconductor package using.

According to another aspect of the invention, the present invention, the encapsulation material surrounding the semiconductor chip, the outer edge of the semiconductor chip, having the same height as the semiconductor chip, and located inside the encapsulation material in the vertical direction A plurality of signal leads made of a lead frame material having a penetrating shape, a redistribution metal pattern connecting the bond pads of the semiconductor chip and the signal leads, a redistribution metal pad connected to the redistribution metal pattern, and the redistribution metal Provided is a fan-out semiconductor package using a lead frame having a conductive connection terminal attached to a pad.

According to another aspect of the invention, the present invention, a semiconductor chip, encapsulating the outer edge of the semiconductor chip, the encapsulant having the same height as the semiconductor chip, included in the encapsulant and penetrating the encapsulant in the vertical direction A plurality of signal leads of a lead frame material of a shape, a redistribution metal pattern connecting the bond pads of the semiconductor chip and the signal leads, a redistribution metal pad connected to the redistribution metal pattern, and a redistribution metal pad A first semiconductor package having a conductive connection terminal, a sealing material mounted on the first semiconductor package through a conductive connection terminal, surrounding the semiconductor chip and the outer edge of the semiconductor chip, and having the same height as the semiconductor chip, the encapsulation member A plurality of signal leads of a lead frame material included in the ash and penetrating the encapsulant in the vertical direction, and the bond pad of the semiconductor chip. And a second semiconductor package including a redistribution metal pattern connecting the signal lead, a redistribution metal pad connected to the redistribution metal pattern, and a conductive connection terminal attached to the redistribution metal pad. Provide a package on package.

According to the present invention, by using a plurality of signal leads separated from the first lead frame, the number of metal layers formed to manufacture the fan-out semiconductor package can be reduced. At this time, the signal lead of the leadframe can simplify a complicated circuit design or be used as a vertical connection terminal.

Second, it is used as a signal lead of the lead frame by using a protrusion by half etching in the lead frame, so that it is a vertical connection terminal without forming a separate via hole or via contact. Can be used. This structure is advantageous for signal connection in a package on package (POP), in which two semiconductor packages are stacked vertically.

1 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a first embodiment of the present invention.
2 and 3 are a plan view and a cross-sectional view for explaining the lead frame used in the first embodiment of the present invention.
4 through 9 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a first embodiment of the present invention.
10 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a second embodiment of the present invention.
11 and 12 are a plan view and a cross-sectional view for explaining a lead frame used in a second embodiment of the present invention.
13 to 18 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a second embodiment of the present invention.
19 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a third embodiment of the present invention.
20 and 21 are a plan view and a cross-sectional view for explaining a lead frame used in a third embodiment of the present invention.
22 to 27 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a third embodiment of the present invention.
28 and 29 are cross-sectional views illustrating modified examples of FIGS. 22 and 23.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be embodied in various forms and various modifications may be made. It should be understood, however, that the description of the embodiments is provided to enable the disclosure of the invention to be complete, and will fully convey the scope of the invention to those skilled in the art. In the accompanying drawings, the constituent elements are shown enlarged for the sake of convenience of explanation, and the proportions of the constituent elements may be exaggerated or reduced.

The terms used in the embodiments of the present invention may be construed as commonly known to those skilled in the art unless otherwise defined.

Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

First Embodiment

1 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a first embodiment of the present invention.

Referring to FIG. 1, first, a lead frame as shown in FIGS. 2 and 3, in which an opening in which a semiconductor chip is mounted, is prepared (S100). The leadframe may be an etched leadframe or a stamped leadframe. However, the present invention is not limited thereto, and a general conductive plate (eg, a metal plate) having a conductive structure as the lead frame may be applied without limitation, and a method of manufacturing the lead frame may be variously selected. The lead frame is attached on the first base (S102). In addition, the semiconductor chip is attached to the first base through the opening of the lead frame as shown in FIG. 4 (S104).

In addition, a molding process is performed to form an encapsulant that seals the lead frame and the semiconductor chip on the first base as shown in FIG. 5 (S106), and illustrates a first base used to form an encapsulant. Remove as S6 (S108). After that, the resultant from which the first base has been removed is inverted and a second base (118 of FIG. 7) is optionally attached to the lower part of the resultant if necessary. Subsequently, an insulating film is formed and patterned on the resultant to form an insulating film pattern to expose the bond pad of the semiconductor chip and the signal lead of the lead frame to the outside (S110). Then, the redistribution metal pattern is formed to connect the bond pad and the signal lead as shown in FIG. 8 (S112). The insulating layer pattern is formed again to expose the redistribution metal pad exposing a part of the redistribution metal pattern (S114). Thereafter, a conductive connection terminal is attached to the exposed redistribution metal pad as shown in FIG. 8 (S116). The conductive connection terminal may be solder balls or solder bumps.

Meanwhile, the selectively attached second base may be removed after attaching the conductive connection terminal. Finally, a singulation process for separating the unit semiconductor package from the lead frame in a strip state is performed as shown in FIG. 9 (S118) to manufacture a fan-out semiconductor package using the lead frame according to the first embodiment of the present invention. Complete the process. In this case, C1 of FIG. 2 indicates a portion of the lead frame in which signal terminals respectively separated remain inside the semiconductor package.

2 and 3 are a plan view and a cross-sectional view for explaining the lead frame used in the first embodiment of the present invention. In this case, Figure 3 indicates the cut surface of 3-3 'of FIG.

2 and 3, the lead frame 100 used in the first embodiment of the present invention is preferably in the form of a strip in which at least two or more lead frames are arranged in a long band shape as shown in FIG. 2. Do. The strip frame lead frame 100 may have a strip shape in which a plurality of unit lead frames for forming one semiconductor package are arranged in a matrix form.

The lead frame 100 has a dam line 106 for supporting the respective signal leads 102 on the outside thereof, and a plurality of signal leads 102 connected to the dam line 106 are formed. have. Meanwhile, the shape of the signal lead 102 shown in FIG. 2 is an example for describing the present invention and may be modified in various shapes for effective connection with the semiconductor chip.

In addition, the lead frame 100 according to the preferred embodiment of the present invention is characterized in that the opening 104, which is a space in which the semiconductor chip can be mounted inside the signal lead 102, is provided. A typical lead frame has a chip mounting portion formed in the center thereof, and thus there is no opening. However, the lead frame 100 according to the present invention is characterized by an opening having an empty place. This structure is a semiconductor package having a fan-out structure. It can be confirmed through the subsequent process that it is useful in the process of making.

4 through 9 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a first embodiment of the present invention.

Referring to FIG. 4, the lead frame 100 of FIGS. 2 and 3 is attached onto the first base 112 by using an adhesive material. The first base 112 may be used as long as it is a material of a solid type material. For example, a mold molding or a polyimide tape may be used. Subsequently, the semiconductor chip 108 is mounted on the first base 112 using an adhesive material through the opening of the lead frame (104 in FIG. 3). On the other hand, the semiconductor chip 108 is preferably mounted so that the active region A in which the circuit portion is formed is directed downward, and the bottom surface B in which the circuit portion is not formed is mounted upward. Therefore, the bond pad 110 provided in the active region A in which the circuit unit is formed is in contact with the first base 112.

5 to 7, a molding process is performed on the resultant product on which the semiconductor chip 108 is mounted. In the molding process, the encapsulant 114 is sealed to sufficiently cover the semiconductor chip 108 and the signal lead 102 of the lead frame. The encapsulant 114 may be a high molecular compound such as an epoxy mold compound.

Thereafter, as shown in FIG. 6, the first base 112 used for fixing the semiconductor chip 108 and the signal lead 102 is removed and removed to form the panel 116. As a result, the bond pad 110 and the signal lead 102 of the semiconductor chip 108 are exposed to the position where the first base 112 is removed from the panel 116. The second base 118 is selectively attached to the direction in which the bottom surface of the semiconductor chip 108 is positioned by inverting the result of removing the first base, as shown in FIG. 7. The second base 118 may also be used as long as it is a material of a solid type material. For example, a mold molding or a polyimide tape may be used.

8 and 9, first, an insulating film 124 is formed on the entire surface of the exposed bond pad 110 and the signal lead 102, and then patterned to form the bond pad 110 and the signal lead 102. Expose to the outside. A redistribution metal pattern 122 connecting the bond pad 110 and the signal lead 102 is formed on the exposed insulating pad 110 and the insulating film 124 having the signal lead 102. The redistribution metal pattern 122 extends the array of bond pads 110 formed in the semiconductor chip 108 together with the signal leads 102 to the signal leads 102 formed outside the semiconductor chip 108. It is a means for implementing the out semiconductor package.

Subsequently, an insulating film 124 is formed on the resultant product on which the redistribution metal pattern 122 is formed and patterned to form a redistribution metal pad exposing a part of the redistribution metal pattern 122. Meanwhile, the redistribution metal pad may be formed on the metal layer pattern of the single layer structure connected to the bond pad as shown in FIG. 8, or may be formed on the metal layer pattern formed on the two layer structure as illustrated in FIG. 9. A conductive connection terminal 126, for example, a solder ball or a solder bump is attached to the exposed redistribution metal pad. Subsequently, each leadframe is separated along the cutout 128 using a diamond blade or the like to perform a singulation process of separating the unit semiconductor package from the leadframe strip.

Meanwhile, the singulation process removes all the outer portions including the damper line (106 in FIG. 2) of the lead frame and leaves only the signal leads 102 separated from each other as shown in C1 of FIG. 2. This signal lead (102 in FIG. 2) functions to expand the circuit wiring planarly or vertically in the semiconductor package of the fan-out structure, thereby reducing the number of layers of the redistribution metal pattern and simplifying the design of the circuit wiring. It can be a means. In addition, the singulation process may be performed using a punch instead of cutting using the blade, or may be performed using a laser (LASER).

Next, a structure of a fan-out semiconductor package using a lead frame according to a preferred embodiment of the present invention will be described with reference to FIG. 9.

A fan-out semiconductor package using a lead frame according to an embodiment of the present invention includes a semiconductor chip (108 in FIG. 7), an encapsulant (114 in FIG. 8) surrounding the underside and the outside of the semiconductor chip, and the semiconductor. A redistribution metal pattern 122 connecting the bond pad of the chip (110 of FIG. 7) and a plurality of signal leads (102 of FIG. 7) of the material of the lead frame, a redistribution metal pad connected to the redistribution metal pattern, and The conductive connection terminal 126 is attached to the redistribution metal pad.

At this time, the signal lead (102 in FIG. 7) of the lead frame material is disposed horizontally or vertically in the encapsulant around the semiconductor chip, thereby minimizing the number of layers forming the redistribution metal pattern, and a complicated circuit. It simplifies the design and improves the electrical performance of the semiconductor package.

Although two semiconductor chips 108 are shown in the first embodiment, the present invention is not limited thereto, and three or more semiconductor chips 108 may be attached thereto. At this time, a matrix arrangement of the semiconductor chips 108 is possible in the horizontal-vertical direction.

10 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a second embodiment of the present invention.

Referring to FIG. 10, first, a lead frame as shown in FIGS. 11 and 12 having an opening on which a semiconductor chip is mounted is prepared (S200). The lead frame is preferably an etched leadframe in which protrusions formed by half etching are formed. Subsequently, the lead frame is attached on the first base (S202). At the same time, the semiconductor chip is attached to the first base through the opening of the lead frame as shown in FIG. 13 (S204). At this time, it is preferable to attach the bond pad of the semiconductor chip to face downward, and attach the protrusion of the lead frame to face upward.

In addition, a molding process is performed to form an encapsulant sealing the lead frame and the semiconductor chip on the first base (S206), and the protrusion of the lead frame is polished with a polishing stopper. Thus, the protrusion of the signal lead is exposed to the outside as shown in FIG. An upper metal pad, for example, a vertically connected metal pad is formed on the exposed signal of the lead frame as shown in FIG. 15 (S210). Thereafter, the first base used for forming the encapsulant is removed (S212).

Subsequently, an insulating film pattern is formed on the entire opposite surface on which the protrusion is formed, thereby exposing the signal lead of the lead frame and the bond pad of the semiconductor chip to the outside (S214). In addition, the signal lead of the lead frame and the bond pad of the semiconductor chip may be connected to each other using a lower metal pattern, for example, a redistribution metal pattern, and an insulating layer pattern may be formed on the entire surface of the resultant product on which the lower metal pattern is formed, and then connected to the lower metal pattern. A lower metal pad exposed to the outside by the insulating film pattern is formed as shown in FIG. 16 (S218). Thereafter, a conductive connection terminal is attached to the exposed redistribution metal pad as shown in FIG. 16 (S220). The conductive connection terminal may be solder balls or solder bumps.

Finally, a singulation process is performed to separate the unit semiconductor package from the lead frame in a strip state (S222). As shown in FIG. 18, two semiconductor packages are vertically mounted using conductive connection terminals and an upper metal pad. This completes the manufacturing process of the fan-out semiconductor package, for example, the package on package (POP) using the lead frame according to the second embodiment of the present invention. In this case, C2 of FIG. 11 indicates a portion of the lead frame in which signal terminals respectively separated remain inside the semiconductor package.

11 and 12 are a plan view and a cross-sectional view for explaining a lead frame used in a second embodiment of the present invention. Here, FIG. 12 refers to the cut plane of 12-12 'of FIG.

11 and 12, in the lead frame 200 used in the second embodiment of the present invention, a damper line 206 for supporting each signal lead 202 is formed at an outer side thereof. A plurality of signal leads 202 connected to the damper line 206 are configured. On the other hand, the signal lead 202 includes a half-etched portion (203 in FIG. 12) and a protrusion (201 in FIG. 12) that is protruded because it is not half-etched by etching only a part of the lead frame. The shape of the signal lead 202 shown in FIG. 11 is an example for describing the present invention, and may be modified in various shapes for connection with a semiconductor chip.

In addition, the lead frame 200 according to the preferred embodiment of the present invention is characterized in that the opening 204 is provided, which is a space in which the semiconductor chip can be mounted inside the signal lead 202. The structure of the opening 204 may be usefully applied in the process of making a fan-out semiconductor package through a subsequent process.

Meanwhile, although only the shape of the lead frame 200 included in one semiconductor package is illustrated in FIG. 11, at least two lead frames are preferably strips arranged in a long band shape. The strip frame leadframe 200 may be a strip in which a plurality of unit leadframes for forming one semiconductor package are arranged in a matrix form.

13 to 18 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a second embodiment of the present invention.

13 to 15, the leadframe 200 illustrated in FIGS. 11 and 12 is attached onto the first base 212 using an adhesive material. At this time, the lead frame 200 is preferably attached so that the protrusion (201 of FIG. 12) is upward in the signal lead 202 of the lead frame. The first base 212 may be used as long as it is a material of a solid type material. For example, a mold molding or a polyimide tape may be used. Subsequently, the semiconductor chip 208 is mounted on the first base 212 using an adhesive material through the opening of the lead frame (204 of FIG. 12). On the other hand, the semiconductor chip 208 is preferably mounted so that the active region in which the circuit portion is formed faces downward, and is mounted so that the bottom surface where the circuit portion is not formed faces upward. Therefore, the bond pad 210 formed in the active region where the circuit portion is formed is in contact with the first base 212.

The molding process is performed on the resultant product on which the semiconductor chip 208 is mounted. In the molding process, the encapsulant 213 is used to completely seal the semiconductor chip 208 and the signal lead 202 of the lead frame as shown in FIG. 13. The encapsulant 213 may be made of a polymer compound such as an epoxy mold compound. As shown in FIG. 14, the protrusion 201 of the lead frame is polished to an upper portion of the encapsulant 213 by using a polishing stopper to expose the protrusion 201 of the signal lead to the surface of the encapsulant 213. Be sure to

Subsequently, the insulating film 214 is coated as shown in FIG. 15, and then patterned to expose the protrusion 201 of the signal lead, and then a metal film is formed on the insulating film 214 in a blanket manner. Patterning to form the upper metal pad 216 is electrically connected to the protrusion 201 of the signal lead. The upper metal pad 216 may serve as a vertical connection passage in a process of stacking a fan-out semiconductor package in a vertical direction to create a package on package (POP). Thereafter, the first base 212 used for fixing the semiconductor chip 208 and the signal lead 202 is removed and removed. However, before the upper metal pad 216 is formed, a single or multiple layers of upper metal patterns (not shown) may be further formed.

Referring to FIG. 16, an insulating film 218 is formed on the entire surface of the bond pad 210 and the signal lead 202 exposed to the surface from which the first base 212 is removed, and then patterned to form the insulating pad 210. And signal lead 202 are exposed to the outside. The lower metal pattern 220 connecting the bond pad 210 and the signal lead 202 to the insulating layer 218 including the exposed bond pad 210 and the signal lead 202 may be formed. Form. In the present embodiment, the lower metal pattern 220 is formed of a single layer, but the present invention is not limited thereto, and may be formed of a plurality of layers. The redistribution metal pattern 220 extends the arrangement of the bond pads 210 formed on the semiconductor chip to the signal lead 202 formed on the outside of the semiconductor chip 208, thereby becoming a main means for making a fan-out semiconductor package.

Subsequently, an insulating film 218 pattern is formed on the entire surface of the resultant product on which the lower metal pattern 220 is formed, and a lower metal pad 222 connected to the lower metal pattern 220 and exposed to the outside by the insulating film 218 pattern is formed. do. The insulating layer 218 may be a thin film having a multilayer structure made of the same material or different materials. Thereafter, a conductive connection terminal 226, for example, a solder ball or a solder bump, is attached to the lower metal pad 222. If the conductive connection terminal 226 is solder ball or solder bump, an under bump metal (UBM) may be further formed between the conductive connection terminal 226 and the lower metal pad 222. In addition, UBM may be further formed on the upper metal pad 216.

Then, each lead frame is cut (224) using a diamond blade or the like to perform a singulation process of separating the unit semiconductor package from the lead frame strip.

On the other hand, in the singulation process, all the outer portions including some of the damper lines (206 in FIG. 11) of the lead frame are removed, and only the signal leads 202 are separated from each other as shown in C2 of FIG. 11. The signal lead 202 of FIG. 11 may reduce the number of layers of the redistribution metal pattern in the semiconductor package having a fan out structure, and may have a half-etched staircase structure to simplify the circuit design. In addition, the singulation process may be performed using a punch (cut) instead of the blade, or may be performed using a laser (LASER).

FIG. 17 is a cross-sectional view of a fan-out semiconductor package using a lead frame according to a second embodiment of the present invention, which is manufactured by the singulation process.

Referring to FIG. 17, a fan-out semiconductor package 230A using a lead frame according to a second exemplary embodiment of the present invention may include a semiconductor chip 208 of FIG. 14 and an outer surface of the semiconductor chip. An encapsulant having the same height (213A in FIG. 14), a plurality of signal leads (202 in FIG. 14) of lead frame material included in the encapsulant and penetrating the encapsulant vertically, and the semiconductor chip A redistribution metal pattern 220 connecting the bond pad and the signal lead, a redistribution metal pad 222 connected to the redistribution metal pattern, and a conductive connection terminal 226 attached to the redistribution metal pad 222. It is configured to include).

In this case, the signal lead 202 serves to reduce the number of layers of a metal layer, for example, a redistribution metal pattern used to manufacture a fan-out semiconductor package, between the bond pad of the semiconductor chip and the conductive connection terminal, which is an external connection terminal. This has the advantage of simplifying the circuit design in its path. In addition, the half-etched signal lead 202 is a vertical connection penetrating the top and bottom of the semiconductor package without forming a separate via hole or via contact inside the encapsulant 213A. Can be used as a terminal. This structure is advantageous for signal connection in a package on package (POP), in which two semiconductor packages are stacked vertically.

Referring to FIG. 18, a package on package (POP) is manufactured by stacking first and second semiconductor packages 230B and 230A using the lead frame shown in FIG. 17 up and down. In this case, the upper metal pad 216 may not be formed on the signal lead of the first semiconductor package 230B as shown in part D of the drawing. In addition, the second semiconductor package 230A and the first semiconductor package 230B are physically and electrically connected to each other by the conductive connection terminal 226A of the second semiconductor package 230A.

Although the first semiconductor package 230B and the second semiconductor package 230A have substantially the same structure, the present invention is not limited thereto and may have different sizes and functions.

Meanwhile, when the upper metal pad 216 is formed on the second semiconductor package 230A, a passive element 228 such as a resistor or a capacitor may be additionally attached to improve the function of the package on package.

19 is a flowchart illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a third embodiment of the present invention.

Referring to FIG. 19, first, a lead frame as shown in FIGS. 20 and 21, in which an opening and a half etching part on which a semiconductor chip is mounted, is prepared (S300). The lead frame is preferably an etched leadframe in which protrusions formed by half etching are formed. Subsequently, the lead frame is attached on the first base (S302). In the method of attaching the lead frame to the first base, it is preferable to attach the protruding portion downward as shown in FIG. 22. In addition, the semiconductor chip is attached together on the first base through the opening of the lead frame (S304). At this time, it is suitable to attach the bond pad of the semiconductor chip to face downward.

In addition, a molding process may be performed to form an encapsulant that completely seals the lead frame and the upper portion of the semiconductor chip on the first base (S306), and the upper encapsulant and the leadframe half etching part (FIG. 21). 303) is removed completely. Accordingly, the signal lead (302 of FIG. 21) consisting of the half-etching portion (303 in FIG. 21) and the protrusion is separated, and only the protrusion 302 is exposed to the outside of the encapsulant as shown in FIG. 23 (S308). An upper metal pad, for example, a vertically connected metal pad, is formed on the exposed lead frame signal lead as illustrated in FIG. 24 (S310). Thereafter, the first base used for forming the encapsulant is removed (S312).

Subsequently, an insulating film is formed on the entire opposite surface on which the upper metal pad is formed and patterned to expose the signal lead of the lead frame and the bond pad of the semiconductor chip to the outside (S314). The signal lead of the lead frame and the bond pad of the semiconductor chip are connected to a lower metal pattern, for example, a redistribution metal pattern (S316), an insulating film pattern is formed on the entire surface of the resultant product on which the lower metal pattern is formed, and connected to the lower metal pattern. A lower metal pad exposed to the outside by the insulating film pattern is formed as shown in FIG. 25 (S318). The conductive connection terminal is attached to the exposed redistribution metal pad as shown in FIG. 26 (S320). The conductive connection terminal may be solder balls or solder bumps.

Finally, a singulation process for separating the unit semiconductor package from the lead frame in a strip state is performed (S322), and two semiconductor packages are vertically mounted using conductive connection terminals as shown in FIG. 27. A process of manufacturing a fan-out semiconductor package, for example, a package on package (POP) using the lead frame according to the third embodiment is completed (S324). At this time, in the C3 of FIG. 20, the protrusion 301 indicates a portion of the lead frame in which signal terminals separated from each other remain in the semiconductor package.

20 and 21 are a plan view and a cross-sectional view for explaining a lead frame used in a third embodiment of the present invention. FIG. 21 illustrates a cut plane of 21-21 'of FIG. 20.

20 and 21, the lead frame 300 used in the third embodiment of the present invention does not include a damper line like the lead frames described above, and has a half-etched flat half-etched portion ( Only the protrusion 302 to be used as the signal lead in 303 is formed in a rectangle. The shape of the signal lead, that is, the protrusion 302 may be modified in various shapes.

In addition, the lead frame 300 according to the preferred embodiment of the present invention is characterized in that the opening 304, which is a space in which the semiconductor chip can be mounted, is provided in the center. The structure of the opening 304 may be usefully applied in the process of making a semiconductor package having a fan-out structure through a subsequent process.

Meanwhile, although only the shape of a lead frame 300 included in one semiconductor package is illustrated in FIGS. 20 and 21, it is preferable that at least two lead frames are strips arranged in a long band shape. The strip frame lead frame 300 may be a strip in which a plurality of unit lead frames for forming one semiconductor package are arranged in a matrix form.

22 to 27 are cross-sectional views illustrating a method of manufacturing a fan-out semiconductor package using a lead frame according to a third embodiment of the present invention.

22 to 24, the lead frame 300 illustrated in FIGS. 20 and 21 is attached onto the first base 312 by using an adhesive material. At this time, it is suitable to attach the lead frame 300 so that the protrusion 302 of FIG. 22 faces downward in the lead frame. The first base 312 can be used as long as the material of the solid (rigid type) material, for example, may be a molded molding or a polyimide tape. Subsequently, the semiconductor chip 308 is mounted on the first base 312 using an adhesive material through the opening of the lead frame (304 in FIG. 21). On the other hand, the semiconductor chip 308 is suitable to be mounted so that the active region in which the circuit portion is formed to face downward, it is suitable to be mounted so that the bottom surface without the circuit portion is formed to face upward. Therefore, the bond pad 310 formed in the active region where the circuit portion is formed is in contact with the first base 312.

The molding process is performed on the resultant product on which the semiconductor chip 308 is mounted. In the molding process, the encapsulant 314 is used to completely seal the upper portion of the semiconductor chip 308 and the upper portion of the lead frame 300 as shown in FIG. 22. The encapsulant 314 may be made of a polymer compound such as an epoxy mold compound.

Subsequently, the upper portion of the encapsulant 314 and the half-etched portion 303 of FIG. 21 are completely polished as shown in FIG. 23 to separate the signal leads 302 in the form of protrusions from the lead frame 300, respectively. At the same time, the surface of the encapsulant 314 is exposed. In this case, the bottom surface of the semiconductor chip 308 may also be polished while the half etching portion 303 is polished. Alternatively, in order to prevent the bottom surface of the semiconductor chip 308 from being polished, a method of attaching the semiconductor chip 308 in the polished state may be used.

In addition, the separation of the protrusion may be performed as follows. Referring to FIG. 28, when polishing is performed while the thickness of the protrusion 302v of the lead frame 300 ′ is covered by the encapsulant 314 ′ in a state where the thickness of the protrusion 302v is greater than the thickness of the semiconductor chip 308, FIG. 29. As shown, the bottom surface of the semiconductor chip 308 is not polished. At this time, the semiconductor chip 308 is covered with the encapsulant 314A '.

Referring again to FIG. 24, after the insulating film 316 is coated and patterned, the signal lead 302 is exposed, and then a metal film is formed on the insulating film 316 in a blanket manner. Patterning forms an upper metal pad 320 electrically connected to the signal lead 302. The upper metal pad 320 may serve as a vertical connection passage in a process of stacking a fan-out semiconductor package in a vertical direction to make a package on package (POP). Thereafter, the first base 312 used for fixing the semiconductor chip 308 and the signal lead 302 is removed and removed. However, before the upper metal pad 320 is formed, a single or multiple layers of upper metal patterns (not shown) may be further formed.

Referring to FIG. 25, another bond layer 310 is formed on the entire surface of the bond pad 310 and the signal lead 302 exposed to the surface from which the first base 312 is removed, and then patterned to form the bond pad 310. ) And the signal lead 302 are exposed to the outside. The lower metal pattern 324 connecting the bond pad 310 and the signal lead 302 to the insulating layer 322 including the exposed bond pad 310 and the signal lead 302 may be formed. Form. In the present embodiment, the lower metal pattern 324 is formed as a single layer, but the present invention is not limited thereto and may be formed as a plurality of layers. The redistribution metal pattern 324 extends the arrangement of the bond pads 310 formed on the semiconductor chip to the signal lead 302 formed on the outside of the semiconductor chip 308, thereby becoming a main means for making a fan-out semiconductor package.

Subsequently, an insulating film 322 pattern is formed on the entire surface of the resultant product on which the lower metal pattern 324 is formed, and the lower metal pad 326 connected to the lower metal pattern 324 in the vertical direction and exposed to the outside by the insulating film 322 pattern. ). The insulating layer 322 may be a thin film having a multilayer structure made of the same material or different materials. Then, a conductive connector 328, for example, solder balls or solder bumps, is attached to the lower metal pad 326. Then, each lead frame is cut 330 using a diamond blade or the like to perform a singulation process of separating the unit semiconductor package from the lead frame strip. In the singulation process, cutting may be performed using a punch instead of a blade, or cutting may be performed using a laser.

Meanwhile, the signal lead 302 of FIG. 21 penetrates up and down the semiconductor package without forming a separate via hole or via contact inside the encapsulant 314. It can be used as a vertical connector. This structure is advantageous for signal connection in a package on package (POP), in which two semiconductor packages are stacked vertically.

FIG. 26 is a cross-sectional view of a fan-out semiconductor package using a lead frame according to a third embodiment of the present invention, which is manufactured by the singulation process of FIG. 25.

Referring to FIG. 26, a fan-out semiconductor package 340 using a lead frame according to a third embodiment of the present invention may include a semiconductor chip (308 of FIG. 23), an outer surface of the semiconductor chip, and a semiconductor chip; 23 (314A in FIG. 23) having the same height, a plurality of signal leads (302 in FIG. 23) of lead frame material included in the encapsulant and penetrating the encapsulant vertically, and the semiconductor chip. A redistribution metal pattern 324 connecting the bond pad and the signal lead, a redistribution metal pad 326 connected to the redistribution metal pattern, and a conductive connection terminal 328 attached to the redistribution metal pad 326. It is configured to include).

The signal lead 302 may be used as a vertical connection terminal penetrating the top and bottom of the semiconductor package without forming a separate via hole or via contact in the encapsulant 314A. This structure is advantageous for signal connection in a package on package (POP), in which two semiconductor packages are stacked vertically.

Referring to FIG. 27, a package on package POP is manufactured by stacking first and second packages 340B and 340A up and down using the lead frame illustrated in FIG. 26. In this case, the upper metal pad 320 may not be formed on the signal lead of the first semiconductor package 340B. In addition, the second semiconductor package 340A and the second semiconductor package 340B are physically and electrically connected to each other by the conductive connection terminal 328 of the second semiconductor package 340A. When the conductive connection terminal 328 is solder balls or solder bumps, UBMs may be further formed on the upper metal pad 320 and the lower metal pad 326.

Although the first semiconductor package 340B and the second semiconductor package 340A have substantially the same structure, the present invention is not limited thereto and may have different sizes and functions.

Meanwhile, when the upper metal pad is formed on the second semiconductor package 340A, a passive element 330 such as a resistor or a capacitor may be additionally attached to improve the function of the package on package.

100: lead frame, 102: signal lead,
104: opening, 106: dam line,
108: semiconductor chip, 110: bond pad,
112: first base, 114: encapsulant,
116: panel, 118: second base,
122: redistribution metal pattern, 124: insulating film,
126: conductive connecting terminal. 128: cutout.

Claims (21)

  1. delete
  2. delete
  3. delete
  4. delete
  5. Preparing a lead frame in a strip state having an opening in which a semiconductor chip can be seated in a center thereof, including a plurality of signal leads around the signal lead, and a protrusion formed by half etching;
    Attaching the lead frame to a first base and mounting a semiconductor chip on the first base through an opening of the lead frame;
    Performing a molding process of exposing only the protrusion of the lead frame and the bottom surface of the semiconductor chip to the outside, and removing the first base;
    After removing the first base, forming an insulating layer pattern on the entire opposite surface of the protrusion to expose the signal lead of the lead frame and the bond pad of the semiconductor chip to the outside;
    Forming a lower metal pattern connecting the signal lead of the lead frame and the bond pad of the semiconductor chip;
    Forming an insulating film pattern on an entire surface of the resultant product on which the lower metal pattern is formed, and forming a lower metal pad connected to the lower metal pattern and exposed to the outside by the insulating film pattern;
    Attaching a conductive connection terminal to the lower metal pad; And
    And a singulation process of separating a unit semiconductor package from the lead frame strip and separating individual signal lines.
  6. The method according to claim 5,
    The method of performing a molding process of exposing only the protrusion of the lead frame and the bottom surface of the semiconductor chip to the outside,
    Molding an encapsulant to cover the protrusion of the lead frame and the bottom surface of the semiconductor chip; And
    And polishing the encapsulant such that the protrusion of the lead frame and the bottom surface of the semiconductor chip are exposed.
  7. The method according to claim 5,
    After the molding process exposing only the protrusion of the lead frame and the bottom surface of the semiconductor chip, before removing the first base,
    The method of manufacturing a fan-out semiconductor package using a lead frame further comprising the step of forming an upper metal pad on the exposed protrusion of the lead frame.
  8. The method according to claim 5 or 7
    After the singulation process,
    Mounting the two semiconductor packages subjected to the singulation up and down using the conductive connection terminal to further manufacture a package on package (POP), characterized in that the fan-out using the lead frame Semiconductor package manufacturing method.
  9. The method according to claim 8,
    The method of manufacturing a fan-out semiconductor package using a lead frame further comprising the step of mounting the passive element on the upper metal pad of the upper semiconductor package in the package on package.
  10. Preparing a lead frame in a strip state in which an opening in which a semiconductor chip is mounted is provided at a center thereof, and a signal lead is formed in the form of a protrusion by half etching around the semiconductor chip;
    Attaching the lead frame to a first base and mounting a semiconductor chip on the first base through an opening of the lead frame;
    Forming an encapsulant which completely seals the semiconductor chip and the lead frame;
    Polishing the half-etched portion, which is a portion other than the signal lead in the lead frame, with the encapsulant to separate and expose the signal lead and remove the first base;
    After removing the first base, forming an insulating layer pattern on the entire surface of the first base from which the first base is removed to expose the signal lead of the lead frame and the bond pad of the semiconductor chip;
    Forming a lower metal pattern connecting the signal lead of the lead frame and the bond pad of the semiconductor chip;
    Forming an insulating film pattern on an entire surface of the resultant product on which the lower metal pattern is formed, and forming a lower metal pad connected to the lower metal pattern and exposed to the outside by the insulating film pattern;
    Attaching a conductive connection terminal to the lower metal pad; And
    And a singulation process of separating the unit semiconductor package from the leadframe strip.
  11. The method of claim 10,
    The method of attaching the lead frame and the semiconductor chip to the first base,
    And attaching the protrusion of the lead frame downward and the active region in which the circuit portion is formed in the semiconductor chip to face downward.
  12. The method of claim 10,
    The method for separating the signal lead by grinding the half etching portion of the encapsulant and lead frame,
    A method of manufacturing a fan-out semiconductor package using a lead frame, wherein the bottom surface of the semiconductor chip mounted in the center is also polished.
  13. The method of claim 10,
    After polishing the half-etched portion of the encapsulant and the lead frame by separating and exposing the signal leads, and before removing the first base,
    The method of manufacturing a fan-out semiconductor package using a lead frame further comprising the step of forming an upper metal pad on the exposed signal lead.
  14. The method according to claim 13,
    After the singulation process,
    Mounting the two semiconductor packages subjected to the singulation up and down using the conductive connection terminal to further manufacture a package on package (POP), characterized in that the fan-out using the lead frame Semiconductor package manufacturing method.
  15. The method according to claim 14,
    The method of manufacturing a fan-out semiconductor package using a lead frame further comprising the step of mounting the passive element on the upper metal pad of the upper semiconductor package in the package on package.
  16. delete
  17. A semiconductor chip;
    An encapsulation material surrounding an outer edge of the semiconductor chip and having the same height as the semiconductor chip;
    A plurality of signal leads made of a lead frame material positioned inside the encapsulant and penetrating the encapsulant in an up and down direction;
    A redistribution metal pattern connecting the bond pad of the semiconductor chip and the signal lead;
    A redistribution metal pad connected to the redistribution metal pattern; And
    And a conductive connection terminal attached to the redistribution metal pad.
  18. 18. The method of claim 17,
    The fan-out semiconductor package,
    The fan-out semiconductor package using the lead frame further comprises a vertically connected upper metal pad formed on the signal lead in the opposite direction connected to the redistribution metal pattern.
  19. A first semiconductor package according to claim 17; And
    A package on package (POP) mounted on the first semiconductor package via a conductive connection terminal, comprising a second semiconductor package according to claim 17.
  20. The method of claim 19,
    The first and second semiconductor packages,
    The package on package (POP) characterized in that it further comprises a vertically connected upper metal pad formed on the signal lead in the opposite direction connected to the redistribution metal pattern.
  21. The method of claim 19,
    The second semiconductor package has the same structure as the first semiconductor package, the package on package (POP).
KR1020110113649A 2011-11-03 2011-11-03 Method of manufacturing fan-out semiconductor package using lead frame, semiconductor package thereof, and package on package thereof KR101297015B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110113649A KR101297015B1 (en) 2011-11-03 2011-11-03 Method of manufacturing fan-out semiconductor package using lead frame, semiconductor package thereof, and package on package thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020110113649A KR101297015B1 (en) 2011-11-03 2011-11-03 Method of manufacturing fan-out semiconductor package using lead frame, semiconductor package thereof, and package on package thereof
PCT/KR2011/009049 WO2013065895A1 (en) 2011-11-03 2011-11-25 Method for manufacturing a fanout semiconductor package using a lead frame, and semiconductor package and package-on-package for same

Publications (2)

Publication Number Publication Date
KR20130048810A KR20130048810A (en) 2013-05-13
KR101297015B1 true KR101297015B1 (en) 2013-08-14

Family

ID=48192223

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110113649A KR101297015B1 (en) 2011-11-03 2011-11-03 Method of manufacturing fan-out semiconductor package using lead frame, semiconductor package thereof, and package on package thereof

Country Status (2)

Country Link
KR (1) KR101297015B1 (en)
WO (1) WO2013065895A1 (en)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101053079A (en) 2004-11-03 2007-10-10 德塞拉股份有限公司 Stacked packaging improvements
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
KR101128063B1 (en) 2011-05-03 2012-04-23 테세라, 인코포레이티드 Package-on-package assembly with wire bonds to encapsulation surface
US9105483B2 (en) 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
KR101840626B1 (en) * 2013-08-29 2018-03-21 로베르트 보쉬 게엠베하 Semiconductor package and manufacturing method thereof
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
CN108417498A (en) * 2018-03-14 2018-08-17 中国电子科技集团公司第五十八研究所 A kind of packaging method and encapsulation chip of chip

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010039537A (en) * 1999-10-15 2001-05-15 마이클 디. 오브라이언 semiconductor package and its manufacturing method
JP2005294443A (en) 2004-03-31 2005-10-20 Sony Corp Semiconductor device and its manufacturing method
JP2010073893A (en) 2008-09-18 2010-04-02 Shinko Electric Ind Co Ltd Semiconductor device and production process thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010039537A (en) * 1999-10-15 2001-05-15 마이클 디. 오브라이언 semiconductor package and its manufacturing method
JP2005294443A (en) 2004-03-31 2005-10-20 Sony Corp Semiconductor device and its manufacturing method
JP2010073893A (en) 2008-09-18 2010-04-02 Shinko Electric Ind Co Ltd Semiconductor device and production process thereof

Also Published As

Publication number Publication date
KR20130048810A (en) 2013-05-13
WO2013065895A1 (en) 2013-05-10

Similar Documents

Publication Publication Date Title
US9362210B2 (en) Leadframe and semiconductor package made using the leadframe
CN103325779B (en) Methods of making microelectronic packages
US8183092B2 (en) Method of fabricating stacked semiconductor structure
US8873244B2 (en) Package structure
US8269323B2 (en) Integrated circuit package with etched leadframe for package-on-package interconnects
US7075816B2 (en) Quad flat no-lead (QFN) grid array package, method of making and memory module and computer system including same
TWI495082B (en) Multi-layer semiconductor package
US6759737B2 (en) Semiconductor package including stacked chips with aligned input/output pads
US8076770B2 (en) Semiconductor device including a first land on the wiring substrate and a second land on the sealing portion
TWI446460B (en) Integrated circuit package system for package stacking
US6740961B1 (en) Lead frame design for chip scale package
US8653654B2 (en) Integrated circuit packaging system with a stackable package and method of manufacture thereof
US7141886B2 (en) Air pocket resistant semiconductor package
US8541872B2 (en) Integrated circuit package system with package stacking and method of manufacture thereof
KR100886100B1 (en) Semiconductor package and method for manufacturing the same
US7671451B2 (en) Semiconductor package having double layer leadframe
US7190062B1 (en) Embedded leadframe semiconductor package
US8502387B2 (en) Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US7501697B2 (en) Integrated circuit package system
TWI379362B (en) Integrated circuit package system with interposer
KR100594229B1 (en) Semiconductor package including a chip or plural chips and method for manufacturing the semiconductor package
KR101118774B1 (en) Image sensor device
US8878361B2 (en) Leadless package system having external contacts
US6855577B2 (en) Semiconductor devices having different package sizes made by using common parts
US7211900B2 (en) Thin semiconductor package including stacked dies

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20160729

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20180627

Year of fee payment: 6

FPAY Annual fee payment

Payment date: 20190701

Year of fee payment: 7