JP3859318B2 - Package method of the electronic circuit - Google Patents

Package method of the electronic circuit Download PDF

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Publication number
JP3859318B2
JP3859318B2 JP24744997A JP24744997A JP3859318B2 JP 3859318 B2 JP3859318 B2 JP 3859318B2 JP 24744997 A JP24744997 A JP 24744997A JP 24744997 A JP24744997 A JP 24744997A JP 3859318 B2 JP3859318 B2 JP 3859318B2
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Prior art keywords
circuit
resin
circuit board
set
mold frame
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JP24744997A
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JPH1174295A (en )
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誠 長山
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シチズン電子株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Description

【0001】 [0001]
【発明の属する技術分野】 BACKGROUND OF THE INVENTION
本発明は、回路基板上にICチップを始めとする小型の電子回路部品を実装し、樹脂を注入して回路部品を樹脂中に埋設する電子回路モジュールのパッケージ方法に関する。 The present invention implements a small electronic circuit components including the IC chip on a circuit board, to method of packaging an electronic circuit module circuits by injecting resin component is embedded in the resin.
【0002】 [0002]
【従来の技術】 BACKGROUND OF THE INVENTION
回路基板に各種の回路部品を搭載して一定の機能を持つモジュールを構成する電子回路は、多様な種類のものが現れるとともに小型化が進み、電子機器に表面実装するのに適したものが普及しつつある。 Electronic circuit constituting a module having a certain function by mounting various circuit components on the circuit board, miniaturization proceeds with appears that a variety of types, dissemination those suitable for surface mounting on electronic equipment a while. このような小型回路のパッケージとして、図4に示すのは発明者らが従来から製造しているもので、寸法の一例を上げれば縦横10mm以下、高さ5mm以下程度である。 As a package of such a microcircuit, that shown in FIG. 4 by way inventors are manufactured conventionally, vertical and horizontal 10mm or less As an example of dimensions, of the order or less height 5 mm. 図4(A)のものはそのB−B断面を同図(B)に示すが、回路基板101にICチップ102やチップ抵抗、チップ・コンデンサ等の回路部品103を実装し、回路基板101周辺の一部または全部にモールド枠104を接合し、その内側にエポキシ等の樹脂105を注入して回路部品を埋設し、金属のシールド・ケース106を取り付けたものである。 Figure 4 (A) one is shown in (B) the cross section B-B, IC chip 102 and chip resistors on the circuit board 101, and mounting the circuit components 103 such as chip capacitors, circuit board 101 near part or bonding a molded frame 104 to all, embedded circuit components by injecting resin 105 such as epoxy to the inside, is prepared by attaching the metal shield case 106. シールド・ケース106に開けた窓107は、回路中の光電素子のための光の通路である。 Window 107 opened in the shield case 106 is a passage of light for the photoelectric elements in the circuit.
【0003】 [0003]
図4(C)も上記と同系統のパッケージで、そのD−D断面を同図(D)に示すが、回路基板101の両側に樹脂の乗ってない箇所108がある。 Figure 4 (C) in the package of the same strain, but shows the section D-D in FIG. 1 (D), there is a portion 108 that is not riding resin on both sides of the circuit board 101. このパッケージにも金属のシールド・ケース106を取り付けてある。 Even in this package is attached a metal shield case 106.
【0004】 [0004]
上記のような電子回路の製造は、多数の電子回路となる領域を縦横に格子状に配置した集合回路基板を用いて、各領域に回路部品を実装し、樹脂を注入して硬化させた後これを切断して個々の電子回路に分割することにより能率よく行われる。 The manufacture of electronic circuits as described above, a region where a large number of electronic circuits using a set circuit board arranged in a lattice vertically and horizontally, and mounting the circuit components to each area, after curing the resin injection to by cutting it performed better efficiency by dividing the individual electronic circuits. 図5にそのようなパッケージ方法の一例を示す。 Figure 5 shows an example of such a packaging method.
【0005】 [0005]
図5(A)にて、集合回路基板1には多数の電子回路となる領域が配置してあり、各領域にそれぞれ回路部品2をチップ・マウンタ等によって実装する。 FIG at 5 (A), Yes disposed region where a large number of electronic circuits in the set circuit board 1, respectively circuit component 2 in each region implemented by chip mounter or the like. 次に同図(B)にて、集合回路基板1の回路部品搭載面に樹脂成形品のモールド枠3をエポキシ系接着剤などで接合する。 Next in FIG. (B), joining the mold frame 3 of the resin molded article with an epoxy-based adhesive to the circuit component mounting face of the collective circuit board 1. モールド枠3には個々の回路領域に対応する多くの窓4が開けてあり、各領域の回路部品2はそれぞれこの窓の中に収まる。 The mold frame 3 be opened a number of windows 4 that correspond to each circuit region, the circuit components 2 of each region fit in the window, respectively. 次いで同図(C)のようにモールド枠3の各窓4に樹脂5を充填する。 Then filling the resin 5 into the window 4 of the mold frame 3 as shown in FIG. (C). そして樹脂5を硬化させた後、図5(D)のように各回路領域の境界線である切断線6に沿って全体を縦横に切断するダイシングを行う。 And after curing the resin 5, dicing to cut the whole vertically and horizontally along a line 6 which is a boundary line of each circuit region as in FIG. 5 (D). 切断した各部分が個々の電子回路7となり、必要に応じてシールド・ケースをつけて完成する。 Each part was cut individual electronic circuit 7 next, complete with a shield case, if necessary. これは図4(A)、(B)の電子回路に相当するものである。 This FIG. 4 (A), the corresponds to the electronic circuit (B).
【0006】 [0006]
図5のモールド枠3は窓4が格子状に設けてあるが、窓4を各行または各列で一つにつないで短冊形の窓にしたものを平行に配置してもよい。 Although the mold frame 3 in FIG. 5 is provided a window 4 is in a lattice shape, it may be arranged parallel to what was thin and long window connects to one window 4 in each row or column. その場合、図5(D)で切り離した電子回路7の平行な2辺にモールド枠が残り、他の2辺はモールド枠がなく樹脂の切断面となる。 In that case, the remainder is molded frame on two parallel sides of the electronic circuit 7 detached in FIG. 5 (D), the other two sides becomes a cut surface of the resin without the mold frame.
【0007】 [0007]
図6に、集合回路基板に回路部品を実装し樹脂をモールドした状態の断面図をいくつか示す。 Figure 6 shows some of the cross-sectional view of a state in which mold the implemented resin circuit components to set the circuit board. 図6(A)は図5のパッケージ方法のものである。 FIG 6 (A) is of the packaging method of FIG. 図6(B)は、樹脂、レジスト材等で作ったモールド・リブ8を集合回路基板1に接合しておくもので、これは同図(A)のモールド枠3よりも高さが低く、樹脂の根元の部分で領域を定めている。 FIG. 6 (B) is a resin, the mold ribs 8 made from resist material or the like intended to be joined to the collective circuit board 1, which is lower in height than the mold frame 3 in FIG (A), defining an area in the base portion of the resin. このような背の低いモールド・リブ8は樹脂が硬化した後に剥して除去することがあり、その場合、電子回路は図4(C)のように基板上に樹脂のない部分108があるものとなる。 Lower mold ribs 8 Such Tall is be removed peel after the resin has cured, in which case the electronic circuit and those have a portion 108 without the resin on the substrate as shown in FIG. 4 (C) Become. 図6(C)ではモールド枠やリブを用いず、樹脂成形用の金型9によって樹脂をモールドする。 FIG 6 (C) in not using a mold frame and ribs, molding the resin by the mold 9 for resin molding. 回路部品の実装後、金型9を回路基板1に当接させ、各回路領域に対応するキャビティ10に樹脂5を注入して回路部品2を封入する。 After mounting of the circuit components, it is brought into contact with the mold 9 to the circuit board 1, to encapsulate the circuit components 2 by injecting resin 5 into the cavity 10 corresponding to each circuit region. この方法によるパッケージは完成品にモールド枠が残らず、図4(C)、(D)に相当するものとなる。 Package according to this method is not left the mold frame in the finished product, FIG. 4 (C), the becomes equivalent to (D).
【0008】 [0008]
【発明が解決しようとする課題】 [Problems that the Invention is to Solve
上述の電子回路のパッケージ方法は次の点で改良の余地がある。 Method of packaging an electronic circuit described above has room for improvement in the following points. すなわち、図6の断面図に見るように、これらはいずれも集合回路基板1の一方の面、すなわち部品の実装面だけに樹脂を乗せた構造であり、硬化に伴う樹脂の収縮などによって集合回路基板1に反りを生じる傾向がある。 That is, as seen in the sectional view of FIG. 6, these one surface of both the set circuit board 1, that is, a structure carrying the mounting surface only resin components, the set circuit or the like contraction of the resin caused by the curing tend to produce a warp in the substrate 1. 図6(A)、図6(B)のようにモールド枠3やモールド・リブ8を集合回路基板1に接合したり、図6(C)のように金型9に壁11を設けて集合回路基板1に樹脂を充填しない部分を残すのは、基板の反りを押さえるためであるが、モールド枠や樹脂のない部分が集合回路基板上で一定の面積を占めるから、製品の小型化や多数個取りによる取り個数を制限する要因となる。 FIG. 6 (A), the or joining the mold frame 3 and the mold rib 8 to set the circuit board 1, provided with a wall 11 in a mold 9 as shown in FIG. 6 (C) set as shown in FIG. 6 (B) leave the portion not filled with the resin to the circuit board 1, but in order to suppress the warping of the substrate, because no portion of the mold frame and the resin occupies a certain area of ​​a set circuit board, downsizing of products and numerous is a factor that limits the number taken by-piece. しかし、みだりにモールド枠や樹脂のない部分を省くと基板の反りを招く。 However, leading to warpage of the substrate when vain omitted portion without the mold frame and the resin.
【0009】 [0009]
また、樹脂の引けや高さのばらつきによって回路部品が露出することを防ぎ、回路部品を樹脂中で確実に保護するために、回路部品の高さに対し樹脂の厚さに多少の余裕を設けねばならず、製品の薄型化が制限される。 Further, prevents exposure of the circuit components due to variations in resin shrinkage or height, in order to reliably protect the circuit components in the resin, it provided some allowance for the thickness of the resin to a height of the circuit component not must, thinning of the product is limited.
本発明はこれらの問題を解決して、小型、薄型化や多数個取りによる取り個数の増量に適する電子回路のパッケージ方法を提供するものである。 The present invention is to solve these problems, there is provided a small, a method of packaging an electronic circuit suitable for increasing the number taken by thickness and multi-cavity.
【0010】 [0010]
【課題を解決するための手段】 In order to solve the problems]
本発明の電子回路のパッケージ方法は、回路部品を実装した回路基板を上板で覆い、回路基板と上板の間に封止用の樹脂を充填し硬化させて全体を一体化するものである。 Packaging method of an electronic circuit of the present invention is to integrate the whole circuit board mounted with circuit components covered with the top plate, is filled with resin for sealing the circuit board and the upper plates curing. すなわち、回路基板と上板が回路部品を封入した樹脂層をサンドイッチ状に挟持するから、これまでのように回路基板の片面側だけに樹脂があるものと違って、回路基板の反りが確実に防がれる。 That is, a resin layer circuit board and the upper plate was sealed circuit components from sandwich to sandwich, which until only one side of the circuit board in contrast to that there is a resin as, to ensure the warp of the circuit board It is prevented.
【0011】 [0011]
具体的方法として、切り離して多数の回路基板にするための集合回路基板の各回路領域に、それぞれ回路部品を実装し、集合回路基板の周囲に額縁状のモールド枠を接着してモールド枠内に樹脂を注入し、集合回路基板と同程度の大きさの集合上板を載せて樹脂を硬化させ全体を接合する。 As a specific method, detach it to each circuit area of ​​the set circuit board for a large number of the circuit board, respectively mounting the circuit components, in the mold frame by bonding a frame-shaped mold frame around the collective circuit board resin is injected to join the whole resin is cured by placing the set upper plate of the same order of magnitude as the collective circuit board. そして各回路領域を区分する切断線に沿ってダイシングすることにより電子回路のパッケージを得るのである。 And get package of the electronic circuit by dicing along a cutting line for dividing the respective circuit areas.
【0012】 [0012]
別の方法として、集合回路基板に接着するモールド枠として、3辺が閉じて1辺が開いているもの、あるいは1辺の一部に途切れた箇所を設けたものを集合回路基板に接着し、この上に集合上板を接着して箱状にし、モールド枠の途切れた部分である注入口から樹脂を注入して硬化させ、各回路領域を区分する切断線に沿ってダイシングする。 Alternatively, as a mold frame that adheres to the collective circuit board, those three sides are one side is open is closed, or those in which a portion where discontinuity in a part of one side was adhered to a set circuit board, the box-like by bonding a set top plate thereon, by injecting resin from the injection port is interrupted portions of the mold frame and cured, diced along cutting lines for partitioning each circuit area.
【0013】 [0013]
さらに別の方法では、集合回路基板に実装した回路部品に集合上板を当接させて乗せる。 In yet another method, put by abutting a set top plate to the circuit component mounted to the set circuit board. つまり回路部品のうちもっとも背の高いものを集合回路基板と集合上板の間隔を決めるスペーサに用いる。 That used in the spacer for determining the distance between the collective circuit board and set the upper most higher Tall of the circuit components. このように集合回路基板と集合上板を重ねておいて、周囲を封止テープで封止する。 Thus keep overlapping a set circuit board as a set top plate, sealing the periphery with a sealing tape. ただし周囲を全部ふさがず、一部、樹脂の注入口として開けておく。 However not closed all around, some, previously opened as an injection port of the resin. そして注入口から樹脂を注入して硬化させ、各回路領域を区分する切断線に沿ってダイシングする。 And from the injection port of the resin injected and cured, diced along cutting lines for partitioning each circuit area.
【0014】 [0014]
上板には絶縁材を用いるなり、あるいは回路部品の表面が十分に絶縁されていて短絡の恐れがないならば、金属板を用いるなりする。 Nari an insulating material in the upper plate, or if there is no risk of short circuit it is sufficiently insulating surface of the circuit component, to Nari using a metal plate. 絶縁塗装した金属板を用いたり、絶縁材の上板に金属層を重ねるなりしてもよく、このように金属板や金属層を設けることにより遮蔽機能が得られ、従来のようなシールド・ケースを用いなくとも信頼性が保たれる。 Or an insulating painted metal plate, may be Nari stacking metal layer to the upper plate of insulating material, the shielding function can be obtained by providing such a metal plate or a metal layer, a conventional shield case as reliability can be maintained without using the.
【0015】 [0015]
【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION
以下、図面に基づいて本発明の実施形態を説明する。 Hereinafter, an embodiment of the present invention with reference to the accompanying drawings.
図1は、本発明による電子回路のパッケージ方法の第1の実施形態を示す。 Figure 1 shows a first embodiment of the packaging method of an electronic circuit according to the invention.
図1(A)にて、1は集合回路基板で個々の電子回路の基板となる領域を多数含んでおり、チップ・マウンタによって各領域にそれぞれ回路部品2を実装する。 1 at (A), 1 is includes a number of areas where the substrate of each of the electronic circuits of a set circuit board, respectively mounting the circuit component 2 to each area by chip mounter. 3は樹脂製のモールド枠で額縁状であり、これを接着剤で集合回路基板1に接着する。 3 is a frame shape made of resin molded frame, to adhere to the collective circuit board 1 with an adhesive thereto. 次に同図(B)にて、モールド枠3の内側に樹脂5を注入して回路部品を樹脂5中に封入する。 Next in FIG. (B), the circuit components are sealed in the resin 5 by injecting resin 5 inside the mold frame 3. 次に同図(C)にて、接着剤で集合上板12をモールド枠3上に接着し、樹脂5を硬化させて集合回路基板1、モールド枠3および集合上板12の全体を接合する。 Next in FIG. (C), a set top plate 12 with an adhesive adhered on the mold frame 3, to join the entire set by curing the resin 5 circuit board 1, the mold frame 3, and set the upper plate 12 . これを同図(D)に示すように各回路領域の境界線である切断線6に沿ってダイシングすれば、1枚の集合回路基板1からパッケージされた電子回路7が多数個取りされる。 If diced along the cutting line 6 which is a boundary line of each circuit region to indicate this in FIG. 1 (D), an electronic circuit 7 packaged from a single collective circuit board 1 is multi-piece. モールド枠3は厚さが回路部品の中で最も背の高いものと同じかそれよりやや厚い程度であればよい。 Mold frame 3 may be a degree slightly larger or equal than the most those tall in the circuit component thickness.
【0016】 [0016]
図2は本発明の第2の実施形態である。 Figure 2 is a second embodiment of the present invention. まず、同図(A)のように回路部品2を実装した集合回路基板1、モールド枠3、それから集合上板12を接着剤で一体に接合する。 First, joining together collective circuit board 1 mounted with the circuit components 2 as shown in FIG (A), the mold frame 3, then the set top plate 12 with an adhesive. この実施形態ではモールド枠3は4辺が閉じたものでなく、1辺がなくて開口しているものを用いる。 No mold frame 3 in which four sides are closed in this embodiment, use one one side is opening without. 図2(B)の左側はこうして箱型に接合したものを立てた様子で、モールド枠3が上辺で開口している箇所は樹脂の注入口13となる。 In state left thus erected those bonded to a box-type of FIG. 2 (B), portions of the mold frame 3 is open at the upper side is an inlet 13 of the resin. モールド枠3は一辺を全部除くのでなく、同図の右側のもののように、上辺の一部に途切れた箇所を設けて注入口13にしてもよい。 Mold frame 3 is not the exclusion all side, so that those on the right side in the figure, may be the inlet 13 provided with a portion where discontinuity in a part of the upper side. 同図(C)のように注入口13から樹脂5を注入して箱の内部を充填する。 Filling the interior of the box by injecting resin 5 from the injection port 13 as shown in FIG. (C). 樹脂5を硬化させて切断線6に沿ってダイシングすれば、多数の電子回路パッケージが得られる。 If diced along the cutting line 6 by curing the resin 5, a number of electronic circuit packages is obtained.
【0017】 [0017]
図3は本発明の第3の実施形態で、この方法では先の二つの実施形態のようにモールド枠を用いることをしない。 Figure 3 is a third embodiment of the present invention, not the use of the mold frame as in the previous two embodiments in this way. 同図(A)にて、集合回路基板1に実装した回路部品2の上に集合上板12を重ねる。 In FIG (A), overlapping set top plate 12 on the circuit components 2 mounted on the collective circuit board 1. これを側面から見た状態を同図(A′)に示すが、集合上板12は下面が回路部品2のうち一番背の高いものに接して乗っており、回路部品2を集合回路基板1と集合上板12の間隔を決めるスペーサに使っているのである。 It shows a state seen this from the side in FIG. (A '), a set top plate 12 rests in contact with one lower surface having the highest profile of the circuit components 2, collective circuit board circuit components 2 1 that you are using the spacer for determining the distance of the set top plate 12. ワイヤ・ボンディングしたICチップはスペーサに適しないが、通常、電子回路はこれよりも背の高い回路部品を含んでいる。 Wire bonding the IC chip is not suitable for the spacer but usually electronic circuit includes a tall circuit components than this. 次にこのように重ねた集合回路基板1と集合上板12の周囲を、図3(B)に示すように注入口13を残して粘着性テープ等の封止テープ14で封止する。 Then the periphery of the collective circuit board 1 and the set upper plate 12 overlaid as this, is sealed with a sealing tape 14, such as adhesive tape, leaving the inlet 13 as shown in Figure 3 (B). 同図(C)のように注入口13から樹脂5を注入して内部を充填し、樹脂5を硬化させて封止テープ14を剥し、切断線6に沿ってダイシングする。 Filling the interior by injecting the resin 5 from the injection port 13 as shown in FIG. (C), peeled off sealing tape 14 to cure the resin 5 is diced along cutting lines 6.
【0018】 [0018]
集合上板12は、絶縁材であれば短絡を起こしたりせずに下面を回路部品2に当接させることができる。 Set top plate 12 can abut the lower surface to the circuit component 2 without or cause a short circuit if the insulating material. 製品の薄型化のため、強度の許す範囲で極力薄手の材料(例えば0.1mm前後)を用いる。 For thinner products, the extent permitted by strength using as much as possible thin material (e.g. 0.1mm so). モジュールの機能によってはフォト・トランジスタ、フォト・ダイオード、LED等の受光、発光の光電素子を含むから、その場合は集合上板12は光を通すことが必要で、光の強度に応じて透明または半透明の樹脂材料等を用いる。 Phototransistor Depending on the capabilities of the module, the photo diode, the light receiving of the LED or the like, because including a photoelectric element emitting, in which case must be set upper plate 12 through a light, transparent or according to the intensity of light using a semi-transparent resin material. しかし他方に遮光を要する回路部品があるなら、その箇所は集合上板12にマスク印刷などを施しておく。 But if there is a circuit component that requires the other to shading, that portion is kept subjected to such mask printing to the set top plate 12.
【0019】 [0019]
回路部品2の表面が十分に絶縁性であれば集合上板12を金属板にでき、金属上板からはシールド作用が得られる。 If the surface is sufficiently insulating the circuit components 2 can aggregate the upper plate 12 to the metal plate, the shield effect is obtained from a metal top plate. シールド作用の安定のために金属の上板を回路基板の接地パターンに接続するには、例えば接地パターン上に接地用のばね片や導電エラストマ等を置いて上板の下面に当接させるなどの構造を取ることができる。 To connect to a ground pattern of the circuit board a metal top plate for stabilizing the shield effect, for example, such as to abut against the lower surface of the upper plate at a spring piece and a conductive elastomer or the like for grounding on the ground pattern structure can take. 金属上板は、シールド作用以外にも遮光性や放熱性に優れるという利点がある。 Metal top plate has the advantage that excellent in light shielding property and heat radiation in addition to shielding effects.
金属上板の下面を絶縁塗装などして回路部品に当接させてもよい。 The lower surface of the metal upper plate may be brought into contact with the circuit components by an insulating coating. 金属上板を接地するには、下面の絶縁被覆を一部省き、ここに前記の接地用ばね片等が当接するようにする。 To ground the metal upper plate is omitted part lower surface of the insulating coating, the grounding spring pieces like the is into contact here.
【0020】 [0020]
以上、本発明の実施形態をいくつか示したが、これらで見たようなモールド枠3や封止テープ14を使わず、治具や取り付け具を用いて本発明の方法を行うこともできる。 Although the embodiments of the present invention showed some without a mold frame 3 and the sealing tape 14, as seen in these, the jigs and fixtures, it is also possible to carry out the present invention with reference. 詳細は省くが、例えば図1の方法の場合、集合回路基板1の周囲に樹脂注入のための壁を設けるのにモールド枠3を接合するのでなく、周囲に壁のある箱状の治具の中に集合回路基板1を置いて樹脂を注入し、集合上板12を乗せる方法でもよい。 Without going into details, for example, in the case of the method of FIG. 1, not to join the mold frame 3 to provide a wall for the resin injected into the periphery of the collective circuit board 1, the box-shaped jig having the wall around the resin is injected at a set circuit board 1 in, or a method of putting a set top plate 12. あるいは図2や図3の方法の場合、上方が開いた「コ」の字型の治具に集合回路基板1と集合上板12を取り付けることによって周辺の3方をふさぎ、開口部から樹脂を注入、硬化させてもよい。 Or in the case of the method of FIG. 2 and FIG. 3, block the 3-way around by attaching a set circuit board 1 and the set upper plate 12 shaped jig upwardly open "U", the resin from the opening injection, may be cured. 治具の幅を増せば1個の治具に集合回路基板1と集合上板12を何組も平行に取り付けられるから、能率よく回路のパッケージを行える。 Since it mounted Invite Maze width jig one jig a set circuit board 1 and the set top plate 12 parallel nothing set, perform the efficiently circuit package. このような方法も本発明の範囲内である。 Such methods are within the scope of the present invention.
【0021】 [0021]
【発明の効果】 【Effect of the invention】
本発明による電子回路のパッケージ方法によれば、樹脂が回路基板と上板で挟まれているので、電子回路を多数個取りする面積の大きな集合回路基板を用いる製造方法において基板の反りを防ぐことができ、加工精度や歩留まりが向上する。 According to method of packaging an electronic circuit according to the present invention, the resin is sandwiched by the circuit board and the upper plate, preventing the warpage of the substrate in the manufacturing method using a large set circuit board area of ​​a large number of electronic circuit-cavity It can be, improved machining accuracy and yield. ダイシングして完成した電子回路は周囲が樹脂面であってモールド枠を含まず、樹脂の乗ってない基板領域もないから製品の面積を小さくでき、1枚の集合回路基板からの電子回路の取り個数が増えて製造コストが下がる。 Electronic circuit completed by dicing is free of mold frame a surrounding resin surface, because there is no substrate areas not riding resin can reduce the area of ​​the product, taken in the electronic circuit from one set circuit board the number is increased by the production cost is reduced. 電子回路が上板で保護されているので、従来使えなかったような柔らかい樹脂を使うことが可能になって生産性が上がり、また、電子回路の用途や雰囲気に応じて最適の樹脂を選ぶことができて製品の信頼性が高まる。 Since the electronic circuit is protected by a top plate, it made it possible to use a soft resin as was used prior increases productivity, also possible to choose the best of resin depending on the application and feel of the electronic circuit the reliability of the product increases made. 回路基板と上板の間隔はモールド枠や回路部品をスペーサにして定まるから、製品の高さのばらつきがなくなりパッケージの厚さを薄くできる。 Since the distance between the circuit board and the top plate is determined by the mold frame and the circuit component to the spacer, it can reduce the thickness of the eliminated variations in the product height package. 更に、製品の上面がフラットな上板で構成されているためマウンターによるマウントを確実にすることができる。 Furthermore, the upper surface of the product can ensure mounting by the mounter because it is constituted by a flat upper plate. 従って、電子機器への実装が容易になる。 Therefore, to facilitate the implementation of the electronic equipment. このように本発明の電子回路のパッケージ方法は電子回路の生産性の向上と小型化、薄型化を可能にし、ひいてはこのような回路を用いた電子機器の低廉化、小型化に寄与する。 Thus packaging method of an electronic circuit of the present invention is improved and the size reduction of the productivity of the electronic circuit, enables thinner and thus cost reduction of an electronic apparatus using such a circuit, which contributes to miniaturization.
【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS
【図1】本発明の電子回路のパッケージ方法の一実施形態の手順を示す斜視図である。 1 is a perspective view showing the procedure of an embodiment of a method of packaging an electronic circuit of the present invention.
【図2】本発明の電子回路のパッケージ方法の別の実施形態の手順を示す斜視図である。 Is a perspective view showing the procedure of another embodiment of a method of packaging an electronic circuit of the invention; FIG.
【図3】本発明の電子回路のパッケージ方法のさらに別の実施形態の手順を示す斜視図である。 3 is a perspective view showing still procedure of another embodiment of a method of packaging an electronic circuit of the present invention.
【図4】従来の電子回路のパッケージで、図(A)、(C)はそれぞれ外観図、図(B)、(D)はそれぞれ図(A)、(C)のB−B断面図、D−D断面図である。 [4] In the package of a conventional electronic circuit, FIG (A), (C), respectively an external view, Figure (B), (D), respectively showing (A), B-B sectional view of (C), it is a D-D cross-sectional view.
【図5】従来の電子回路のパッケージ方法の手順を示す斜視図である。 5 is a perspective view showing a procedure of a method of packaging conventional electronic circuits.
【図6】従来の電子回路のパッケージ方法において、回路部品を実装した集合回路基板に樹脂をモールドした状態を示す断面図である。 [6] In packaging method of a conventional electronic circuit is a sectional view showing a state in which the molding resin to set the circuit board mounted with circuit components.
【符号の説明】 DESCRIPTION OF SYMBOLS
1 集合回路基板2、103 回路部品3、104 モールド枠5、105 樹脂6 切断線7 電子回路8 モールド・リブ9 金型12 集合上板13 注入口14 封止テープ101 回路基板102 ICチップ106 シールド・ケース 1 set circuit board 2,103 CC 3,104 mold frame 5,105 resin 6 cut line 7 electronics 8 mold ribs 9 die 12 set the upper plate 13 injection port 14 sealing tape 101 circuit board 102 IC chip 106 shields ·Case

Claims (3)

  1. 集合回路基板に設けた複数の回路領域にそれぞれ回路部品を実装し、 Respectively mounting the circuit components on a plurality of circuit region provided in the collective circuit board,
    前記集合回路基板の周辺に額縁状のモールド枠を接着して、その内側に樹脂を注入し、 By bonding a frame-shaped mold frame around the collective circuit board, the resin is injected into the inside,
    前記モールド枠およびその内側の前記樹脂層の上に集合上板を乗せて樹脂を硬化させ、 前記集合回路基板と前記モールド枠と前記樹脂層と前記集合上板を一体化した後、 After the ride the set top plate on top of the mold frame and the resin layer of the inner to cure the resin, integrating the set upper the set circuit board and the mold frame and said resin layer,
    この一体化物を各回路領域別に切断することにより、 前記回路部品を樹脂に封入して、前記集合回路基板を分割した個別の回路基板と前記集合上板を分割した個別の上板で挟持した構造を得る電子回路のパッケージ方法。 By cutting the integrated product for each circuit region, said circuit component encapsulated in a resin, is sandwiched between a separate top plate obtained by dividing the set upper and individual circuit board obtained by dividing the aggregate circuit board packaging method of an electronic circuit for obtaining a structure.
  2. 集合回路基板に設けた複数の回路領域にそれぞれ回路部品を実装し、 Respectively mounting the circuit components on a plurality of circuit region provided in the collective circuit board,
    前記集合回路基板および別に用意した集合上板の周囲を、ある一辺の一部または全部を開口して注入口としたモールド枠を挟んで接合し、 Wherein the periphery of the set circuit sets upper plate prepared substrate and the separate, joined across the inlet and the mold frame opens a part or all of a side,
    この接合体を注入口を上に向けて立てた姿勢にして前記注入口から樹脂を注入し硬化させて、前記集合回路基板と前記モールド枠と前記樹脂層と前記集合上板を一体化した後、 The conjugate was the inlet to the posture standing facing upward, from said inlet by hardening resin is injected, integrated the set upper the set circuit board and the mold frame and said resin layer after,
    この一体化物を各回路領域別に切断することにより、 前記回路部品を樹脂中に封入して、前記集合回路基板を分割した個別の回路基板と前記集合上板を分割した個別の上板で挟持した構造を得る電子回路のパッケージ方法。 By cutting the integrated product for each circuit region, said circuit component encapsulated in a resin, is sandwiched between a separate top plate obtained by dividing the set upper and individual circuit board obtained by dividing the aggregate circuit board packaging method of an electronic circuit for obtaining a structure.
  3. 集合回路基板に設けた複数の回路領域にそれぞれ回路部品を実装し、 Respectively mounting the circuit components on a plurality of circuit region provided in the collective circuit board,
    前記回路部品に当接させて集合上板を配置することにより前記集合回路基板と前記集合上板の間隔を定め、 Define an interval of the set circuit board and the set upper by placing the set top plate is brought into contact with the circuit component,
    前記集合回路基板と前記集合上板の周囲を樹脂の注入口を残して封止テープで封止し、 前記注入口から樹脂を注入し硬化させて、 前記集合回路基板と前記樹脂層と前記集合上板を一体化した後、 Wherein the periphery of the collective circuit board and the set upper sealed with sealing tape, leaving an inlet of the resin, and the resin injected and cured from the inlet, the said collective circuit board and the resin layer set after the integration of the upper plate,
    この一体化物を各回路領域別に切断することにより、 前記回路部品を樹脂中に封入して、前記集合回路基板を分割した個別の回路基板と前記集合上板を分割した個別の上板で挟持した構造を得る電子回路のパッケージ方法。 By cutting the integrated product for each circuit region, said circuit component encapsulated in a resin, is sandwiched between a separate top plate obtained by dividing the set upper and individual circuit board obtained by dividing the aggregate circuit board packaging method of an electronic circuit for obtaining a structure.
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Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001210755A (en) * 2000-01-28 2001-08-03 Nec Corp Substrate for semiconductor device and method of manufacturing semiconductor device
DE10014380A1 (en) * 2000-03-23 2001-10-04 Infineon Technologies Ag A device for packaging electronic components
JP5592055B2 (en) 2004-11-03 2014-09-17 テッセラ,インコーポレイテッド Improvement of the laminated packaging
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
JP5427374B2 (en) * 2008-06-25 2014-02-26 協立化学産業株式会社 The method of manufacturing an electronic component module and the electronic component module
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
KR101075241B1 (en) 2010-11-15 2011-11-01 테세라, 인코포레이티드 Microelectronic package with terminals on dielectric mass
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
KR101128063B1 (en) 2011-05-03 2012-04-23 테세라, 인코포레이티드 Package-on-package assembly with wire bonds to encapsulation surface
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
JP6115505B2 (en) 2013-06-21 2017-04-19 株式会社デンソー The electronic device
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
KR20150042043A (en) * 2013-10-10 2015-04-20 삼성전기주식회사 Frame Stiffener For Semiconductor Package And Method For Manufacturing The Same
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
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