KR101011863B1 - Semiconductor package and fabricating?method thereof - Google Patents

Semiconductor package and fabricating?method thereof Download PDF

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Publication number
KR101011863B1
KR101011863B1 KR1020080120884A KR20080120884A KR101011863B1 KR 101011863 B1 KR101011863 B1 KR 101011863B1 KR 1020080120884 A KR1020080120884 A KR 1020080120884A KR 20080120884 A KR20080120884 A KR 20080120884A KR 101011863 B1 KR101011863 B1 KR 101011863B1
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South Korea
Prior art keywords
semiconductor die
upper
solder ball
substrate
encapsulant
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KR1020080120884A
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Korean (ko)
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KR20100062315A (en
Inventor
강대병
김광호
김진성
박동주
Original Assignee
앰코 테크놀로지 코리아 주식회사
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Priority to KR1020080120884A priority Critical patent/KR101011863B1/en
Publication of KR20100062315A publication Critical patent/KR20100062315A/en
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    • HELECTRICITY
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    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • HELECTRICITY
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    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2225/1041Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
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    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

The present invention relates to a semiconductor package capable of realizing a high performance semiconductor package by forming an upper land on an upper surface of the semiconductor package and increasing the number of input / output terminals without increasing the size of the semiconductor package, and a method of manufacturing the same.
A semiconductor package according to the present invention includes a substrate having a plurality of conductive patterns on an upper surface and a plurality of lower lands electrically connected to the conductive pattern on a lower surface of the semiconductor package; A first semiconductor die formed on the substrate and electrically connected to the conductive pattern; An upper solder ball formed on the substrate to be spaced apart from the first semiconductor die and electrically connected to the conductive pattern; A plurality of upper lands formed on the first semiconductor die and the upper solder ball and electrically connected to the upper solder ball; And an encapsulant formed on the substrate to surround the first semiconductor die and the upper solder ball.
Semiconductor Die, Encapsulant, Land, Solder Ball, TMV

Description

Semiconductor package and its manufacturing method {SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF}

The present invention relates to a semiconductor package capable of realizing a high performance semiconductor package by forming an upper land on an upper surface of the semiconductor package and increasing the number of input / output terminals without increasing the size of the semiconductor package, and a method of manufacturing the same.

Recently, electronic products are manufactured using semiconductor packages. These products are required to be smaller in size, while their functionality is required to be increased. In accordance with this trend, the semiconductor package constituting the product is also required to be light and thin.

In general, the semiconductor package is connected to an external circuit board through solder balls or lands exposed to the bottom surface. When the size of such a semiconductor package itself is reduced, space for forming an input / output terminal is limited. Accordingly, when the size of the semiconductor package is reduced, it is difficult to realize various functions of the semiconductor package.

In order to solve this problem, a package on package (POP) technology for stacking a semiconductor package on top of a semiconductor package or a package in packge (PIP) technology for mounting a semiconductor package inside a semiconductor package has been developed. Since the input and output terminals are formed on the lower surface of the semiconductor package, these technologies also have difficulty securing the input and output terminals, and there are still limited problems in implementing various functions of the semiconductor package.

An object of the present invention is to provide a semiconductor package and a method of manufacturing the semiconductor package that can implement a high-performance semiconductor package by increasing the number of input and output terminals without increasing the size of the semiconductor package by forming an upper land on the upper surface of the semiconductor package.

In order to achieve the above object, a semiconductor package according to an embodiment of the present invention has a substrate having a plurality of conductive patterns on the upper surface, a lower substrate having a plurality of lower lands electrically connected to the conductive pattern; A first semiconductor die formed on the substrate and electrically connected to the conductive pattern; An upper solder ball formed on the substrate to be spaced apart from the first semiconductor die and electrically connected to the conductive pattern; A plurality of upper lands formed on the first semiconductor die and the upper solder ball and electrically connected to the upper solder ball; And an encapsulant formed on the substrate to surround the first semiconductor die and the upper solder ball.

The encapsulant surrounds the plurality of upper lands, and an upper surface of the encapsulant and an upper surface of the upper land may form the same plane.

In addition, the semiconductor package according to the embodiment of the present invention may further include a conductive bump formed under the first semiconductor die to electrically connect the first semiconductor die and the conductive pattern.

In addition, the semiconductor package according to the embodiment of the present invention may further include a lower solder ball formed under the substrate and electrically connected to the lower land.

In addition, the semiconductor package according to the embodiment of the present invention may further include a second semiconductor die formed on the first semiconductor die and electrically connected to the upper land through a conductive wire.

The encapsulant surrounds the upper land, the second semiconductor die, and the conductive wire, and an upper surface of the encapsulant, an upper surface of the upper land, and an upper surface of the second semiconductor die may be coplanar.

The first semiconductor die may be attached to an upper portion of the substrate using an adhesive member, and may be electrically connected to the conductive pattern using a conductive wire.

In addition, the semiconductor package according to the embodiment of the present invention may further include a second semiconductor die attached to an upper portion of the first semiconductor die by using an adhesive member and electrically connected to the conductive pattern by using a conductive wire.

In addition, the semiconductor package according to the embodiment of the present invention may further include a through mold via (TMV) formed to penetrate the encapsulant and electrically connected to the upper solder ball.

The upper land may be formed to protrude on an upper portion of the encapsulant, and may be electrically connected to the TMV.

In order to achieve the above object, a method of manufacturing a semiconductor package according to an embodiment of the present invention has a sub-side having a plurality of conductive patterns on the upper surface, a substrate having a plurality of lower lands electrically connected to the conductive pattern on the lower surface Straight preparation step; A semiconductor die disposed on the substrate to electrically connect with the conductive pattern, and an upper solder ball formed on the substrate to be spaced apart from the first semiconductor die to electrically connect with the conductive pattern. Connecting and forming an upper solder ball; A carrier bonding step of bonding the circuit pattern to the upper solder ball by disposing a carrier having a circuit pattern formed on the first semiconductor die; An encapsulant forming step of encapsulating the first semiconductor die, the upper solder ball, and the circuit pattern to form an encapsulant between the substrate and the carrier; And removing a carrier to form an upper land on an upper surface of the encapsulant.

The connecting of the semiconductor die and the forming of the upper solder ball may include electrically connecting the first semiconductor die and the conductive pattern by using a conductive bump formed under the first semiconductor die.

The carrier bonding step may include forming the circuit pattern with a conductive material and preparing the carrier by forming a material different from the circuit pattern.

The carrier removing step may be performed by an etching process.

In addition, the method of manufacturing a semiconductor package according to an embodiment of the present invention may further include forming a lower solder ball on the lower portion of the substrate and electrically connecting the lower land to the lower land.

The carrier bonding may further include forming a second semiconductor die on the carrier, the second semiconductor die being electrically connected to the circuit pattern through a conductive wire.

In order to achieve the above object, a method of manufacturing a semiconductor package according to another embodiment of the present invention has a substrate having a plurality of conductive patterns on the upper surface, a substrate having a plurality of lower lands electrically connected to the conductive pattern on the lower surface A substrate preparation step; A semiconductor die attached to an upper portion of the substrate to electrically connect with the conductive pattern, and an upper solder ball formed on the substrate to be spaced apart from the first semiconductor die to electrically connect with the conductive pattern Connecting and forming an upper solder ball; An encapsulant forming step of encapsulating the first semiconductor die and the upper solder ball to form an encapsulant on the substrate; Forming a through hole in an area of the encapsulant corresponding to the upper solder ball to expose the solder ball to the outside; Forming a TMV (Through Mold Via) electrically connected to the upper solder ball by applying a conductive material to the inside of the through hole; A carrier bonding step of bonding the circuit pattern to the TMV by disposing a carrier on which a circuit pattern is formed on the first semiconductor die; And removing a carrier to form an upper land on an upper surface of the encapsulant.

The step of connecting the semiconductor die and forming the upper solder ball may include attaching the first semiconductor die to the upper portion of the substrate using an adhesive member, and electrically connecting the conductive pattern to the conductive pattern using a conductive wire.

The step of connecting the semiconductor die and forming the upper solder ball may include attaching a second semiconductor die to the upper portion of the first semiconductor die using an adhesive member, and electrically connecting the conductive pattern to the conductive pattern using a conductive wire.

According to an embodiment of the present invention, a semiconductor package and a method of manufacturing the same may form an upper land on an upper surface of a semiconductor package using a carrier on which a circuit pattern is formed, thereby increasing the number of input / output terminals of the semiconductor package without increasing the size of the semiconductor package. Can be. Accordingly, the semiconductor package and the method of manufacturing the same according to the embodiment of the present invention can implement a high performance semiconductor package.

Hereinafter, a semiconductor package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings and embodiments.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor package 100 according to an embodiment of the present invention may include a substrate 10, a first semiconductor die 20, a plurality of conductive bumps 30, a plurality of upper solder balls 40, It may include a plurality of upper lands 50, an encapsulant 60, and a plurality of lower solder balls 70.

The substrate 10 has a substantially plate shape. The substrate 10 is formed on a plurality of conductive vias 11 penetrating through the substrate 10, a plurality of conductive patterns 12 formed on an upper surface thereof and electrically connected to the conductive vias 11, and formed on a lower surface of the substrate 10. A plurality of lower lands 13 are electrically connected to the conductive vias 11. In addition, the substrate 10 further includes a solder mask 14 covering a region exposed to the lower portion of the substrate 10 except for a region in which the lower solder ball 70 is to be formed in the lower land 13. can do.

The first semiconductor die 20 is formed on the substrate 10 to be electrically connected to the conductive pattern 12. The first semiconductor die 20 refers to a circuit in which a plurality of transistors, resistors, capacitors, and the like are integrated on a silicon substrate. The first semiconductor die 20 may control a machine or store information. Here, although the first semiconductor die 20 is shown as a bump type die, a general semiconductor die electrically connected to the substrate by a conductive wire may be used.

The conductive bumps 30 are formed under the first semiconductor die 20 to electrically connect the first semiconductor die 20 and the conductive pattern 12. Accordingly, the conductive bumps 30 electrically connect the first semiconductor die 20 and the substrate 10.

The upper solder ball 40 is formed to be spaced apart from the first semiconductor die 20 on the substrate 10. The upper solder ball 40 is formed in a ball shape on the conductive pattern 12, and is electrically connected to the conductive pattern 12. Here, the upper solder ball 40 is formed to have a height higher than the height of the first semiconductor die 20 is disposed on the substrate 10, the upper land 50 to be described later is the first semiconductor die It is possible to prevent unnecessary contact with the 20 and to easily contact the surface of the upper solder ball 40.

The upper land 50 is formed on the first semiconductor die 20 and the upper solder ball 40 to be electrically connected to the upper solder ball 40. The upper land 50 is a region where the semiconductor package 100 is surface-mounted through solder or the like to an external device, and is exposed to an upper portion of the encapsulant 60 to be described later. The upper land 50 may be formed of a conductive material.

The encapsulant 60 is formed on the substrate 10 so as to surround the first semiconductor die 20, the upper solder ball 40, and the upper land 50. The encapsulant 60 maintains the appearance of the semiconductor package 100 and protects the first semiconductor die 20 and the like. The encapsulant 60 may be formed by a molding process using any one selected from conventional epoxy resins, silicone resins, or equivalents thereof. Here, the encapsulant 60 is formed such that an upper surface thereof is coplanar with an upper surface of the upper land 50 so as to expose the upper land 50.

The lower solder ball 70 may be formed in a ball shape on the lower land 13 of the substrate 10. The lower solder ball 70 facilitates electrical and mechanical contact between semiconductor packages or with external devices when the semiconductor package 100 is stacked in another package or mounted on an external device. The lower solder ball 70 may be formed of a solder material.

As described above, the semiconductor package 100 according to the exemplary embodiment of the present invention increases performance by securing a larger number of input / output terminals without increasing the size of the semiconductor package through the upper land 50 in addition to the lower land 13. The semiconductor package can be implemented.

In addition, the semiconductor package 100 according to an embodiment of the present invention may facilitate the electrical interconnection between the upper and lower portions of the semiconductor package by using the upper solder ball 40.

Next, a semiconductor package according to another embodiment of the present invention will be described.

The semiconductor package 200 according to another embodiment of the present invention is different from the semiconductor package 100 according to an embodiment of the present invention except that the second semiconductor die 152 is further provided, and has the same components. Do the same. Accordingly, the same reference numerals will be given to the same configuration, and duplicate descriptions will be omitted, and the second semiconductor die 152 will be mainly described.

2 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention.

2, a semiconductor package 200 according to another embodiment of the present invention may include a substrate 10, a first semiconductor die 20, a plurality of conductive bumps 30, a plurality of upper solder balls 40, The plurality of upper lands 50, the encapsulant 60, the plurality of lower solder balls 70, and the second semiconductor die 152 may be included.

The second semiconductor die 152 is formed on the first semiconductor die 20, through the upper land 50 and the conductive wire 154 positioned on the first semiconductor die 20. Electrically connected.

Like the first semiconductor die 20, the second semiconductor die 152 may control a machine or store information. Here, the second semiconductor die 152 may be formed such that an upper surface thereof is coplanar with an upper surface of the encapsulant 60, and may be exposed to an upper portion of the encapsulant 60. Accordingly, heat dissipation characteristics in which heat generated during operation of the second semiconductor die 152 is discharged to the outside may be improved.

As described above, the semiconductor package 200 according to another embodiment of the present invention is not only the first semiconductor die 20 but also through the second semiconductor die 152, the semiconductor package 100 shown in FIG. 1. Higher performance semiconductor packages can be realized.

Next, a semiconductor package according to another embodiment of the present invention will be described.

3 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention.

Referring to FIG. 3, a semiconductor package 300 according to another embodiment of the present invention may include a substrate 210, a first semiconductor die 220, a second semiconductor die 230, a conductive wire 240, and a plurality of semiconductor packages 300. The upper solder ball 250, the encapsulant 260, a through mold via (TMV) 270, a plurality of upper lands 280, and a plurality of lower solder balls 290 may be included.

The substrate 210 has a difference only in the formation patterns of the conductive via 11, the conductive pattern 12, and the lower land 13, compared to the substrate 10 shown in FIG. 1, and thus plays the same role. Duplicate explanations will be omitted.

The first semiconductor die 220 is attached to an upper portion of the substrate 210 using an adhesive member 221 as compared to the first semiconductor die 20 shown in FIG. 1, and a bond pad 222 formed on the upper portion of the substrate 210. ), And only duplicated descriptions will play the same role.

The second semiconductor die 230 is attached to an upper portion of the first semiconductor die 220 by using an adhesive member 221 and includes a bond pad 232 formed thereon. The second semiconductor die 230 plays the same role as the first semiconductor die 220.

The conductive wire 240 electrically connects the bond pad 222 of the first semiconductor die 220 and the conductive pattern 12, the bond pad 232 of the second semiconductor die 230, and the The conductive pattern 12 is electrically connected.

The upper solder ball 250 has a difference only in that it is formed at a lower height than the upper solder ball 40 shown in FIG. 1, and thus duplicated description will be omitted.

The encapsulant 260 may be formed of the first semiconductor die 220, the second semiconductor die 230, and the conductive parts, except for the upper land 280, which will be described later in comparison with the encapsulant 60 shown in FIG. 1. Since only the wire 240 and the upper solder ball 250 are formed to cover the same role, the duplicated description will be omitted.

The TMV 270 is formed through the encapsulant 260, one end of which is electrically connected to the upper solder ball 250, and the other end of the TMV 270 is exposed to an upper portion of the encapsulant 260.

The TMV 270 may electrically connect the first and second semiconductor dies 220 and 230 to an external device that is in electrical contact with the upper portion of the semiconductor package 300 as well as the lower portion of the semiconductor package 300 so that electrical signals may be input and output. have. The TMV 270 is a conductive material, for example, tin (Sb), lead (Pb), gold (Au), silver (Ag), copper (Cu), bismuth in the via hole penetrating the encapsulant 260 (bi) or an alloy thereof.

The upper land 280 is formed to protrude on the encapsulant 260 and is electrically connected to the TMV 270. Since the upper land 280 plays the same role as the upper land 50 illustrated in FIG. 1, duplicate descriptions thereof will be omitted.

Since the lower solder ball 290 has the same shape as the lower solder ball 70 shown in FIG. 1 and plays the same role, duplicated descriptions will be omitted.

As described above, the semiconductor package 300 according to another exemplary embodiment of the present invention is not only the first semiconductor die 220 but also the second semiconductor die 230, the semiconductor package 100 shown in FIG. 1. It is possible to realize a higher performance semiconductor package than).

In addition, the semiconductor package 300 according to another embodiment of the present invention facilitates electrical interconnection between the upper and lower parts of the semiconductor package 300 by using the upper solder ball 250 and the TMV 270. can do.

Next, a method of manufacturing the semiconductor package 100 according to an embodiment of the present invention will be described.

4 is a flowchart illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention, and FIGS. 5A to 5F are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 4, a method of manufacturing a semiconductor package 100 according to an embodiment of the present invention may include a substrate preparation step (S1), a semiconductor die connection and an upper solder ball forming step (S2), a carrier bonding step (S3), An encapsulant forming step S4, a carrier removing step S5, and a lower solder ball forming step S6 may be included.

Referring to FIG. 5A, the substrate preparing step S1 may include a plurality of conductive patterns 12 on an upper surface and a plurality of lower lands 13 electrically connected to the conductive patterns 12 on a lower surface thereof. A step of preparing the straight 10.

The conductive pattern 12 and the lower land 13 of the substrate 10 are connected to each other through the conductive via 11 and partially insulated through the solder mask 14. Since the substrate 10 has been sufficiently described above, a detailed description thereof will be omitted.

Referring to FIG. 5B, the semiconductor die connection and upper solder ball forming step (S2) is a step of connecting the first semiconductor die 20 to the upper portion of the substrate 10 and forming the upper solder ball 40.

Specifically, in the step of connecting the semiconductor die and forming the upper solder ball (S2), the first semiconductor die 20 may be disposed on the substrate 10, and the conductive die may be formed below the first semiconductor die 20. The bump 30 may be used to electrically connect the first semiconductor die 20 and the conductive pattern 12.

In addition, the semiconductor die connection and upper solder ball forming step (S2) may form the upper solder ball 40 spaced apart from the first semiconductor die 20 on the substrate 10, and the conductive pattern 12. Electrical connection. Here, the semiconductor die connection and the upper solder ball forming step (S2) is such that the upper solder ball 40 has a height higher than the height at which the first semiconductor die 20 is disposed on the substrate 10. do. Since this has been described above, duplicate descriptions will be omitted.

Referring to FIG. 5C, in the carrier bonding step S3, the carrier 52 on which the circuit pattern 51 is formed is disposed on the first semiconductor die 20 so that the circuit pattern 51 is disposed on the upper solder ball 40. It is a step of bonding to.

In the carrier bonding step S3, the circuit pattern 51 is formed of a conductive material, and the carrier 52 is formed of a material different from that of the circuit pattern 51. This is to facilitate the removal of only the carrier 52 by an etching process or the like in the removal step of the carrier. Here, the carrier 52 may be a lead frame or a tape.

Referring to FIG. 5D, the encapsulant forming step S4 is encapsulated to surround the first semiconductor die 20, the upper solder ball 40, and the circuit pattern 51, so that the substrate 10 and the substrate are encapsulated. The encapsulant 60 is formed between the carriers 52.

The encapsulant 60 protects the first semiconductor die 20, the upper solder ball 40, and the circuit pattern 51 from external impact. The encapsulant 60 may typically be formed of an epoxy resin, a silicone resin, or an equivalent thereof.

Referring to FIG. 5E, the carrier removing step S5 may be performed by removing the carrier 52 to form the upper land 50 on the upper surface of the encapsulant 60.

In detail, the carrier removing step S5 removes the carrier 52 formed of a material different from the circuit pattern 51 by using an etching process, and is exposed to an upper portion of the encapsulant 60. The land 50 is formed. The upper land 50 is electrically connected to an external device stacked on the semiconductor package 100 to provide a path for inputting and outputting an electrical signal to the semiconductor package 100.

Referring to FIG. 5F, the lower solder ball forming step S6 is formed under the substrate 10 to form a lower solder ball 70 electrically connected to the lower land 13.

The lower solder ball 70 is then connected to an external circuit of another semiconductor package stacked under the semiconductor package 100 to provide a path for inputting and outputting an electrical signal to the semiconductor package 100.

As described above, in the method of manufacturing the semiconductor package 100 according to the exemplary embodiment of the present invention, the upper land 50 exposed to the upper portion of the semiconductor package 100 using the carrier 52 on which the circuit pattern 51 is formed. ), It is possible to implement a high-performance semiconductor package having a large number of input and output terminals in the same size semiconductor package.

Next, a method of manufacturing the semiconductor package 200 according to another embodiment of the present invention will be described.

The manufacturing method of the semiconductor package 200 according to another embodiment of the present invention has only the same step as the carrier bonding step (S13) compared with the manufacturing method of the semiconductor package 100 according to an embodiment of the present invention, and has the same step. . Accordingly, duplicate descriptions of the same step will be omitted, and a description will be focused on the carrier bonding step S13.

6 is a flowchart illustrating a method of manufacturing a semiconductor package according to another exemplary embodiment of the present invention, and FIG. 7 is a cross-sectional view illustrating the carrier bonding step of FIG. 6.

Referring to FIG. 6, a method of manufacturing a semiconductor package 200 according to another embodiment of the present invention may include preparing a substrate (S1), connecting a semiconductor die and forming an upper solder ball (S2), a carrier bonding step (S13), An encapsulant forming step S4, a carrier removing step S5, and a lower solder ball forming step S6 may be included.

Referring to FIG. 7, the carrier bonding step S13 is similar to the carrier bonding step S3 shown in FIG. 5C. However, in the carrier bonding step S13, the carrier 52 having the second semiconductor die 152 further connected to the circuit pattern 51 using the conductive wire 154 may be formed as well as the circuit pattern 51. There is a difference in preparing. Accordingly, the carrier 52 in which the circuit pattern 51 and the second semiconductor die 152 are formed in the carrier bonding step S13 is disposed on the first semiconductor die 20, and the circuit pattern 51 ) Is bonded to the upper solder ball 40.

Thereafter, when the encapsulant forming step S4, the carrier removing step S5, and the lower solder ball forming step S6 are performed, the semiconductor package 200 illustrated in FIG. 2 is completed.

As described above, in the method of manufacturing the semiconductor package 200 according to another embodiment of the present invention, the semiconductor package 200 may be formed using the carrier 52 on which the circuit pattern 51 and the second semiconductor die 152 are formed. By easily forming the upper land 50 exposed to the top, it is possible to implement a high-performance semiconductor package having a large number of input and output terminals in the same size semiconductor package.

Next, a method of manufacturing a semiconductor package 300 according to another embodiment of the present invention will be described.

8 is a flowchart illustrating a method of manufacturing a semiconductor package according to still another embodiment of the present invention, and FIGS. 9A to 9H are cross-sectional views illustrating a method of manufacturing a semiconductor package according to still another embodiment of the present invention. .

Referring to FIG. 8, a method of manufacturing a semiconductor package 300 according to another embodiment of the present invention may include preparing a substrate (S21), connecting a semiconductor die, and forming an upper solder ball (S22) and forming an encapsulant ( S23), a through hole forming step S24, a TMV forming step S25, a carrier bonding step S26, a carrier removing step S27, and a lower solder ball forming step S28.

Referring to FIG. 9A, the substrate preparation step S21 includes a plurality of conductive patterns 12 on the upper surface, and a substrate having a plurality of lower lands 13 electrically connected to the conductive patterns 12 on the lower surface. Step 210 is to prepare. Here, the substrate preparation step (S21) is the formation of the conductive via 11, the conductive pattern 12 and the lower land 13 in the substrate 210 compared to the substrate preparation step (S1) shown in 5a Since only the patterns differ, duplicate descriptions will be omitted.

Referring to FIG. 9B, the semiconductor die connection and upper solder ball forming step (S22) is a step of connecting the first semiconductor die 220 to the upper portion of the substrate 210 and forming the upper solder ball 250.

Specifically, in the step of connecting the semiconductor die and forming the upper solder ball (S22), the first semiconductor die 220 is attached to the upper portion of the substrate 210 by using the adhesive member 221, and the conductive wire 240 is attached. The first semiconductor die 220 and the conductive pattern 12 are electrically connected to each other.

In addition, in the step of connecting the semiconductor die and forming the upper solder ball (S22), the second semiconductor die 230 is attached to the upper portion of the first semiconductor die 220 using the adhesive member 221, and the conductive wire 240 is attached. The second semiconductor die 230 and the conductive pattern 12 may be electrically connected to each other.

In addition, the semiconductor die connection and upper solder ball forming step (S22) may form the upper solder ball 250 spaced apart from the first semiconductor die 220 on the substrate 210 and the conductive pattern 12. Electrical connection. Here, the semiconductor die connection and the upper solder ball forming step (S22) may have the upper solder ball 250 lower or higher than the height at which the first semiconductor die 220 is disposed on the substrate 210. It can be formed so that.

Referring to FIG. 9C, the encapsulant forming step S23 may be encapsulated to surround the first semiconductor die 220, the second semiconductor die 230, and the upper solder ball 250, so that the substrate 210 may be encapsulated. Forming the encapsulant 260 on top of the step.

The encapsulant 260 protects the first semiconductor die 220, the second semiconductor die 230, and the upper solder ball 250 from an external impact. The encapsulant 260 may be typically formed of an epoxy resin, a silicone resin, or an equivalent thereof.

Referring to FIG. 9D, in the forming of the through hole (S24), a through hole 262 is formed in a region corresponding to the upper solder ball 250 of the encapsulant 260, and the upper solder ball 250 is moved to the outside. It is a step of exposing.

The through hole forming step S24 may be performed by a method such as laser drilling.

Referring to FIG. 9E, the TMV forming step S25 is a step of forming a TMV 270 electrically connected to the upper solder ball 250 by applying a conductive material to the inside of the through hole 262.

Application of the conductive material may be made by any one method selected from spraying, coating, printing and plating methods.

The TMV 270 formed by the above method is electrically connected to the conductive pattern 12 of the substrate 210. Accordingly, the TMV 270 electrically connects the first and second semiconductor dies 220 and 230 to an external circuit electrically contacting not only the bottom but also the top of the semiconductor package 300 of FIG. It can be done.

Referring to FIG. 9F, in the carrier bonding step S26, the carrier 52 on which the circuit pattern 51 is formed is disposed on the first semiconductor die 220 and the second semiconductor die 230, thereby forming a circuit pattern ( 51) to the TMV 270.

In the carrier bonding step S26, the circuit pattern 51 is formed of a conductive material, and the carrier 52 is formed of a material different from that of the circuit pattern 52. Since this has been described above, duplicate descriptions will be omitted.

Referring to FIG. 9G, the carrier removing step (S27) may be performed by removing the carrier 52 to form an upper land 280 on an upper surface of the encapsulant 260.

In detail, the carrier removing step S27 removes the carrier 52 formed of a material different from the circuit pattern 51 by using an etching process, and is exposed to the upper portion of the encapsulant 260. Land 280 is formed. The upper land 280 is electrically connected to an external device stacked on the semiconductor package 300 to provide a path for inputting and outputting an electrical signal to the semiconductor package 300.

9H, the lower solder ball forming step S28 is a step of forming a lower solder ball 290 formed under the substrate 210 and electrically connected to the lower land 13.

The lower solder ball 290 is then connected to an external circuit of another semiconductor package stacked under the semiconductor package 300 to provide a path for inputting and outputting an electrical signal to the semiconductor package 300.

As described above, the manufacturing method of the semiconductor package 300 according to another embodiment of the present invention by performing a carrier bonding step (S26) after the encapsulant forming step (S23), according to an embodiment of the present invention Compared to the case where the carrier bonding step S3 is performed before the encapsulant forming step S4 in the method of manufacturing the semiconductor package 100, the carrier 52 may be stably bonded.

In addition, in the method of manufacturing the semiconductor package 300 according to another embodiment of the present invention, the first and second semiconductor dies 220 and 230 are disposed on the substrate 210 in the step of connecting the semiconductor die and forming the upper solder balls (S22). By stacking, compared to the case in which the second semiconductor die 152 is separately formed in the carrier bonding step S3 in the method of manufacturing the semiconductor package 200 according to another embodiment of the present invention, the manufacturing process hassle can be reduced. have.

The present invention is not limited to the above-described specific preferred embodiments, and any person skilled in the art to which the present invention pertains may make various modifications without departing from the gist of the present invention as claimed in the claims. Of course, such changes are within the scope of the claims.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

2 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention.

3 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention.

4 is a flowchart illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.

5A through 5F are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with an embodiment of the present invention.

6 is a flowchart illustrating a method of manufacturing a semiconductor package according to another embodiment of the present invention.

FIG. 7 is a cross-sectional view for describing the carrier bonding step of FIG. 6.

8 is a flowchart illustrating a method of manufacturing a semiconductor package according to still another embodiment of the present invention.

9A to 9H are cross-sectional views illustrating a method of manufacturing a semiconductor package according to still another embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

10, 210: substrate 20, 220: first semiconductor die

30: conductive bump 40, 250: upper solder ball

50, 280: upper ram 60, 260: encapsulant

70, 290: solder balls 100, 200, 300: semiconductor package

152 230: second semiconductor die 154, 240: conductive wire

270: Through Mold Via (TMV)

Claims (22)

  1. A substrate having a plurality of conductive patterns on an upper surface and a plurality of lower lands electrically connected to the conductive pattern on a lower surface;
    A first semiconductor die formed on the substrate and electrically connected to the conductive pattern;
     An upper solder ball formed on the substrate to be spaced apart from the first semiconductor die and electrically connected to the conductive pattern;
    A plurality of upper lands formed on the first semiconductor die and the upper solder ball and electrically connected to the upper solder ball; And
    An encapsulant formed on the substrate to surround the first semiconductor die and the upper solder ball,
    And the plurality of upper lands are exposed to an upper portion of the encapsulant.
  2. The method of claim 1,
    The encapsulant surrounds the plurality of upper lands,
    And a top surface of the encapsulant and a top surface of the upper land form the same plane.
  3. The method of claim 1,
    And a conductive bump formed under the first semiconductor die to electrically connect the first semiconductor die and the conductive pattern.
  4. The method of claim 1,
    And a lower solder ball formed under the substrate and electrically connected to the lower land.
  5. The method of claim 1,
    And a second semiconductor die formed on the first semiconductor die and electrically connected to the upper land through a conductive wire.
  6. The method of claim 5,
    The encapsulant surrounds the upper land, the second semiconductor die and the conductive wire,
    And a top surface of the encapsulant, a top surface of the upper land, and a top surface of the second semiconductor die are coplanar.
  7. The method of claim 1,
    And the first semiconductor die is attached to an upper portion of the substrate using an adhesive member and electrically connected to the conductive pattern using a conductive wire.
  8. The method of claim 7, wherein
    And a second semiconductor die attached to an upper portion of the first semiconductor die using an adhesive member and electrically connected to the conductive pattern using a conductive wire.
  9. The method of claim 7, wherein
    And a through mold via (TMV) formed through the encapsulant and electrically connected to the upper solder ball.
  10. The method of claim 9,
    And the upper land is formed to protrude on an upper portion of the encapsulant and electrically connected to the TMV.
  11. A substrate preparation step of preparing a substrate having a plurality of conductive patterns on an upper surface and having a plurality of lower lands electrically connected to the conductive pattern on a lower surface;
    A first semiconductor die disposed on the substrate to electrically connect with the conductive pattern, and an upper solder ball formed on the substrate to be spaced apart from the first semiconductor die to electrically connect to the conductive pattern Die connecting and forming an upper solder ball;
    A carrier bonding step of bonding the circuit pattern to the upper solder ball by disposing a carrier having a circuit pattern formed on the first semiconductor die;
    An encapsulant forming step of encapsulating the first semiconductor die, the upper solder ball, and the circuit pattern to form an encapsulant between the substrate and the carrier; And
    And removing a carrier to form an upper land on an upper surface of the encapsulant.
  12. The method of claim 11,
    The semiconductor die connection and the upper solder ball forming step
    And electrically connecting the first semiconductor die and the conductive pattern by using a conductive bump formed under the first semiconductor die.
  13. The method of claim 11,
    The carrier bonding step
    And forming the circuit pattern with a conductive material and forming the carrier with a material different from the circuit pattern.
  14. The method of claim 13,
    The carrier removing step is a manufacturing method of the semiconductor package, characterized in that by the etching process.
  15. The method of claim 11,
    And forming a lower solder ball on the lower portion of the substrate to electrically connect the lower solder ball to the lower land.
  16. The method of claim 11,
    The carrier bonding step
    And forming a second semiconductor die on the carrier, the second semiconductor die being electrically connected to the circuit pattern through a conductive wire.
  17. A substrate preparation step of preparing a substrate having a plurality of conductive patterns on an upper surface and having a plurality of lower lands electrically connected to the conductive pattern on a lower surface;
    A semiconductor die attached to an upper portion of the substrate to electrically connect with the conductive pattern, and an upper solder ball formed on the substrate to be spaced apart from the first semiconductor die to electrically connect with the conductive pattern Connecting and forming an upper solder ball;
    An encapsulant forming step of encapsulating the first semiconductor die and the upper solder ball to form an encapsulant on the substrate;
    Forming a through hole in an area of the encapsulant corresponding to the upper solder ball to expose the solder ball to the outside;
    Forming a TMV (Through Mold Via) electrically connected to the upper solder ball by applying a conductive material to the inside of the through hole;
    A carrier bonding step of bonding the circuit pattern to the TMV by disposing a carrier on which a circuit pattern is formed on the first semiconductor die; And
    And removing a carrier to form an upper land on an upper surface of the encapsulant.
  18. The method of claim 11,
    The semiconductor die connection and the upper solder ball forming step
    And attaching the first semiconductor die to the upper portion of the substrate using an adhesive member, and electrically connecting the first semiconductor die to the conductive pattern using conductive wires.
  19. The method of claim 18,
    The semiconductor die connection and the upper solder ball forming step
    And attaching a second semiconductor die to the upper portion of the first semiconductor die by using an adhesive member, and electrically connecting the second semiconductor die to the conductive pattern using a conductive wire.
  20. The method of claim 17,
    The carrier bonding step
    And forming the circuit pattern with a conductive material and forming the carrier with a material different from the circuit pattern.
  21. The method of claim 20,
    The carrier removing step is a manufacturing method of the semiconductor package, characterized in that by the etching process.
  22. The method of claim 17,
    And forming a lower solder ball on the lower portion of the substrate to electrically connect the lower solder ball to the lower land.
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