KR20080020069A - Semiconductor package and method for fabricating the same - Google Patents

Semiconductor package and method for fabricating the same Download PDF

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KR20080020069A
KR20080020069A KR1020060082924A KR20060082924A KR20080020069A KR 20080020069 A KR20080020069 A KR 20080020069A KR 1020060082924 A KR1020060082924 A KR 1020060082924A KR 20060082924 A KR20060082924 A KR 20060082924A KR 20080020069 A KR20080020069 A KR 20080020069A
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semiconductor
semiconductor package
package
substrate
formed
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KR1020060082924A
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Korean (ko)
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김영룡
염근대
최영신
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삼성전자주식회사
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Abstract

A semiconductor package and a method of manufacturing the same are provided to reduce a stacked height and to improve a component yield by reducing a size of a solder ball in a POP(Package On Package) structure. A semiconductor chip group includes one or more semiconductor chips(150) which are laminated on a substrate(110). An attaching layer(155) is formed to attach the substrate and the lowest semiconductor chip of the semiconductor chip group with each other and to attach the semiconductor chips of the semiconductor chip group with each other by using a die-attaching manner. A bonding wire(170) is formed to connect electrically each of the semiconductor chips of the semiconductor chip group with a first electrode pad(131) formed on an upper surface of the substrate. A sealing part(160) is formed on the bonding wire, the semiconductor chip, and the substrate. A conductive column(180) is connected to a second electrode pad(132) to be extended to an upper surface of the sealing part.

Description

반도체 패키지 및 그 제조방법{Semiconductor package and Method for fabricating the same} A semiconductor package and its manufacturing method {Semiconductor package and Method for fabricating the same}

도 1은 종래의 POP 구조를 도시한 단면도이고; Figure 1 illustrates a conventional POP structure, a cross-sectional view;

도 2는 본 발명의 일 실시예에 따른 반도체 패키지의 단면도이고; 2 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention;

도 3은 본 발명의 다른 실시예에 따른 반도체 패키지의 단면도이고; Figure 3 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention;

도 4 내지 도 6은 또 다른 실시예에 따른 반도체 패키지의 단면도이고; 4 to 6 is a cross-sectional view of a semiconductor package according to another embodiment; 그리고 And

도 7a 내지 도 7d는 본 발명의 일 실시예에 따른 반도체 패키지의 제조방법을 나타낸 단면도들이다. Figures 7a-7d are sectional views showing a manufacturing method of a semiconductor package according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명> <Description of the Related Art>

110 : 기판 131 : 제1전극패드 110: substrate 131: first electrode pad

132 : 제2전극패드 133 : 제3전극패드 132: second electrode pad 115. The third electrode pad

190,290 : 솔더볼 170 : 본딩와이어 190290: solder balls, 170: bonding wire

180 : 도전성 컬럼 180: conductive column

본 발명은 반도체 패키지와 그 제조방법에 관한 것으로서, 더욱 상세하게는 POP(Package On Package)구조의 배선연결에 관한 반도체 패키지와 그 제조방법에 관한 것이다. The present invention relates to a semiconductor package and a manufacturing process related to, and more particularly, to a wiring connection structure (Package On Package) POP relates to a semiconductor package and a manufacturing method thereof.

현재의 전자 산업은 핸드폰, PDA의 등장과 함께 빠른 속도로 발전하고 있다. Current electronics industry has developed rapidly with mobile phones, the emergence of a PDA. 이에 따라 반도체 패키지 기술도 점점 고용량, 박형화, 소형화에 대한 요구가 높아지고 이에 대응하는 다양한 솔루션이 등장하고 있다. Accordingly, the semiconductor package technology is increasingly growing demand for high-capacity, thinning, miniaturization appeared wide range of solutions that respond. 이러한 반도체 패키지 기술중에서 고용량을 위한 칩 스택 패키지(Chip Stack Package)는 낮은 구성요소 수율(Component Yield), 본딩와이어 길이의 제한등으로 인하여 단가(cost)가 비싸고 손실(loss)이 크다. Chip stack package for a high capacity of these semiconductor packaging technology (Chip Stack Package) is large this is expensive and the loss (loss) low yield component (Component Yield), bonding due to restrictions such as cost (cost) of the wire length.

이러한 문제점에 대응하여 POP(Package On Package)의 형태를 가지는 솔루션이 등장하였다. This solution has the form of a POP (Package On Package) has emerged in response to these problems. 즉 반도체 패키지 위에 다른 반도체 패키지를 적층하는 구조이다. That is, the structure of laminating the other semiconductor packages on a semiconductor package. 하지만 반도체 패키지를 적층하는 경우 기판의 휨(warpage)현상에 의하여 솔더볼의 접촉불량(non-wet)현상이 많으며 전체 패키지의 높이는 줄이면서 세밀한 피치를 요구(Fine Pitch & Solder Ball Size Needs)하는 고용량, 소형화의 전자매체에는 공정상의 어려움이 있다. However, often the bending (warpage) developing a contact failure (non-wet) phenomenon of solder balls by the substrate when the stacked semiconductor packages require reducing fine pitch height of the whole package (Fine Pitch & Solder Ball Size Needs) high capacity for, electronic media for miniaturization, there are difficulties in the process.

도 1은 종래의 POP 구조를 도시한 단면도이다. 1 is a cross-sectional view showing the conventional POP structure.

도 1을 참조하면, 상부의 반도체 패키지(20)와 하부의 반도체 패키지(10)는 솔더볼(29)에 의하여 연결된다. 1, the semiconductor package 10 of the semiconductor package 20 of the upper and lower portions are connected by a solder ball (29). 적층 결합 높이(H)는 하부의 반도체 패키지(10)의 몰드(mold, 16) 높이와 기판(21, 11)의 휨(warpage)현상을 고려하여 설계된다. Layered combined height (H) is designed for the bending (warpage) of the developing mold (mold, 16) height and the substrate (21, 11) of the lower semiconductor package 10. 상부의 반도체 패키지(20)를 참조하면, 솔더볼(29)은 기판(21)의 하면에 형성되어 있 는 전극패드(23)에 연결되어 형성된다. Referring to the semiconductor package 20 of the upper portion, a solder ball 29 is formed is connected to the electrode pad 23 can be formed on the lower surface of the substrate 21. 고밀도의 반도체 패키지에서는 이러한 전극패드(23)의 피치(pitch)는 좁아지게 되는데 이에 따라 솔더볼(29)의 크기도 작아져야 하므로 결국 적층 결합 높이(H)는 낮아져야 한다. Pitch (pitch) is there is narrowed Accordingly size after all lamination bonding height (H), so also must be small to the solder balls 29 of the semiconductor package of the high density of these electrode pads 23 are to be lowered. 그런데 적층 결합 높이(H)는 하부의 반도체 패키지(10)의 몰드(mold, 16) 높이와 기판(21, 11)의 휨(warpage)현상을 고려하여 설계되므로 서로 상충되는 문제점이 발생한다. However, lamination bonding height (H) is so designed in consideration of the bending (warpage) of the developing mold (mold, 16) height and the substrate (21, 11) of the lower semiconductor package 10 arises a problem in that conflict with each other.

본 발명이 이루고자 하는 기술적 과제는 POP 구조에서 적층 결합 높이를 줄일 수 있는 반도체 패키지의 제조 방법을 제공하는 데 있다. The present invention also provides a method for manufacturing a semiconductor package that can reduce the laminate bond above the POP structure.

본 발명이 이루고자 하는 다른 기술적 과제는 상기와 같은 본 발명의 제조방법에 의해 구현된 반도체 패키지를 제공하는 데 있다. The present invention is to provide a semiconductor package implemented by the production method of the present invention as described above.

상기 기술적 과제를 달성하기 위한 본 발명의 반도체 패키지 제조 방법에서는 기판 및 하나 이상의 반도체칩을 준비하는 단계; In the manufacturing method a semiconductor package of the present invention for achieving the above aspect the method comprising: preparing a substrate and at least one semiconductor chip; 상기 기판 상에 접착층을 형성하는 단계; Forming an adhesive layer on the substrate; 상기 접착층상에 하나 이상의 상기 반도체칩을 순차적으로 적층하여 상기 반도체칩을 상기 기판상에 다이 어태치 하는 단계; The step of die attach of the semiconductor chip by sequentially stacking at least one semiconductor chip on the adhesive layer on the substrate; 상기 기판과 상기 반도체칩이 전기적으로 연결되도록 본딩와이어를 사용하여 상기 기판의 상면에 형성되는 제1전극패드와 상기 반도체칩을 와이어 본딩하는 단계; Wherein the substrate and the semiconductor chip is electrically connected to the first electrode pad and the semiconductor chip is formed on the upper surface of the substrate, wire bonding using bonding wires to; 상기 기판의 상면에 형성되는 제2전극패드에 연결되어 상향 신장되는 도전성 컬럼(column)을 형성하는 단계; Forming a conductive column (column) that is up-height is connected to the second electrode pad formed on the upper surface of the substrate; 및 상기 도전성 칼럼, 상기 본딩와이어 및 상기 반도체칩을 보호하기 위하여 상기 기판 상에 봉지부를 형성하는 단계를 포함한다. And a step of forming a bag on the substrate to protect the conductive columns, the bonding wires and the semiconductor chip.

상기 다른 기술적 과제를 달성하기 위한 본 발명의 반도체 패키지는 기판; The semiconductor package of the present invention for achieving the aforementioned another aspect of the substrate; 상기 기판 상에 순차적으로 적층되는 하나 이상의 반도체칩으로 이루어진 반도체칩군; Chipgun semiconductor of one or more semiconductor chips to be sequentially stacked on the substrate; 상기 기판과 상기 반도체칩군의 최하단 반도체칩 및 상기 반도체칩군의 반도체칩 각각을 다이 어태치(die attach)하는 접착층; Adhesion to the substrate and the semiconductor chipgun lowermost semiconductor chip and a semiconductor chip, each of the semiconductor chipgun die attach (die attach); 상기 반도체칩군의 반도체칩 각각을 상기 기판의 상면에 형성되는 제1전극패드에 전기적으로 연결하는 본딩와이어; Bonding wires for electrically connecting the respective semiconductor chips of the semiconductor chipgun to the first electrode pad formed on the upper surface of the substrate; 상기 본딩와이어, 상기 반도체칩 및 상기 기판 상에 형성된 봉지부; The bonding wire seal portion formed on the semiconductor chip and the substrate; 및 상기 기판의 상면에 형성되는 제2전극패드에 연결되어 상기 봉지부 상면으로 신장되는 도전성 컬럼(column);을 포함할 수 있다. May comprise; and is connected to the second electrode pad formed on the upper surface of the substrate, the conductive columns (column) extending in the upper surface of the seal portion.

상기 반도체 패키지에 있어서, 상기 기판의 상면과 대향되는 하면에 형성되는 제3전극패드에 전기적으로 연결되는 솔더볼; In the semiconductor package, the solder balls electrically coupled to the third electrode pad formed on the bottom is the top surface and an opposite of the substrate; 및 상기 반도체패키지 상에 적층되는 또 다른 상기 반도체패키지를 더 포함하고, 상부 반도체패키지의 상기 솔더볼과 서로 대응하는 하부 반도체패키지의 상기 도전성 컬럼 각각이 전기적 및 기계적으로 연결될 수 있다. And there is another and further comprising a semiconductor package, may be connected to the electrically and mechanically the conductive columns of each of the lower semiconductor package corresponding to each other with the solder balls of the upper semiconductor package is stacked on the semiconductor package.

상기 반도체 패키지에 있어서, 상기 반도체패키지 상에 적층되는 웨이퍼 레벨 패키지(wafer level package)를 더 포함하고, 상기 웨이퍼 레벨 패키지의 전극패드와 상기 반도체패키지의 상기 도전성 컬럼 각각이 서로 대응하여 전기적으로 연결되고, 상기 웨이퍼 레벨 패키지와 상기 반도체패키지 사이에는 비전도성의 접착층이 형성될 수 있다. In the semiconductor package, the semiconductor package onto the wafer-level package to be laminated to include a (wafer level package) more, and wherein the conductive columns and each of the electrode pads and the semiconductor package of the wafer-level package and electrically connected to corresponding another , there may be a non-conductive adhesive layer is formed between the wafer-level package and the semiconductor package.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. With reference to the accompanying drawings will be described a preferred embodiment of the present invention; 그러나, 본 발명은 여기서 설명되어지는 실시예들에 한정되지 않고 다 른 형태로 구체화될 수도 있다. However, the present invention may be embodied in different forms and should not be limited to the embodiments set forth herein. 오히려, 여기서 소개되는 실시예들은 개시된 내용이 철저하고 완전해질 수 있도록 그리고 당업자에게 본 발명의 사상이 충분히 전달될 수 있도록 하기 위해 제공되어지는 것이다. Rather, the embodiments are described here examples are being provided to make this disclosure to be thorough and is transmitted to be complete, and fully the scope of the present invention to those skilled in the art. 도면들에 있어서, 층 및 영역들의 두께는 명확성을 기하여 위하여 과장되어진 것이다. In the figures, the dimensions of layers and regions are exaggerated for clarity gihayeo. 명세서 전체에 걸쳐서 동일한 참조번호들은 동일한 구성요소들을 나타낸다. The same reference numerals throughout the specification denote like elements. 명세서 전체에 걸쳐서 막, 영역, 또는 기판등과 같은 하나의 구성요소가 또 다른 구성요소 "상에" 위치한다고 언급할 때는, 상기 하나의 구성요소가 다른 구성요소에 직접 접촉하거나 중간에 개재되는 구성요소들이 존재할 수 있다고 해석될 수 있다. When referring to said film, region, or one component and another component, such as a substrate, such as "on" position, throughout the specification, the configuration in which the one component is directly in contact with the other component or intervening It can be interpreted that the elements may be present.

또한, "하부의(lower)" 또는 "하단(bottom)" 및 "상부의(upper)" 또는 "상단(top)"과 같은 상대적인 용어들은 도면들에서 도해되는 것처럼 다른 요소들에 대한 어떤 요소들의 관계를 기술하기 위해 여기에서 사용될 수 있다. In addition, of certain elements of the "lower portion of the (lower)" or the "lower (bottom)" and the "upper portion of the (upper)" or "upper (top)", and other elements as is illustrated in relative terms are the same diagram as It can be used here to describe the relationship. 상대적 용어들은 도면들에서 묘사되는 방향에 추가하여 소자의 다른 방향들을 포함하는 것을 의도한다고 이해될 수 있다. Relative terms are to be understood to add to the direction depicted in the figures and intended to include other directions of the device. 예를 들어, 도면들에서 소자가 뒤집어 진다면(turned over), 다른 요소들의 "상부의" 면 상에 존재하는 것으로 묘사되는 요소들은 상기 다른 요소들의 "하부의" 면 상에 방향을 가지게 된다. For example, if the device in the figures jindamyeon inverted (turned over), elements described as being present on the "upper" side of other elements are to have a direction on "the lower" face of the other element. 그러므로 예로써 든 "상부의"라는 용어는, 도면의 특정한 방향에 의존하여, "하부의" 및 "상부의" 방향 모두를 포함할 수 있다. Therefore, all terms "upper", for example is, depending on the particular direction in the drawing, may include both "on the bottom" and "upper" direction. 유사하게, 도면들의 하나에서 소자가 뒤집어 진다면, 다른 요소들의 "아래의(below or beneath)"라고 묘사되어 있는 요소들은 상기 다른 요소들의 "위의(above)" 방향을 가지게 된다. Similarly, the flip element jindamyeon in one of the figures, of the other elements "below (below or beneath)" elements that are described as they are have a "above (above)" direction of the other element. 그러므로 예로써 든 "상의"라는 용어는, 위 및 아래의 방향 모두를 포함할 수 있다. Therefore, all the term "on" is by way of example, it may include both directions of up and down.

제1 실시예 First Embodiment

도 2는 본 발명의 일 실시예에 따른 반도체 패키지의 단면도이다. Figure 2 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

도 2를 참조하면, 기판(110)의 상면에는 도전성의 제1전극패드(131), 제2전극패드(132) 및 비도전성의 포토 솔더 레지스트(120)가 형성된다. 2, the upper surface of the substrate 110 is formed with a first electrode pad 131, a second electrode pad 132 and the non-photo solder resist (120) of the electrically conductive malleable. 기판(110)은 인쇄회로기판(PCB), 테이프, 리드프레임(Lead Frame) 또는 웨이퍼 형태일 수 있으며 반도체 패키지의 기술분야의 당업자들이 통상적으로 사용하고 변형 가능한 모든 종류의 기판을 포함한다. The substrate 110 includes a printed circuit board (PCB), a tape, a lead frame (Lead Frame) or wafer form, and can be any type of the substrate those skilled in the art of semiconductor packages are available and commonly used in transformation. 반도체칩(150)은 하나 이상의 반도체칩으로 이루어진 반도체칩군으로 형성될 수 있다. The semiconductor die 150 may be formed of a semiconductor chipgun of one or more semiconductor chips. 기판(110) 상에 상기 반도체칩군의 최하단 반도체칩이 접착층(155)에 의해 다이 어태치(die attach)된다. The bottom semiconductor die of the semiconductor chipgun is die attach (die attach) by an adhesive layer 155 on the substrate 110. The 또한 반도체칩군의 반도체칩 각각이 접착층(155)에 의해 다이 어태치(die attach)된다. In addition, each of the semiconductor chipgun semiconductor chip is die-attach (die attach) by the adhesive layer 155. 상기 반도체칩군의 반도체칩(150) 각각을 기판(110)의 상면에 형성되는 제1전극패드(131)에 전기적으로 연결하는 본딩와이어(170)가 형성된다. The bonding wires 170 for electrically connecting the first electrode pad 131 is formed a semiconductor chip 150, each of the semiconductor chipgun on the upper surface of the substrate 110 is formed. 본딩 와이어(170), 반도체칩(150)을 보호하기 위하여 기판(110) 상에 봉지부(160)가 형성된다. Bonding wires 170, and the seal portion 160 on the substrate 110 is formed to protect the semiconductor chip 150. 봉지부(160)는 바람직하게는 에폭시 몰드 수지(Epoxy Mold Compound, EMC)일 수 있다. Encapsulation section 160 may preferably be an epoxy mold resin (Epoxy Mold Compound, EMC). 한편, 기판(110)의 상면에 형성되는 제2전극패드(132)에 연결되어 봉지부(160) 상면으로 신장되는 도전성 컬럼(column)(180)이 형성된다. On the other hand, is connected to the second electrode pad 132 is formed on the upper surface of the substrate 110 is formed with a conductive column (column) (180) extending in a top surface seal portion 160. 도전성 컬럼(180)은 본딩와이어(170)를 사용하여 형성될 수 있는데 재질이 금, 구리 또는 알루미늄일 수 있으며 강도가 높은 것이 바람직하다. Conductive columns 180 may be formed using the bonding wire 170 can be a material of gold, copper or aluminum, preferably has a high strength. 도전성 컬럼(180)은 봉지부(160)의 상면에서 돌출될 수 있는데 이것은 다른 반도체 패키지를 적층할 경우 도전성 컬럼(180)의 돌출된 부분을 가열하여 리플로우(reflow)하기 위함이다. A conductive column 180 may be protruded from the upper surface of the seal portion 160. This is the case for stacking other semiconductor packages by heating the protruding portion of the conductive columns 180, in order to reflow (reflow).

제2 실시예 Second Embodiment

도 3은 본 발명의 다른 실시예에 따른 반도체 패키지의 단면도이다. 3 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

도 3을 참조하면, 도 2에서 설명한 본 발명의 일실시예에 따른 반도체 패키지(100)가 하부에 위치하고 상부에는 또 다른 반도체 패키지(200)가 위치한다. Referring to Figure 3, also located in one embodiment the semiconductor package 100 according to the lower of the invention described in the second and another semiconductor package 200, the upper position. 상부의 반도체 패키지(200)는 하부의 반도체 패키지(100)와 동일할 수 있으나 적층구조에 따라서는 도전성 컬럼(180)이 없을 수 있다. The upper semiconductor package 200 may be the same as the semiconductor package 100 of the bottom, but may not have a conductive column 180 according to the stack structure. 상부의 반도체 패키지(200)에서 기판(210)의 상면과 대향되는 하면에 위치하는 제3전극패드(233)에 전기적으로 연결되는 솔더볼(290)이 형성된다. The solder ball electrically coupled to the third electrode pad 233 is located on the upper surface and the counter when that of the substrate 210 in the semiconductor package 200 of the upper 290 is formed. 상부 반도체 패키지(200)의 솔더볼(290)과 서로 대응하는 하부 반도체 패키지(100)의 도전성 컬럼(180) 각각이 전기적 및 기계적으로 연결된다. It is electrically and mechanically connected to a conductive column 180, each solder ball 290 and the lower semiconductor package 100 corresponding to each other in the upper semiconductor package 200. 상부의 반도체 패키지(200)의 솔더볼(290)은 도전성 컬럼(180)의 존재로 인하여 하부의 반도체 패키지의 기판(110)까지 신장될 필요가 없으므로 솔더볼(290)의 크기가 작아질 수 있다. Solder ball 290 of the upper semiconductor package 200 has the size of a conductive column 180 due to the presence does not need to be extended to the substrate 110 of the lower semiconductor package of the solder ball 290 can be made small. 따라서 좁은 피치를 가지는 솔더볼 구조를 가질 수 있는 이점이 있다. Therefore, there is an advantage that the solder balls may have a structure having a narrow pitch.

제3 실시예 Third Embodiment

도 4는 본 발명의 또 다른 실시예에 따른 반도체 패키지의 단면도이다. Figure 4 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

도 4를 참조하면, 도 2에서 설명한 본 발명의 일실시예에 따른 반도체 패키지(100)가 하부에 위치하고 상부에는 웨이퍼 레벨 패키지(wafer level package, 300)가 위치한다. 4, also located in one embodiment the lower semiconductor package 100 according to the embodiment of the present invention described in the second to the upper part of the wafer-level package (wafer level package, 300) position.

우선 웨이퍼 레벨 패키지에 대해서 설명한다. First, a description will be given of a wafer-level package. 칩 스케일 패키지가 크기 면에서 절대적인 이점을 가지고 있는 반면 아직까지는 여러모로 단점들을 안고 있는 것 도 사실이며, 그 중의 하나는 신뢰성의 확보가 어렵다는 점이며, 다른 하나는 칩 스케일 패키지의 제조에 추가로 투입되는 제조 설비 및 소요되는 원부자재가 많고 제조 단가가 높아 가격 경쟁력이 떨어진다는 점이다. While the chip scale package has an absolute advantage in size will still hold them in many ways drawback until is also true, one of which is the fact that the reliability is hard, the other is being introduced in addition to the production of a chip scale package the raw materials and manufacturing equipment that takes less price-competitive manufacturing cost is increased many points. 즉, 통상적인 웨이퍼 제조 공정을 통하여 반도체 웨이퍼(semiconductor wafer)가 제조되면 웨이퍼로부터 개별 칩을 분리하여 패키지 조립 공정을 거치게 된다. In other words, when through the conventional wafer manufacturing process, a semiconductor wafer (semiconductor wafer) is manufactured by separating individual chips from the wafer subjected to the package assembly process. 패키지 조립 공정은 웨이퍼 제조 공정과는 다른 설비와 원부자재를 필요로 하는 전혀 별개의 공정이지만, 웨이퍼 레벨에서, 즉 웨이퍼로부터 개별 칩을 분리하지 않은 상태에서 완전한 제품으로서의 패키지를 제조할 수 있다. Package assembly process may be prepared as a package complete product in a state in all but a separate process, the wafer level, which require different equipment and raw materials and the wafer production process, that is without removing the individual chips from the wafer. 그리고 패키지를 제조하는데 사용되는 제조 설비나 제조 공정에 기존 웨이퍼 제조설비, 공정들을 그대로 이용할 수 있다. And in the production equipment and manufacturing process used to manufacture the package as it can take advantage of existing wafer fabrication facility, process. 이는 패키지를 제조하기 위하여 추가로 소요되는 원부자재를 최소활 수 있음을 의미하기도 한다. This also means that the minimum number of active raw materials required to manufacture an additional package.

도 4를 참조하면, 웨이퍼 레벨 패키지(300)의 전극패드(미도시)와 하부의 반도체 패키지(100)의 도전성 컬럼(180)이 서로 대응하여 전기적으로 연결된다. 4, the wafer-level conductive column 180 of the package, electrode pads (not shown) and the lower semiconductor package 100 of the 300 by corresponding to each other are electrically connected. 예를 들어 도전성 컬럼(180)이 구리의 재질일 경우 웨이퍼 레벨 패키지(300)의 전극패드(미도시)도 구리인 것이 바람직하며 동일재질의 금속이 접합하여 금속 결합(bonding)이 이루어진다. For example, a conductive column 180 (not shown), the electrode pads of the wafer-level package 300 when the copper material and copper is also preferred that the metal bond is made (bonding) by the metal of the same material as the bonding. 또한 웨이퍼 레벨 패키지(300)와 하부의 반도체 패키지(100) 사이에는 비전도성의 접착층(355)이 형성된다. In addition, the adhesive layer 355 of non-conducting is formed between the wafer-level package 300 and the lower portion of the semiconductor package 100. 비전도성의 접착층(355)은 필름(film) 또는 페이스트(paste) 형태일 수 있다. The adhesive layer 355 of non-conductive can be a film (film) or a paste (paste) form.

제4 실시예 Fourth Embodiment

도 5는 본 발명의 또 다른 실시예에 따른 반도체 패키지의 단면도이다. 5 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

도 5를 참조하면, 도 2에서 설명한 본 발명의 일실시예에 따른 반도체 패키 지(100)가 하부에 위치하고 상부에는 웨이퍼 레벨 패키지(wafer level package, 400)가 위치한다. 5, also located in an exemplary semiconductor package 100 is lower according to the embodiment of the present invention will be described in the second upper portion of the chip scale package (wafer level package, 400) position. 웨이퍼 레벨 패키지(400)의 솔더범프(495)와 하부의 반도체 패키지(100)의 도전성 컬럼(180) 각각이 서로 대응하여 접촉함으로써 전기적으로 연결된다. The conductive columns 180, each wafer level package 400, the solder bumps 495 and the lower semiconductor package 100 are electrically connected by the contact with each other correspondingly. 또한 웨이퍼 레벨 패키지(400)와 하부의 반도체 패키지(100) 사이에는 비전도성의 봉지재(460)가 형성된다. In addition, between the wafer-level package 400 and the lower portion of the semiconductor package 100 is formed with a sealing material 460 of the non-conductive. 봉지재(460)는 바람직하게는 폴리머, 에폭시 수지 등으로 형성될 수 있다. Encapsulant 460 is preferably as may be formed of a polymer, epoxy resin or the like. 봉지재(460)는 솔더범프(495) 및 웨이퍼(450)를 보호하면서 동시에 웨이퍼 레벨 패키지(400)와 하부의 반도체 패키지(100)의 접착에 기여한다. Encapsulation material 460 and contributes to the bonding of the solder bumps 495 and the wafer while protecting the 450 at the same time, the wafer-level package 400 and the lower semiconductor package 100 of.

제5 실시예 The fifth embodiment

도 6은 본 발명의 또 다른 실시예에 따른 반도체 패키지의 단면도이다. Figure 6 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

도 6을 참조하면, 도 2에서 설명한 본 발명의 일실시예에 따른 반도체 패키지(100)가 하부에 위치하고 상부에는 플립칩 패키지(flip chip package, 600)이 위치한다. 6, also located in one embodiment the lower semiconductor package 100 according to the embodiment of the present invention will be described in the second upper portion of the flip chip package (flip chip package, 600) is located.

우선 플립칩 패키지에 대해서 설명한다. First, a description will be given of the flip chip package. 반도체 패키지는 반도체칩의 전극패드를 외부로 연결하는 방식에 따라 와이어본딩 (wire bonding) 방식과 플립칩 본딩(flip-chip bonding)방식으로 구분할 수 있다. Semiconductor packages can be classified into according to how to connect the electrode pads of the semiconductor chip to the external wire bonding (wire bonding) method and flip chip bonding (flip-chip bonding) method. 와이어본딩 방식은 반도체칩에 마련되어 있는 전극패드와 리이드프레임의 리이드를 전도성 와이어로 연결하는 방식이다. The wire bonding method is a method for connecting the leads of the lead frame and an electrode pad provided on the semiconductor chip to the conductive wire. 이에 비해 플립칩 본딩방식은 반도체칩의 전극패드에 전도성범프를 형성하고 이를 접속대상 부위에 직접 접합하는 방식이다. In comparison, the flip-chip bonding method is a method of forming a conductive bump on an electrode pad of the semiconductor chip, and binding them directly to the connected target site. 이러한 플립칩 본딩방식은 전기적인 연결거리가 짧아 우수한 열적 전기적 특성을 가짐은 물론 패키지의 집적도를 증 가시킬 수 있어 우수한 전기적 특성을 요구하는 슈퍼컴퓨터나 여러 무선통신 장비 등에 광범위하게 적용되고 있다. The flip-chip bonding method has been widely applied to electrical connection distance is shorter excellent thermal super computer or various wireless communication, as well as the degree of integration of the packages has an electrical property requirements increase excellent electrical characteristics can kill visible equipment.

도 6을 참조하면, 플립칩 패키지(600)의 전극패드(633)와 하부의 반도체 패키지(100)의 도전성 컬럼(180)이 전기적으로 연결된다. 6, the conductive columns 180 of the flip-chip package 600, the electrode pad 633 and the lower semiconductor package 100 of the two are electrically connected.

제6 실시예 Sixth Embodiment

도 7a 내지 도 7d는 본 발명의 일 실시예에 따른 반도체 패키지의 제조방법을 나타낸 단면도들이다. Figures 7a-7d are sectional views showing a manufacturing method of a semiconductor package according to an embodiment of the present invention.

도 7a를 참조하면, 기판(110) 및 하나 이상의 반도체칩(150)이 제공된다. Referring to Figure 7a, a substrate 110, and is provided with at least one semiconductor chip (150). 기판(110)의 표면에는 포토 솔더 레지스트(120)이 코팅될 수 있다. The surface of the substrate 110 has a photo solder resist 120 may be coated. 기판(110) 상에 접착층(155)를 형성한 후 하나 이상의 반도체칩(150)을 순차적으로 적층하여 다이어태치(die attach)한다. After forming the adhesive layer 155 on the substrate 110 by sequentially stacking at least one semiconductor chip 150 to attach diaphragm (die attach). 이후 기판(110)과 반도체칩(150)이 전기적으로 연결되도록 본딩와이어(170)를 사용하여 기판(110)의 상면에 형성되는 제1전극패드(131)와 반도체칩(150)을 와이어 본딩한다. The substrate 110 and the semiconductor chip 150 is electrically connected to the bonding wires to the first electrode pad 131 and the semiconductor chip 150 formed on the upper surface of the substrate 110 using a bonding wire 170 to the .

계속하여 도 7b를 참조하면, 기판(110)의 상면에 형성되는 제2전극패드에 연결되어 상향 신장되는 도전성 컬럼(180)을 형성한다. Subsequently Referring to Figure 7b, to form a conductive column 180 is connected to the second electrode pad formed on an upper surface upwardly height of the substrate 110. 도전성 컬럼(180)은 본딩와이어(170)를 사용하며 재질은 금, 구리 또는 알루미늄인 것이 바람직하다. Conductive columns 180 using bonding wires 170, and the material is preferably silver, gold, copper or aluminum. 즉, 와이어본딩을 하는 단계에서 본딩와이어를 사용하여 도전성 컬럼(180)을 형성할 수 있다. That is, by using the bonding wire in the step of wire bonding can form an electrically conductive column 180. 도전성 컬럼(180)이 넘어지지 않고 고강도를 유지하기 위하여 일정한 직경 이상이 필요하다. Conductive columns 180 is not falling down is a constant diameter or higher is required in order to maintain a high strength.

계속하여 도 7c를 참조하면, 도전성 컬럼(180)이 형성된 반도체 패키 지(100b)를 뒤집어 상부가압기(710)와 하부가압기(720)사이에 넣어 봉지재를 형성한다. Subsequently Referring to Figure 7c, a reverse column conductive semiconductor package 180 is formed (100b) placed in between the upper press machine 710 and the lower pusher 720 to form the encapsulant. 예를 들어 에폭시 몰드 수지(760)가 액상으로 존재하는 하부가압기(720) 내에 반도체 패키지(100b)를 넣고 가압하여 본딩와이어(170), 도전성 컬럼(180)을 보호할수 있는 봉지재를 기판(110) 상에 형성한다. For example, an epoxy mold resin 760 is to put the semiconductor package (100b) the pressure in the lower pusher 720 is present in the liquid bonding wire 170, a conductive column 180 to be the sealing material substrate (110 in protected ) is formed on the.

계속하여 도 7d를 참조하면, 봉지부(160)까지 형성된 반도체 패키지(100) 상에 또 다른 반도체 패키지(200)를 적층한다. Continuing with reference to Figure 7d, The seal portion 160 is laminated to another semiconductor package 200 on the semiconductor package 100 formed thus. 기판(210)의 하면에 형성되는 제3전극패드(233)에 전기적으로 연결되는 솔더볼(290)을 형성할 수 있다. A solder ball 290 is electrically connected to the third electrode pad 233 is formed on the lower surface of the substrate 210 can be formed. 상부 반도체 패키지(200)의 솔더볼(290)과 서로 대응하는 하부 반도체 패키지(100)의 도전성 컬럼(180) 각각을 가열하여 리플로우(Reflow)시켜 전기적 및 기계적으로 연결한다. Heating the conductive columns 180, each solder ball 290 and the lower semiconductor package 100 corresponding to each other in the upper semiconductor package 200 is reflowed (Reflow) and connected electrically and mechanically. 이로써 반도체 패키지의 제조 공정이 종료된다. Thus the manufacturing process of the semiconductor package is completed.

발명의 특정 실시예들에 대한 이상의 설명은 예시 및 설명을 목적으로 제공되었다. The foregoing description of the specific embodiments of the invention has been presented for purposes of illustration and description. 따라서, 본 발명은 상기 실시예들에 한정되지 않으며, 본 발명의 기술적 사상 내에서 해당 분야에서 통상의 지식을 가진 자에 의하여 상기 실시예들을 조합하여 실시하는 등 여러 가지 많은 수정 및 변경이 가능함은 명백하다. Accordingly, the invention is not limited to the above embodiments, a number of many modifications and variations are possible, such as by those of ordinary skill in the art within the spirit of the present invention carried out by combining the above-described embodiment is it is obvious.

본 발명에 의한 반도체 패키지 및 그 제조방법에 따르면, 도전성 컬럼이 기판에서 상향 신장되어 형성되므로 POP구조에서 솔더볼의 크기를 작게 하여 적층 결합 높이를 낮출 수 있고 구성성분의 수율(Component Yield)을 개선할 수 있다. According to a semiconductor package and a manufacturing method of the present invention, the conductive columns are formed is raised height from the substrate to reduce the size of the solder ball from the POP structure can lower the stacking bonding height, and to improve the yield of (Component Yield) of constituents can.

Claims (13)

  1. 기판; Board;
    상기 기판 상에 순차적으로 적층되는 하나 이상의 반도체칩으로 이루어진 반도체칩군; Chipgun semiconductor of one or more semiconductor chips to be sequentially stacked on the substrate;
    상기 기판과 상기 반도체칩군의 최하단 반도체칩 및 상기 반도체칩군의 반도체칩 각각을 다이 어태치(die attach)하는 접착층; Adhesion to the substrate and the semiconductor chipgun lowermost semiconductor chip and a semiconductor chip, each of the semiconductor chipgun die attach (die attach);
    상기 반도체칩군의 반도체칩 각각을 상기 기판의 상면에 형성되는 제1전극패드와 전기적으로 연결하는 본딩와이어; Bonding wires for electrically connecting the first electrode pad is formed for each semiconductor chip, the semiconductor chipgun on the upper surface of the substrate;
    상기 본딩와이어, 상기 반도체칩 및 상기 기판 상에 형성된 봉지부; The bonding wire seal portion formed on the semiconductor chip and the substrate; And
    상기 기판의 상면에 형성되는 제2전극패드에 연결되어 상기 봉지부 상면으로 신장되는 도전성 컬럼(column);을 포함하는 것을 특징으로 하는 반도체패키지. A semiconductor package comprising a; is connected to the second electrode pad formed on the upper surface of the substrate, the conductive columns (column) extending in the upper surface of the seal portion.
  2. 제1항에 있어서, According to claim 1,
    상기 기판의 상면과 대향되는 하면에 형성되는 제3전극패드에 전기적으로 연결되는 솔더볼; A solder ball electrically coupled to the third electrode pad formed on a lower substrate opposite to the upper surface; And
    상기 반도체패키지 상에 적층되는 또 다른 상기 반도체패키지를 더 포함하고, Further comprising another semiconductor package is stacked on the semiconductor package,
    상부의 상기 반도체패키지의 상기 솔더볼과 서로 대응하는 하부의 상기 반도체패키지의 상기 도전성 컬럼 각각이 전기적 및 기계적으로 연결되는 것을 특징으 로 하는 반도체 패키지. It is connected to the electrically and mechanically the conductive columns of each of the solder balls and the bottom of the semiconductor package corresponding to each other of the semiconductor package of the upper semiconductor package characterized by lead.
  3. 제1항에 있어서, According to claim 1,
    상기 반도체패키지 상에 적층되는 웨이퍼 레벨 패키지(wafer level package)를 더 포함하고, Further comprising a wafer level package (wafer level package) that is stacked on the semiconductor package,
    상기 웨이퍼 레벨 패키지의 전극패드와 상기 반도체패키지의 상기 도전성 컬럼 각각이 서로 대응하여 전기적으로 연결되고, Wherein the conductive columns and each of the electrode pads and the semiconductor package of the wafer-level package and electrically connected to each other in correspondence,
    상기 웨이퍼 레벨 패키지와 상기 반도체패키지 사이에는 비전도성의 접착층이 형성되는 것을 특징으로 하는 반도체 패키지. Between the wafer-level package and the semiconductor package, the semiconductor package characterized in that the non-conductive adhesive layer is formed.
  4. 제1항에 있어서, According to claim 1,
    상기 반도체패키지 상에 적층되는 웨이퍼 레벨 패키지(wafer level package)를 더 포함하고, Further comprising a wafer level package (wafer level package) that is stacked on the semiconductor package,
    상기 웨이퍼 레벨 패키지의 솔더범프와 상기 반도체패키지의 상기 도전성 컬럼 각각이 서로 대응하여 전기적으로 연결되고, Wherein the electrically conductive columns, each of the solder bumps and the semiconductor package of the wafer-level package and electrically connected to each other in correspondence,
    상기 웨이퍼 레벨 패키지와 상기 반도체패키지 사이에는 비전도성의 봉지재가 형성되는 것을 특징으로 하는 반도체 패키지. Between the wafer-level package and the semiconductor package, the semiconductor package characterized in that the encapsulation material is formed of non-conductive.
  5. 제1항에 있어서, According to claim 1,
    상기 반도체패키지 상에 적층되는 플립칩(flip chip) 패키지를 더 포함하고, And further comprising a flip-chip (flip chip) packages are stacked on the semiconductor package,
    상기 플립칩 패키지의 전극패드와 상기 반도체패키지의 상기 도전성 컬럼 각각이 서로 대응하여 전기적으로 연결되는 것을 특징으로 하는 반도체 패키지. A semiconductor package, characterized in that the conductive columns of each electrode pad and the semiconductor package of the flip-chip package are electrically connected to each other in correspondence.
  6. 제1항에 있어서, 상기 도전성 컬럼은 상기 본딩와이어를 사용하며 재질은 금, 구리 또는 알루미늄인 것을 특징으로 하는 반도체 패키지. According to claim 1, wherein the conductive columns are used for the bonding wire and the material of the semiconductor package, characterized in that silver, gold, copper or aluminum.
  7. 제1항에 있어서, 상기 기판은 인쇄회로기판(PCB), 테이프, 리드프레임(Lead Frame) 또는 웨이퍼 형태인 것을 특징으로 하는 반도체 패키지. The method of claim 1, wherein the substrate is a printed circuit board (PCB), a tape, a lead frame (Lead Frame) or semiconductor package, characterized in that the wafer form.
  8. 기판 및 하나 이상의 반도체칩을 준비하는 단계; Preparing a substrate and at least one semiconductor chip;
    상기 기판 상에 접착층을 형성하는 단계; Forming an adhesive layer on the substrate;
    상기 접착층상에 하나 이상의 상기 반도체칩을 순차적으로 적층하여 상기 반도체칩을 상기 기판상에 다이 어태치 하는 단계; The step of die attach of the semiconductor chip by sequentially stacking at least one semiconductor chip on the adhesive layer on the substrate;
    상기 기판과 상기 반도체칩이 전기적으로 연결되도록 본딩와이어를 사용하여 상기 기판의 상면에 형성되는 제1전극패드와 상기 반도체칩을 와이어 본딩하는 단계; Wherein the substrate and the semiconductor chip is electrically connected to the first electrode pad and the semiconductor chip is formed on the upper surface of the substrate, wire bonding using bonding wires to;
    상기 기판의 상면에 형성되는 제2전극패드에 연결되어 상향 신장되는 도전성 컬럼(column)을 형성하는 단계; Forming a conductive column (column) that is up-height is connected to the second electrode pad formed on the upper surface of the substrate; And
    상기 도전성 칼럼, 상기 본딩와이어 및 상기 반도체칩을 보호하기 위하여 상기 기판 상에 봉지부를 형성하는 단계;를 포함하는 것을 특징으로 하는 반도체 패 키지의 제조방법. A method for fabricating a semiconductor package comprising the, forming sealing portion on the substrate to protect the conductive columns, the bonding wires and the semiconductor chip.
  9. 제8항에 있어서, 상기 봉지부를 형성하는 단계 이후에, The method of claim 8, wherein after the step of forming the sealing portion,
    상기 기판의 상면과 대향되는 하면에 형성되는 제3전극패드에 전기적으로 연결되는 솔더볼을 형성하는 단계; Forming a solder ball electrically coupled to the third electrode pad formed on a lower substrate opposite to the upper surface;
    상기 반도체 패키지 상에 또 다른 상기 반도체 패키지를 적층하는 단계; Laminating the other semiconductor packages on the semiconductor package; And
    상부의 상기 반도체패키지의 상기 솔더볼과 서로 대응하는 하부의 상기 반도체패키지의 상기 도전성 컬럼 각각을 가열하여 리플로우(Reflow)시켜 전기적 및 기계적으로 연결하는 단계;를 더 포함하는 반도체 패키지의 제조방법. The process for manufacturing a semiconductor package further comprising a; heating the conductive columns of each of the bottom corresponding to each other with the solder balls of the semiconductor package, the semiconductor package of the upper step of reflow (Reflow) connected electrically and mechanically.
  10. 제8항에 있어서, 상기 봉지부를 형성하는 단계 이후에, The method of claim 8, wherein after the step of forming the sealing portion,
    상기 반도체패키지 상에 웨이퍼 레벨 패키지를 적층하는 단계; Laminating the wafer-level package in the semiconductor package; And
    상기 반도체 패키지와 상기 웨이퍼 레벨 패키지를 전기적으로 연결하는 단계;를 더 포함하는 반도체 패키지의 제조방법. The process for manufacturing a semiconductor package further comprising a; step of electrically connecting the semiconductor package and the chip scale package.
  11. 제10항에 있어서, 상기 연결하는 단계는 전해도금, 무전해도금 방식에 의해 형성된 솔더 범프(Sold Bump)에 의한 방법 또는 금속본딩에 의한 방법으로 연결하는 것을 포함하는 반도체 패키지의 제조방법. The method of claim 10, wherein the connection is an electrolytic plating, a method for manufacturing a semiconductor package, comprising electroless plating the solder bump connection method by the method or a metal bonding by (Sold Bump) formed by the gold method.
  12. 제8항에 있어서, 상기 도전성 컬럼은 상기 본딩와이어를 사용하며 재질은 금, 구리 또는 알루미늄인 것을 특징으로 하는 반도체 패키지의 제조방법. 10. The method of claim 8 wherein the conductive column is for manufacturing a semiconductor package, characterized in that the use of the bonding wire and the material is gold, copper or aluminum.
  13. 제8항에 있어서, 상기 기판은 인쇄회로기판(PCB), 테이프, 리드프레임(Lead Frame) 또는 웨이퍼 형태인 것을 특징으로 하는 반도체 패키지의 제조방법. 10. The method of claim 8, wherein the substrate is a method for manufacturing a semiconductor package, characterized in that the printed circuit board (PCB), a tape, a lead frame (Lead Frame) or wafer form.
KR1020060082924A 2006-08-30 2006-08-30 Semiconductor package and method for fabricating the same KR20080020069A (en)

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