JPS5150661A - - Google Patents
Info
- Publication number
- JPS5150661A JPS5150661A JP49124394A JP12439474A JPS5150661A JP S5150661 A JPS5150661 A JP S5150661A JP 49124394 A JP49124394 A JP 49124394A JP 12439474 A JP12439474 A JP 12439474A JP S5150661 A JPS5150661 A JP S5150661A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
- H01L2224/49173—Radial fan-out arrangements
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49124394A JPS5150661A (en) | 1974-10-30 | 1974-10-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49124394A JPS5150661A (en) | 1974-10-30 | 1974-10-30 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56152089A Division JPS5921168B2 (en) | 1981-09-28 | 1981-09-28 | Manufacturing method for semiconductor integrated circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5150661A true JPS5150661A (en) | 1976-05-04 |
Family
ID=14884327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP49124394A Pending JPS5150661A (en) | 1974-10-30 | 1974-10-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5150661A (en) |
Cited By (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5423563U (en) * | 1977-07-18 | 1979-02-16 | ||
| JPS56145841U (en) * | 1980-03-31 | 1981-11-04 | ||
| JPS56145842U (en) * | 1980-03-31 | 1981-11-04 | ||
| JP2005167004A (en) * | 2003-12-03 | 2005-06-23 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
| JP2014530511A (en) * | 2011-10-17 | 2014-11-17 | インヴェンサス・コーポレイション | Package on package assembly with wire bond vias |
| US9615456B2 (en) | 2012-12-20 | 2017-04-04 | Invensas Corporation | Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface |
| US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
| US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
| US9691731B2 (en) | 2011-05-03 | 2017-06-27 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
| US9691679B2 (en) | 2012-02-24 | 2017-06-27 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
| US9728527B2 (en) | 2013-11-22 | 2017-08-08 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
| US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
| US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
| US9812402B2 (en) | 2015-10-12 | 2017-11-07 | Invensas Corporation | Wire bond wires for interference shielding |
| US9837330B2 (en) | 2014-01-17 | 2017-12-05 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
| US9842745B2 (en) | 2012-02-17 | 2017-12-12 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
| US9852969B2 (en) | 2013-11-22 | 2017-12-26 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
| US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
| US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
| US9917073B2 (en) | 2012-07-31 | 2018-03-13 | Invensas Corporation | Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package |
| US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
| US9953914B2 (en) | 2012-05-22 | 2018-04-24 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
| US9984901B2 (en) | 2005-12-23 | 2018-05-29 | Tessera, Inc. | Method for making a microelectronic assembly having conductive elements |
| US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
| US10008469B2 (en) | 2015-04-30 | 2018-06-26 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
| US10008477B2 (en) | 2013-09-16 | 2018-06-26 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
| US10026717B2 (en) | 2013-11-22 | 2018-07-17 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
| US10128216B2 (en) | 2010-07-19 | 2018-11-13 | Tessera, Inc. | Stackable molded microelectronic packages |
| US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
| US10297582B2 (en) | 2012-08-03 | 2019-05-21 | Invensas Corporation | BVA interposer |
| US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
| US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
| US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
| US10460958B2 (en) | 2013-08-07 | 2019-10-29 | Invensas Corporation | Method of manufacturing embedded packaging with preformed vias |
| US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
-
1974
- 1974-10-30 JP JP49124394A patent/JPS5150661A/ja active Pending
Cited By (55)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5423563U (en) * | 1977-07-18 | 1979-02-16 | ||
| JPS5826525Y2 (en) * | 1977-07-18 | 1983-06-08 | 日本電気株式会社 | semiconductor equipment |
| JPS56145841U (en) * | 1980-03-31 | 1981-11-04 | ||
| JPS56145842U (en) * | 1980-03-31 | 1981-11-04 | ||
| JP2005167004A (en) * | 2003-12-03 | 2005-06-23 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
| US9984901B2 (en) | 2005-12-23 | 2018-05-29 | Tessera, Inc. | Method for making a microelectronic assembly having conductive elements |
| US10128216B2 (en) | 2010-07-19 | 2018-11-13 | Tessera, Inc. | Stackable molded microelectronic packages |
| US11424211B2 (en) | 2011-05-03 | 2022-08-23 | Tessera Llc | Package-on-package assembly with wire bonds to encapsulation surface |
| US9691731B2 (en) | 2011-05-03 | 2017-06-27 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
| US10593643B2 (en) | 2011-05-03 | 2020-03-17 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
| US10062661B2 (en) | 2011-05-03 | 2018-08-28 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
| US10756049B2 (en) | 2011-10-17 | 2020-08-25 | Invensas Corporation | Package-on-package assembly with wire bond vias |
| US11735563B2 (en) | 2011-10-17 | 2023-08-22 | Invensas Llc | Package-on-package assembly with wire bond vias |
| US9761558B2 (en) | 2011-10-17 | 2017-09-12 | Invensas Corporation | Package-on-package assembly with wire bond vias |
| JP2014530511A (en) * | 2011-10-17 | 2014-11-17 | インヴェンサス・コーポレイション | Package on package assembly with wire bond vias |
| US11189595B2 (en) | 2011-10-17 | 2021-11-30 | Invensas Corporation | Package-on-package assembly with wire bond vias |
| US9842745B2 (en) | 2012-02-17 | 2017-12-12 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
| US9691679B2 (en) | 2012-02-24 | 2017-06-27 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
| US10510659B2 (en) | 2012-05-22 | 2019-12-17 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
| US9953914B2 (en) | 2012-05-22 | 2018-04-24 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
| US9917073B2 (en) | 2012-07-31 | 2018-03-13 | Invensas Corporation | Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package |
| US10297582B2 (en) | 2012-08-03 | 2019-05-21 | Invensas Corporation | BVA interposer |
| US9615456B2 (en) | 2012-12-20 | 2017-04-04 | Invensas Corporation | Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface |
| US10460958B2 (en) | 2013-08-07 | 2019-10-29 | Invensas Corporation | Method of manufacturing embedded packaging with preformed vias |
| US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
| US10008477B2 (en) | 2013-09-16 | 2018-06-26 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
| US10629567B2 (en) | 2013-11-22 | 2020-04-21 | Invensas Corporation | Multiple plated via arrays of different wire heights on same substrate |
| US10026717B2 (en) | 2013-11-22 | 2018-07-17 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
| US9852969B2 (en) | 2013-11-22 | 2017-12-26 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
| US9728527B2 (en) | 2013-11-22 | 2017-08-08 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
| US10290613B2 (en) | 2013-11-22 | 2019-05-14 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
| US10529636B2 (en) | 2014-01-17 | 2020-01-07 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
| US9837330B2 (en) | 2014-01-17 | 2017-12-05 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
| US11404338B2 (en) | 2014-01-17 | 2022-08-02 | Invensas Corporation | Fine pitch bva using reconstituted wafer with area array accessible for testing |
| US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
| US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
| US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
| US10806036B2 (en) | 2015-03-05 | 2020-10-13 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
| US10008469B2 (en) | 2015-04-30 | 2018-06-26 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
| US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
| US10559537B2 (en) | 2015-10-12 | 2020-02-11 | Invensas Corporation | Wire bond wires for interference shielding |
| US10115678B2 (en) | 2015-10-12 | 2018-10-30 | Invensas Corporation | Wire bond wires for interference shielding |
| US11462483B2 (en) | 2015-10-12 | 2022-10-04 | Invensas Llc | Wire bond wires for interference shielding |
| US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
| US9812402B2 (en) | 2015-10-12 | 2017-11-07 | Invensas Corporation | Wire bond wires for interference shielding |
| US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
| US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
| US10043779B2 (en) | 2015-11-17 | 2018-08-07 | Invensas Corporation | Packaged microelectronic device for a package-on-package device |
| US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
| US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
| US10325877B2 (en) | 2015-12-30 | 2019-06-18 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
| US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
| US10658302B2 (en) | 2016-07-29 | 2020-05-19 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
| US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
| US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |