JP2007234845A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2007234845A
JP2007234845A JP2006054362A JP2006054362A JP2007234845A JP 2007234845 A JP2007234845 A JP 2007234845A JP 2006054362 A JP2006054362 A JP 2006054362A JP 2006054362 A JP2006054362 A JP 2006054362A JP 2007234845 A JP2007234845 A JP 2007234845A
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electrode terminal
substrate
internal
signal
semiconductor chip
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Kenji Kawamura
健児 河村
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein the observation of an internal signal can easily be carried out without preventing the miniaturization of a substrate having a chip mounted thereon. <P>SOLUTION: The semiconductor chip 5 comprises an electrode terminal 7a for outputting the internal signal or for inputting the signal required to output the internal signal, and an electrode terminal 7b for outputting the actuating signal for achieving the function as the semiconductor chip or for inputting the signal required to output the actuating signal. Those electrode terminals 7a and 7b are provided on the surface of the chip 5 different from that bonded to the substrate 6. The electrode terminal 7a is connected with a lead frame 11 installed on the substrate 6 via no internal wiring 10 of the substrate 6, and the electrode terminal 7b is connected with an electrode terminal 9 installed on the substrate 6 via a wire 8 and is connected with an external electrode terminal 3 installed on the substrate 6 via the internal wiring 10 of the substrate 6. The lead frame 11 passes through a resin 2 and the upper end thereof is provided with an external electrode terminal 4. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置に関し、特に、パッケージの面積を増大させることなく、内部信号の観測を容易に行える構成とした半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly, to a semiconductor device configured to easily observe an internal signal without increasing a package area.

半導体装置の外部電極端子は、プリント基板を介して他のＬＳＩやコネクタなどと接続するための目的を持つ信号の他に、ＬＳＩ自身が正常に動作しているかを観測するためのＬＳＩ内部の信号を出力するために用いられることもある。   The external electrode terminal of the semiconductor device is a signal inside the LSI for observing whether the LSI itself is operating normally, in addition to a signal having the purpose of connecting to another LSI or a connector via a printed circuit board. May be used to output.

例えば、ＬＳＩパッケージの内部が、ＣＰＵを含むＡＳＩＣから構成される機能ブロックと、メモリから構成される機能ブロックとに分けられる場合、ＡＳＩＣがメモリに対してアクセスするための専用信号（アドレスバスやデータバス、リード・ライト信号など）は、本来ＬＳＩ内部で閉じて良い（外部へ出力する必要のない）信号であり、わざわざＬＳＩパッケージの外部電極端子から出力する必要はないが、ＡＳＩＣ−メモリ間の信号が正常であるか否かを確認するために外部電極端子から出力する場合がある。   For example, when the LSI package is divided into a functional block composed of an ASIC including a CPU and a functional block composed of a memory, a dedicated signal (address bus or data) for the ASIC to access the memory Buses, read / write signals, etc.) are signals that may be originally closed inside the LSI (no need to be output to the outside), and need not be output from the external electrode terminals of the LSI package, but between the ASIC and the memory In some cases, the signal is output from the external electrode terminal to confirm whether the signal is normal.

しかしながら、内部信号をＬＳＩパッケージの外部へ出力することは、外部電極端子が増えることに他ならず、ＬＳＩパッケージの面積が大きくなるというデメリットがある。   However, outputting the internal signal to the outside of the LSI package has the demerit that the area of the LSI package is increased without increasing the number of external electrode terminals.

特に、ＢＧＡ（Ball Grid Array）型ＬＳＩパッケージの場合は、外部電極端子をパッケージ裏面に配置しているために、ＬＳＩ内部信号を観測するための外部電極端子用の配線やランドパターンをプリント基板上に形成しなければならなくなり、プリント基板の面積も大きくなるというデメリットがある。   In particular, in the case of a BGA (Ball Grid Array) type LSI package, since external electrode terminals are arranged on the back of the package, wiring for external electrode terminals and land patterns for observing LSI internal signals are provided on the printed circuit board. There is a demerit that the area of the printed circuit board becomes large.

図１７及び図１８に、従来のＢＧＡ型ＬＳＩパッケージの外観及び断面を示す。ＢＧＡ型のＬＳＩパッケージ１’は、基板６の上に半導体チップ５が搭載され、基板６の電極端子９と半導体チップ５の電極端子７とがワイヤ８を介して接続され、これらが樹脂２によって封止された構成である。   17 and 18 show the appearance and cross section of a conventional BGA type LSI package. In the BGA type LSI package 1 ′, a semiconductor chip 5 is mounted on a substrate 6, an electrode terminal 9 of the substrate 6 and an electrode terminal 7 of the semiconductor chip 5 are connected via a wire 8, and these are connected by a resin 2. It is a sealed configuration.

図示するように、従来のＢＧＡ型ＬＳＩパッケージは、プリント基板との接合部である外部電極端子３が全てＬＳＩパッケージの裏面に配置されている。そのため、同面積のＱＦＰ（Quad Flat Package）型ＬＳＩパッケージと比較して外部電極端子の数を多くできるが、その反面、プリント基板実装後に外部電極端子を直接見たり、触れたりすることはできない。
すなわち、プリント基板に実装した後でも電極端子に測定器のプローブを接触させることのできるＱＦＰ型ＬＳＩパッケージとは異なり、従来のＢＧＡ型ＬＳＩパッケージはプリント基板に実装してしまうと電極端子に測定器のプローブを接触させることはできない。 As shown in the figure, in the conventional BGA type LSI package, all of the external electrode terminals 3 which are joints with the printed circuit board are arranged on the back surface of the LSI package. For this reason, the number of external electrode terminals can be increased as compared with a QFP (Quad Flat Package) type LSI package of the same area, but on the other hand, the external electrode terminals cannot be directly seen or touched after mounting on a printed board.
That is, unlike a QFP type LSI package in which a probe of a measuring instrument can be brought into contact with an electrode terminal even after being mounted on a printed circuit board, a conventional BGA type LSI package is mounted on the printed circuit board when the measuring instrument is connected to the electrode terminal. The probe cannot be brought into contact.

このため、従来のＢＧＡ型ＬＳＩパッケージにおいては、ＬＳＩから出力される信号の状態をプリント基板に実装した後で測定器のプローブを用いて観測するためには、外部電極から出力された信号をプリント基板上で観測するしかなく、そのためにプリント基板上に検査用のランドパターンを設けなければならない。これが上記のようなプリント基板の面積の増大を招く原因となっていた。   For this reason, in the conventional BGA type LSI package, in order to observe the state of the signal output from the LSI on the printed circuit board using the probe of the measuring instrument, the signal output from the external electrode is printed. In order to do so, observation land patterns must be provided on a printed circuit board. This has been a cause of an increase in the area of the printed circuit board as described above.

このような問題を解決するための従来技術として、特許文献１に開示される「半導体装置及び半導体装置ユニット」、特許文献２に開示される「半導体装置」、特許文献３に開示される「マルチチップ半導体装置」、特許文献４に開示される「ＢＧＡ型半導体装置及びＢＧＡモジュール」がある。
各特許文献に開示される発明は、外部電極端子の一部を半導体装置の上面側に配置することによって、プリント基板に実装した後でも半導体装置の内部信号を直接観測できるようにしたものである。
特開平７−３３５７８３号公報 特開平８−２７９５７０号公報 特開平９−８２２０号公報 特開平９−６９５８７号公報 As conventional techniques for solving such problems, “semiconductor device and semiconductor device unit” disclosed in Patent Document 1, “semiconductor device” disclosed in Patent Document 2, and “multi-device” disclosed in Patent Document 3 are disclosed. “Chip semiconductor device” and “BGA type semiconductor device and BGA module” disclosed in Patent Document 4.
In the invention disclosed in each patent document, a part of the external electrode terminal is arranged on the upper surface side of the semiconductor device so that the internal signal of the semiconductor device can be directly observed even after being mounted on the printed circuit board. .
Japanese Patent Laid-Open No. 7-335783 JP-A-8-279570 JP-A-9-8220 Japanese Patent Laid-Open No. 9-69587

しかし、特許文献１〜４に開示される発明は、いずれもＬＳＩ内部信号を一旦チップから基板へと導いており、基板へ導かれた内部信号は、封止樹脂に設けたスルーホールなどを介して底面側の基板からＬＳＩ上面の電極端子へと送られる。このような構造では、ＬＳＩ内部信号の伝送路となる配線を基板に設けなければならない。すなわち、上記各特許文献に開示される発明では、ＬＳＩパッケージの面積増大は避けられない。   However, in all of the inventions disclosed in Patent Documents 1 to 4, the LSI internal signal is once guided from the chip to the substrate, and the internal signal guided to the substrate passes through a through hole provided in the sealing resin. Then, it is sent from the substrate on the bottom side to the electrode terminal on the top surface of the LSI. In such a structure, it is necessary to provide wiring on the substrate as a transmission path for LSI internal signals. That is, in the invention disclosed in each of the above patent documents, an increase in the area of the LSI package is inevitable.

本発明はかかる問題に鑑みてなされたものであり、チップを搭載する基板の小型化を妨げることなく、内部信号の観測を容易に行える構成の半導体装置を提供することを目的とする。   The present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor device having a configuration capable of easily observing an internal signal without hindering downsizing of a substrate on which a chip is mounted.

上記目的を達成するため、本発明は、第１の態様として、一方の面に半導体チップが搭載された基板の該半導体チップが搭載された側の面を樹脂によって封止した半導体装置であって、半導体チップは、内部信号を出力するため、又は該内部信号を出力するために必要な信号を入力するための第１の内部電極端子と、半導体チップとしての機能を実現するための動作信号を出力するため、又は該動作信号を出力するために必要な信号を入力するための第２の内部電極端子とを基板との接合面とは異なる面に備え、第１の内部電極端子は、基板上に設置された導電性部材と該基板内部の配線を介することなく電気的に接続されており、第２の内部電極端子は、基板上に設置された基板電極端子とワイヤを介して接続され、基板に設けられた外部電極端子とは該基板内部の配線を介して電気的に接続されており、導電性部材は、樹脂を貫通しており、上端部には内部検査用電極端子が設けられているを提供するものである。   In order to achieve the above object, the present invention provides, as a first aspect, a semiconductor device in which a surface of a substrate on which a semiconductor chip is mounted on one surface is sealed with a resin. The semiconductor chip has a first internal electrode terminal for inputting an internal signal or a signal necessary for outputting the internal signal, and an operation signal for realizing a function as the semiconductor chip. A second internal electrode terminal for inputting a signal necessary for outputting or a signal necessary for outputting the operation signal is provided on a surface different from a bonding surface with the substrate, and the first internal electrode terminal is provided on the substrate. It is electrically connected to the conductive member installed on the substrate without going through the wiring inside the substrate, and the second internal electrode terminal is connected to the substrate electrode terminal installed on the substrate via a wire. External provided on the board The electrode terminal is electrically connected via the wiring inside the substrate, the conductive member penetrates the resin, and the upper end is provided with an electrode terminal for internal inspection. It is.

本発明の第１の態様においては、導電性部材と第１の内部電極端子とがワイヤボンディングによって接続されることが好ましく、これに加えて、導電性部材は、帯状の部材が側面視略Ｌ字形状に折り曲げられて所定の位置に設置され、内部電極端子とワイヤボンディングされた後で上端部がさらに折り曲げられて側面視略コの字形状に成型されていることがより好ましい。   In the first aspect of the present invention, it is preferable that the conductive member and the first internal electrode terminal are connected by wire bonding. In addition, the conductive member has a belt-like member substantially in side view L. More preferably, the upper end portion is further bent and formed into a substantially U-shape when viewed from the side after being bent into a U shape and placed at a predetermined position and wire-bonded to the internal electrode terminal.

また、上記目的を達成するため、本発明は、第２の態様として、一方の面に半導体チップが搭載された基板の該半導体チップが搭載された側の面を樹脂によって封止した半導体装置であって、半導体チップは、内部信号を出力するため、又は該内部信号を出力するために必要な信号を入力するための第１の内部電極端子と、半導体チップとしての機能を実現するための動作信号を出力するため、又は該動作信号を出力するために必要な信号を入力するための第２の内部電極端子とを基板との接合面とは異なる面に備え、第１の内部電極端子は、半導体チップ上に設置された導電性部材と基板を介することなく電気的に接続されており、第２の内部電極端子は、基板上に設置された基板電極端子とワイヤを介して接続され、基板に設けられた外部電極端子とは該基板内部の配線を介して電気的に接続されており、導電性部材は、樹脂を貫通しており、上端部には内部検査用電極端子が設けられていることを特徴とする半導体装置を提供するものである。   In order to achieve the above object, according to a second aspect of the present invention, there is provided a semiconductor device in which a surface of a substrate on which a semiconductor chip is mounted on one surface is sealed with a resin. The semiconductor chip has a first internal electrode terminal for inputting an internal signal or inputting a signal necessary for outputting the internal signal, and an operation for realizing a function as the semiconductor chip. A second internal electrode terminal for inputting a signal necessary for outputting a signal or inputting a signal necessary for outputting the operation signal is provided on a surface different from the bonding surface with the substrate, and the first internal electrode terminal is The second internal electrode terminal is electrically connected to the conductive member installed on the semiconductor chip without going through the substrate, and the second internal electrode terminal is connected to the substrate electrode terminal installed on the substrate through a wire, Outside the board The electrode terminal is electrically connected via wiring inside the substrate, the conductive member penetrates the resin, and an internal inspection electrode terminal is provided at the upper end. A semiconductor device is provided.

本発明の第２の態様においては、導電性部材と第１の内部電極端子とがワイヤボンディングによって接続されることが好ましく、これに加えて、導電性部材は、帯状の部材が側面視略Ｌ字形状に折り曲げられて所定の位置に設置され、内部電極端子とワイヤボンディングされた後で上端部がさらに折り曲げられて側面視略コの字形状に成型されていることがより好ましい。又は、導電性部材が第１の内部電極端子の上に設置されることが好ましい。   In the second aspect of the present invention, it is preferable that the conductive member and the first internal electrode terminal are connected by wire bonding. In addition, the conductive member has a belt-like member substantially in side view L. More preferably, the upper end portion is further bent and formed into a substantially U-shape when viewed from the side after being bent into a U shape and placed at a predetermined position and wire-bonded to the internal electrode terminal. Alternatively, it is preferable that the conductive member is installed on the first internal electrode terminal.

本発明の第１の態様及び第２の態様の上記のいずれの構成においても、外部電極端子の上に絶縁層が剥離可能に形成されていることが好ましい。   In any of the above configurations of the first aspect and the second aspect of the present invention, it is preferable that the insulating layer is formed on the external electrode terminal so as to be peelable.

本発明の第１の態様及び第２の態様の上記のいずれの構成においても、外部電極端子は、球状であり、基板の樹脂によって封止されていない側の面に形成されたＢＧＡ型であることが好ましい。又は、外部電極端子は針状であり、基板の樹脂によって封止されていない側の面に形成されたＰＧＡ型であることが好ましい。又は、基板が、側面に外部電極端子を備えることが好ましい。   In any of the above-described configurations of the first and second aspects of the present invention, the external electrode terminal has a spherical shape and is a BGA type formed on the surface of the substrate that is not sealed with resin. It is preferable. Alternatively, the external electrode terminal has a needle shape and is preferably a PGA type formed on the surface of the substrate that is not sealed with resin. Or it is preferable that a board | substrate is provided with an external electrode terminal in a side surface.

本発明によれば、チップを搭載する基板の小型化を妨げることなく、内部信号の観測を容易に行える構成の半導体装置を提供できる。   According to the present invention, it is possible to provide a semiconductor device having a configuration capable of easily observing an internal signal without hindering downsizing of a substrate on which a chip is mounted.

〔第１の実施形態〕
本発明を好適に実施した第１の実施形態について説明する。
図１に、本実施形態にかかるＬＳＩパッケージの外観を示す。ＢＧＡ型ＬＳＩパッケージ１は、樹脂２で封止されており、その裏面（底面）にはプリント基板と接合するための外部電極端子３が複数設けられている。また、ＢＧＡ型ＬＳＩパッケージ１の表面（上面）には、内部信号観測用の外部電極端子４が複数設けられている。 [First Embodiment]
A first embodiment in which the present invention is suitably implemented will be described.
FIG. 1 shows the appearance of the LSI package according to the present embodiment. The BGA type LSI package 1 is sealed with a resin 2, and a plurality of external electrode terminals 3 for bonding to a printed circuit board are provided on the back surface (bottom surface). A plurality of external electrode terminals 4 for observing internal signals are provided on the surface (upper surface) of the BGA type LSI package 1.

図２に、ＢＧＡ型ＬＳＩパッケージ１の縦断面（底面と垂直方向の断面）を示す。図示するのは図１のａ−ｂ線での断面である。また、図３に、ＢＧＡ型ＬＳＩパッケージ１の横断面（底面と平行な方向の断面）を示す。図示するのは図１のｃ−ｄ線での断面である。   FIG. 2 shows a longitudinal section (a section perpendicular to the bottom surface) of the BGA type LSI package 1. Shown is a cross section taken along line ab in FIG. FIG. 3 shows a cross section of the BGA type LSI package 1 (cross section in a direction parallel to the bottom surface). Shown is a cross section taken along line cd in FIG.

半導体チップ５は、ＣＰＵ、ＡＳＩＣ、メモリなどで構成されており、基板６上に設置される。   The semiconductor chip 5 includes a CPU, an ASIC, a memory, and the like, and is installed on the substrate 6.

半導体チップ５上の複数の電極端子７の一部（７ｂ）は、各々ワイヤ８を一本ずつ介して基板６の上の複数個の電極端子９のいずれかと電気的に接続されている。電極端子９は、基板６に形成された内部配線１０を介して外部電極端子３と電気的に接続されている。   A part (7b) of the plurality of electrode terminals 7 on the semiconductor chip 5 is electrically connected to one of the plurality of electrode terminals 9 on the substrate 6 through one wire 8 each. The electrode terminal 9 is electrically connected to the external electrode terminal 3 through an internal wiring 10 formed on the substrate 6.

これとは別に、半導体チップ５上の電極端子７の残りの一部（７ａ）は、各々ワイヤ８を一本ずつ介して側面視略コの字形のリードフレーム１１のいずれかに接続され、これを介して外部電極端子４と電気的に接続されている。   Apart from this, the remaining part (7a) of the electrode terminal 7 on the semiconductor chip 5 is connected to one of the substantially U-shaped lead frames 11 through the wires 8 one by one. Is electrically connected to the external electrode terminal 4 via

リードフレーム１１は、帯状部材の上端部及び下端部が基板６と略平行に折り曲げられた側面視略コの字形状であるが、ＢＧＡ型ＬＳＩパッケージ１の製造過程においては上端部は基板６と垂直な状態（すなわち、側面視略Ｌ字形状）であり、下端部の上面にワイヤ８をボンディングした後で上端部を基板６と略平行に折り曲げることによって略コの字状に成型される。これにより、ワイヤ８のボンディングのしやすさと、外部電極端子４の面積の確保とを両立させている。   The lead frame 11 has a substantially U-shape in a side view in which the upper end portion and the lower end portion of the belt-like member are bent substantially in parallel with the substrate 6, but the upper end portion is connected to the substrate 6 in the manufacturing process of the BGA type LSI package 1. It is in a vertical state (that is, substantially L-shaped when viewed from the side), and is formed into a substantially U shape by bending the upper end portion substantially parallel to the substrate 6 after bonding the wire 8 to the upper surface of the lower end portion. Thereby, both the ease of bonding of the wire 8 and the securing of the area of the external electrode terminal 4 are compatible.

外部電極端子３，４、電極端子７，９、ワイヤ８、内部配線１０、及びリードフレーム１１はいずれも導体で形成されている。   The external electrode terminals 3 and 4, the electrode terminals 7 and 9, the wire 8, the internal wiring 10, and the lead frame 11 are all formed of a conductor.

図４に、ＢＧＡ型ＬＳＩパッケージ１の機能構成を示す。半導体チップ５の内部には二つの機能ブロック（第１の機能部１０２、第２の機能部１０３）が構成されている。第１の機能部１０２は、半導体チップ５の外部へ信号１０４を出力し、半導体チップ５の外部から信号１０５が入力される。第２の機能部１０３は、半導体チップ５の外部から信号１０８が入力され、半導体チップ５の外部へ信号１０９を出力する。
信号１０４及び１０９は、外部電極端子３を介して半導体チップ５の外部へ出力される。また、信号１０５及び１０８は、外部電極端子３のいずれかを介して半導体チップ５の内部へ入力される。 FIG. 4 shows a functional configuration of the BGA type LSI package 1. Inside the semiconductor chip 5, two functional blocks (a first functional unit 102 and a second functional unit 103) are configured. The first functional unit 102 outputs a signal 104 to the outside of the semiconductor chip 5, and a signal 105 is input from the outside of the semiconductor chip 5. The second functional unit 103 receives a signal 108 from the outside of the semiconductor chip 5 and outputs a signal 109 to the outside of the semiconductor chip 5.
The signals 104 and 109 are output to the outside of the semiconductor chip 5 through the external electrode terminal 3. The signals 105 and 108 are input into the semiconductor chip 5 via any one of the external electrode terminals 3.

内部信号１０６，１０７は、第１の機能部１０２から第２の機能部１０３へ、又は第２の機能部１０３から第１の機能部１０２へ出力される信号であり、半導体チップ５の外部へ出力しなくても機能上問題の無い信号である。ただし、外部電極端子３から出力される信号１０５又は１０８が正常でない場合に、第１の機能部１０２に原因があるのか第２の機能部１０３に原因があるのかを切り分けるために半導体チップ５の外部へ出力することは非常に効果的である。   The internal signals 106 and 107 are signals output from the first functional unit 102 to the second functional unit 103 or from the second functional unit 103 to the first functional unit 102, and are output to the outside of the semiconductor chip 5. It is a signal that has no functional problem even if it is not output. However, when the signal 105 or 108 output from the external electrode terminal 3 is not normal, in order to determine whether the cause is in the first function unit 102 or the cause in the second function unit 103, Output to the outside is very effective.

ＢＧＡ型ＬＳＩパッケージ１は、内部信号１０６，１０７を外部電極端子４から出力する。外部電極端子４は、樹脂２の上面に設けられているため、ＢＧＡ型ＬＳＩパッケージ１に、観測したい内部信号の数ぶんの外部電極端子３を増やす必要はない。よって、外部電極端子３の増加に伴ってＢＧＡ型ＬＳＩパッケージ１の底面積が大きくなることはない。   The BGA type LSI package 1 outputs internal signals 106 and 107 from the external electrode terminal 4. Since the external electrode terminals 4 are provided on the upper surface of the resin 2, it is not necessary to increase the number of external electrode terminals 3 corresponding to the number of internal signals to be observed in the BGA type LSI package 1. Therefore, the bottom area of the BGA type LSI package 1 does not increase with the increase in the number of external electrode terminals 3.

また、図５に示すように、外部電極端子４を用いてＢＧＡ型ＬＳＩパッケージ１の内部信号１０６，１０７の信号波形を直接プローブで測定できるため、プリント基板に検査用のランドを設ける従来の手法と比較して、より正確に信号波形を観測できる。   Further, as shown in FIG. 5, since the signal waveforms of the internal signals 106 and 107 of the BGA type LSI package 1 can be directly measured by a probe using the external electrode terminal 4, a conventional method of providing an inspection land on a printed circuit board. Compared with, the signal waveform can be observed more accurately.

本実施形態にかかるＢＧＡ型ＬＳＩパッケージ１の製造方法について説明する。基板６に半導体チップ５を実装し、半導体チップ５と電極端子９とをワイヤ８でボンディングするまでの工程は、従来のＢＧＡ型ＬＳＩパッケージの製造工程と同様である。図１０に、半導体チップ５と電極端子９とをワイヤ８でボンディングした後の状態を示す。   A method for manufacturing the BGA type LSI package 1 according to the present embodiment will be described. The process from mounting the semiconductor chip 5 on the substrate 6 and bonding the semiconductor chip 5 and the electrode terminal 9 with the wire 8 is the same as the manufacturing process of the conventional BGA type LSI package. FIG. 10 shows a state after bonding the semiconductor chip 5 and the electrode terminal 9 with the wire 8.

図１１に、基板６にリードフレーム１１を実装し、半導体チップ５の上面の外部電極端子４とワイヤ８を介して接続した状態を示す。リードフレーム１１は、この段階（基板６に実装する段階）ではまだコの字形に成型されておらず、略Ｌ字形である。
半導体チップ５とリードフレーム１１の下端部の上面とをワイヤ８を介して電気的に接続することによって、半導体チップ５とリードフレーム１１とを電気的に接続するための配線を基板６に設ける必要が無くなる。半導体チップ５の内部信号を外部へ出力できるようにするために必要となるのは、リードフレーム１１を実装するスペースのみであるから、半導体チップ５の内部信号を外部へ出力できる構成としても基板６の面積はほとんど増加しない。 FIG. 11 shows a state in which the lead frame 11 is mounted on the substrate 6 and is connected to the external electrode terminals 4 on the upper surface of the semiconductor chip 5 via the wires 8. The lead frame 11 has not been formed into a U-shape at this stage (the stage where it is mounted on the substrate 6), and is substantially L-shaped.
It is necessary to provide wiring on the substrate 6 for electrically connecting the semiconductor chip 5 and the lead frame 11 by electrically connecting the semiconductor chip 5 and the upper surface of the lower end portion of the lead frame 11 via the wire 8. Disappears. Since only the space for mounting the lead frame 11 is required to allow the internal signal of the semiconductor chip 5 to be output to the outside, the substrate 6 can be configured to output the internal signal of the semiconductor chip 5 to the outside. The area of is hardly increased.

リードフレーム１１は、ワイヤ８をボンディングする段階では略Ｌ字状であるため、ボンディング作業の妨げとはならない。   Since the lead frame 11 is substantially L-shaped when the wire 8 is bonded, it does not hinder the bonding operation.

ワイヤ８のボンディングが完了した後、リードフレーム１１の上端側が所定長さだけ突出するように樹脂２で封止する。その後、図１２に示すように、リードフレーム１１の上端側を基板６と略平行に折り曲げて側面視略コの字形状とする。   After the bonding of the wire 8 is completed, the lead frame 11 is sealed with the resin 2 so that the upper end side of the lead frame 11 protrudes by a predetermined length. Thereafter, as shown in FIG. 12, the upper end side of the lead frame 11 is bent substantially parallel to the substrate 6 to obtain a substantially U-shape when viewed from the side.

リードフレーム１１の上端部を折り曲げた後、折り曲げた部分を除いてさらに樹脂２で封止する。これにより、リードフレーム１１の上端部が折り曲げられた部分の上に凹部が形成される。図１３に示すように、この凹部にははんだボールが設置される。設置されたはんだボールは樹脂２と同じ高さとなるように上面が切断され、ＢＧＡ型ＬＳＩパッケージ１が完成する。   After the upper end portion of the lead frame 11 is bent, the lead frame 11 is further sealed with the resin 2 except for the bent portion. Thereby, a concave portion is formed on a portion where the upper end portion of the lead frame 11 is bent. As shown in FIG. 13, solder balls are placed in the recesses. The upper surface of the installed solder ball is cut so as to have the same height as the resin 2, and the BGA type LSI package 1 is completed.

上記工程を経て形成したＢＧＡ型ＬＳＩパッケージ１は、上面が平坦であるため、図１４に示すように、外部電極端子４の上に絶縁層（絶縁塗料や絶縁シール）を形成することによって、外部電極端子４を容易に絶縁できる。これにより、内部信号をＢＧＡ型ＬＳＩパッケージ１の外部に出力する必要がないときに、外部電極端子４からパッケージ内にノイズが侵入する恐れが無い。   Since the BGA type LSI package 1 formed through the above steps has a flat top surface, as shown in FIG. 14, by forming an insulating layer (insulating paint or insulating seal) on the external electrode terminal 4, the external The electrode terminal 4 can be easily insulated. Thereby, when there is no need to output an internal signal to the outside of the BGA type LSI package 1, there is no possibility that noise enters the package from the external electrode terminal 4.

本実施形態にかかるＢＧＡ型ＬＳＩパッケージ１は、プリント基板に実装したあとでも外部電極端子４に測定器のプローブを接触させられるため、半導体チップ５に不具合が生じた場合などに、外部電極端子４を用いて内部信号の信号波形を容易かつ正確に観測できる。   In the BGA type LSI package 1 according to the present embodiment, the probe of the measuring instrument can be brought into contact with the external electrode terminal 4 even after being mounted on the printed circuit board. Can be used to easily and accurately observe the signal waveform of the internal signal.

しかも、ＢＧＡ型であるにもかかわらず、プリント基板に検査用のランドパターンを設けておかなくても半導体チップ５の内部信号を観測可能である。   Moreover, the internal signal of the semiconductor chip 5 can be observed without providing a land pattern for inspection on the printed circuit board despite the BGA type.

なお、ここではリードフレーム１１を略コの字状に成型する場合を例としたが、リードフレームの上端部を下端部とは逆方向に折り曲げてクランク形状としても良いことは言うまでもない。   In this example, the lead frame 11 is molded into a substantially U shape, but it goes without saying that the upper end portion of the lead frame may be bent in a direction opposite to the lower end portion to form a crank shape.

〔第２の実施形態〕
本発明を好適に実施した第２の実施形態について説明する。図６に、本実施形態にかかるＢＧＡ型ＬＳＩパッケージの構成を示す。ＢＧＡ型ＬＳＩパッケージ１は、半導体チップを二つ（５ａ、５ｂ）備える他は、第１の実施形態のＢＧＡ型ＬＳＩパッケージ１と同様の構成である。 [Second Embodiment]
A second embodiment in which the present invention is suitably implemented will be described. FIG. 6 shows the configuration of the BGA type LSI package according to this embodiment. The BGA type LSI package 1 has the same configuration as the BGA type LSI package 1 of the first embodiment, except that two semiconductor chips (5a, 5b) are provided.

図７に、本実施形態にかかるＢＧＡ型ＬＳＩパッケージ１の機能構成を示す。半導体チップ５ａ、５ｂは、それぞれ内部に一つの機能ブロックが構成されるものとする。
半導体チップ５ａは、ＢＧＡ型ＬＳＩパッケージ１の外部へ信号２０４を出力し、ＢＧＡ型ＬＳＩパッケージ１の外部から信号２０５が入力される。半導体チップ５ｂは、ＢＧＡ型ＬＳＩパッケージ１の外部から信号２０８が入力され、ＢＧＡ型ＬＳＩパッケージ１の外部へ信号２０９を出力する。
信号２０４及び２０９は、外部電極端子３を介してＢＧＡ型ＬＳＩパッケージ１の外部へ出力される。また、信号２０５及び２０８は、外部電極端子３のいずれかを介してＢＧＡ型ＬＳＩパッケージ１の内部へ入力される。 FIG. 7 shows a functional configuration of the BGA type LSI package 1 according to the present embodiment. The semiconductor chips 5a and 5b are each configured with one functional block.
The semiconductor chip 5a outputs a signal 204 to the outside of the BGA type LSI package 1, and a signal 205 is input from the outside of the BGA type LSI package 1. The semiconductor chip 5 b receives a signal 208 from the outside of the BGA type LSI package 1 and outputs a signal 209 to the outside of the BGA type LSI package 1.
The signals 204 and 209 are output to the outside of the BGA type LSI package 1 through the external electrode terminal 3. The signals 205 and 208 are input to the inside of the BGA type LSI package 1 via any one of the external electrode terminals 3.

内部信号２０６，２０７は、半導体チップ５ａから半導体チップ５ｂへ、又は半導体チップ５ｂから半導体チップ５ａへ出力される信号であり、ＢＧＡ型ＬＳＩパッケージ１の外部へ出力しなくても機能上問題の無い信号である。ただし、外部電極端子３から出力される信号２０５又は２０８が正常でない場合に、半導体チップ５ａに原因があるのか半導体チップ５ｂに原因があるのかを切り分けるためにＢＧＡ型ＬＳＩパッケージ１の外部へ出力することは非常に効果的である。   The internal signals 206 and 207 are signals output from the semiconductor chip 5a to the semiconductor chip 5b or from the semiconductor chip 5b to the semiconductor chip 5a, and there is no functional problem even if they are not output to the outside of the BGA type LSI package 1. Signal. However, when the signal 205 or 208 output from the external electrode terminal 3 is not normal, the signal 205 or 208 is output to the outside of the BGA type LSI package 1 in order to determine whether the cause is the semiconductor chip 5a or the semiconductor chip 5b. It is very effective.

ＢＧＡ型ＬＳＩパッケージ１は、内部信号２０６，２０７を外部電極端子４から出力する。外部電極端子４は、樹脂２の上面に設けられているため、ＢＧＡ型ＬＳＩパッケージ１に、観測したい内部信号の数ぶんの外部電極端子３を増やす必要はない。よって、外部電極端子３の増加に伴ってＢＧＡ型ＬＳＩパッケージ１の底面積が大きくなることはない。   The BGA type LSI package 1 outputs internal signals 206 and 207 from the external electrode terminal 4. Since the external electrode terminals 4 are provided on the upper surface of the resin 2, it is not necessary to increase the number of external electrode terminals 3 corresponding to the number of internal signals to be observed in the BGA type LSI package 1. Therefore, the bottom area of the BGA type LSI package 1 does not increase with the increase in the number of external electrode terminals 3.

また、第１の実施形態と同様に、外部電極端子４を用いてＢＧＡ型ＬＳＩパッケージ１の内部信号２０６，２０７の信号波形を直接プローブで測定できるため、プリント基板に検査用のランドを設ける従来の手法よりもより正確に信号波形を観測できる。   Similarly to the first embodiment, since the signal waveforms of the internal signals 206 and 207 of the BGA type LSI package 1 can be directly measured by the probe using the external electrode terminal 4, a conventional test land is provided on the printed circuit board. The signal waveform can be observed more accurately than the above method.

本実施形態にかかるＢＧＡ型ＬＳＩパッケージ１は、プリント基板に実装したあとでも外部電極端子４に測定器のプローブを接触させられるため、半導体チップ５ａ、５ｂに不具合が生じた場合などに、外部電極端子４を用いて内部信号の信号波形を容易かつ正確に観測できる。   In the BGA type LSI package 1 according to the present embodiment, since the probe of the measuring instrument can be brought into contact with the external electrode terminal 4 even after being mounted on the printed board, the external electrode can be used when the semiconductor chip 5a, 5b has a problem. The signal waveform of the internal signal can be easily and accurately observed using the terminal 4.

本実施形態においては、半導体チップ５ａ及び５ｂのそれぞれを一つの機能ブロックと見なす場合を例として説明したが、第１の実施形態と同様に半導体チップ５ａや５ｂ内に複数の機能ブロックが形成されていても良い。
また、本実施形態においては、半導体チップ５ａ及び５ｂを積層させて配置した構成を例としたが、基板６上に複数の半導体チップ５を配列させることも可能である。 In the present embodiment, the case where each of the semiconductor chips 5a and 5b is regarded as one functional block has been described as an example. However, a plurality of functional blocks are formed in the semiconductor chips 5a and 5b as in the first embodiment. May be.
In the present embodiment, the semiconductor chips 5 a and 5 b are stacked and arranged, but a plurality of semiconductor chips 5 can be arranged on the substrate 6.

〔第３の実施形態〕
本発明を好適に実施した第３の実施形態について説明する。
図１５に、本実施形態にかかるＢＧＡ型ＬＳＩパッケージの縦断面を示す。図１６に、本実施形態にかかるＢＧＡ型ＬＳＩパッケージ１の横断面を示す。
本実施形態にかかるＢＧＡ型ＬＳＩパッケージ１は、第１の実施形態とほぼ同様の構成であるが、リードフレーム１１は、基板６上ではなく半導体チップ５上に設置されている。外部電極端子４とリードフレーム８とはワイヤ８を介して電気的に接続されている。 [Third Embodiment]
A third embodiment in which the present invention is preferably implemented will be described.
FIG. 15 shows a longitudinal section of the BGA type LSI package according to the present embodiment. FIG. 16 shows a cross section of the BGA type LSI package 1 according to the present embodiment.
The BGA type LSI package 1 according to the present embodiment has substantially the same configuration as that of the first embodiment, but the lead frame 11 is installed not on the substrate 6 but on the semiconductor chip 5. The external electrode terminal 4 and the lead frame 8 are electrically connected via a wire 8.

本実施形態にかかるＢＧＡ型ＬＳＩパッケージ１は、基板６の上にはリードフレーム１１を設置するためのスペースをも設ける必要がないため、従来のＢＧＡ型ＬＳＩパッケージと比較して基板６の面積は全く増加していない。   Since the BGA type LSI package 1 according to the present embodiment does not require a space for installing the lead frame 11 on the substrate 6, the area of the substrate 6 is smaller than that of the conventional BGA type LSI package. It has not increased at all.

しかも、上記第１の実施形態と同様に、ＢＧＡ型であるにもかかわらず、プリント基板に検査用のランドパターンを設けなくても半導体チップ５の内部信号を観測可能である。   In addition, as in the first embodiment, the internal signal of the semiconductor chip 5 can be observed without providing a land pattern for inspection on the printed circuit board despite the BGA type.

〔第４の実施形態〕
本発明を好適に実施した第４の実施形態について説明する。
図１７に、本実施形態にかかるＢＧＡ型ＬＳＩパッケージ１の縦断面を示す。図１８に、本実施形態にかかるＢＧＡ型ＬＳＩパッケージの横断面を示す。
本実施形態にかかるＢＧＡ型ＬＳＩパッケージ１は、第１の実施形態とほぼ同様の構成であるが、リードフレーム１１は、基板６の上ではなく半導体チップ５上に設置されている。外部電極端子４とリードフレーム１１とはワイヤ８を介することなく電気的に接続されている。 [Fourth Embodiment]
A fourth embodiment in which the present invention is preferably implemented will be described.
FIG. 17 shows a longitudinal section of the BGA type LSI package 1 according to the present embodiment. FIG. 18 shows a cross section of the BGA type LSI package according to this embodiment.
The BGA type LSI package 1 according to the present embodiment has substantially the same configuration as that of the first embodiment, but the lead frame 11 is installed not on the substrate 6 but on the semiconductor chip 5. The external electrode terminal 4 and the lead frame 11 are electrically connected without using the wire 8.

本実施形態にかかるＢＧＡ型ＬＳＩパッケージ１は、第３の実施形態と同様の効果が得られる。しかも、外部電極端子４とリードフレーム１１とをワイヤボンディングする必要がないため、製造がより容易である。すなわち、ワイヤボンディングの手間を軽減できるのみならず、リードフレームの上端部を折り曲げる必要もない。よって、リードフレーム１１を最初から略コの字形状にしておいて半導体チップ５の上に設置しても良いし、側面視略工の字形状などとすることも可能である。   The BGA type LSI package 1 according to this embodiment can obtain the same effects as those of the third embodiment. In addition, since there is no need to wire bond the external electrode terminal 4 and the lead frame 11, manufacturing is easier. That is, not only can the labor of wire bonding be reduced, but there is no need to bend the upper end of the lead frame. Therefore, the lead frame 11 may be formed in a substantially U shape from the beginning and installed on the semiconductor chip 5, or may have a substantially U shape in side view.

なお、上記各実施形態は本発明の好適な実施の一例であり、本発明はこれらに限定されることはない。
例えば、上記各実施形態においては、ＢＧＡ型のＬＳＩパッケージを例として説明したが、ＦＱＰ型のＬＳＩパッケージの上面に外部電極端子を設け、ここから内部信号を出力可能としても良い。この場合にも、内部信号の信号波形を容易かつ正確に観測できるという効果が得られる。
また、上記各実施形態においては、全てのリードフレームを基板又は半導体チップの上に設置する構成を例としたが、一部のリードフレームを基板上に設置し、残りの一部を半導体チップ上に設置するようにしても良い。
このように、本発明は様々な変形が可能である。 Each of the above embodiments is an example of a preferred embodiment of the present invention, and the present invention is not limited to these.
For example, in each of the above embodiments, the BGA type LSI package has been described as an example. However, an external electrode terminal may be provided on the upper surface of the FQP type LSI package so that an internal signal can be output therefrom. Also in this case, the effect that the signal waveform of the internal signal can be observed easily and accurately is obtained.
Further, in each of the above embodiments, the configuration in which all the lead frames are installed on the substrate or the semiconductor chip is taken as an example. However, a part of the lead frames is installed on the substrate and the remaining part is placed on the semiconductor chip. You may make it install in.
As described above, the present invention can be variously modified.

本発明を好適に実施した第１の実施形態にかかるＢＧＡ型ＬＳＩパッケージの外観を示す図である。1 is a diagram showing an external appearance of a BGA type LSI package according to a first embodiment in which the present invention is preferably implemented. 第１の実施形態にかかるＢＧＡ型ＬＳＩパッケージの縦断面を示す図である。It is a figure which shows the longitudinal cross-section of the BGA type LSI package concerning 1st Embodiment. 第１の実施形態にかかるＢＧＡ型ＬＳＩパッケージの横断面を示す図である。It is a figure which shows the cross section of the BGA type LSI package concerning 1st Embodiment. 第１の実施形態にかかるＢＧＡ型ＬＳＩパッケージの機能構成を示す図である。It is a figure which shows the function structure of the BGA type | mold LSI package concerning 1st Embodiment. ＢＧＡ型ＬＳＩパッケージの上面の外部電極端子に測定器のプローブを接触させた状態を示す図である。It is a figure which shows the state which made the probe of a measuring device contact the external electrode terminal of the upper surface of a BGA type | mold LSI package. 基板上に半導体チップを搭載し、ワイヤボンディングを行った状態を示す図である。It is a figure which shows the state which mounted the semiconductor chip on the board | substrate and performed wire bonding. 半導体チップを搭載した基板にリードフレームを取り付け、ワイヤボンディングした状態を示す図である。It is a figure which shows the state which attached the lead frame to the board | substrate which mounted the semiconductor chip, and was wire-bonded. 半導体チップ上を樹脂で封止し、リードフレームの上端近傍を折り曲げた状態を示す図である。It is a figure which shows the state which sealed the semiconductor chip top with resin and bent the upper end vicinity of the lead frame. リードフレームの上端部にはんだボールを設置する状態示す図である。It is a figure which shows the state which installs a solder ball in the upper end part of a lead frame. 外部電極端子の上に絶縁層を形成した状態を示す図である。It is a figure which shows the state which formed the insulating layer on the external electrode terminal. 本発明を好適に実施した第２の実施形態にかかるＢＧＡ型ＬＳＩパッケージの縦断面を示す図である。It is a figure which shows the longitudinal cross-section of the BGA type | mold LSI package concerning 2nd Embodiment which implemented this invention suitably. 第２の実施形態にかかるＢＧＡ型ＬＳＩパッケージの機能構成を示す図である。It is a figure which shows the function structure of the BGA type | mold LSI package concerning 2nd Embodiment. 本発明を好適に実施した第３の実施形態にかかるＢＧＡ型ＬＳＩパッケージの縦断面を示す図である。It is a figure which shows the longitudinal cross-section of the BGA type | mold LSI package concerning 3rd Embodiment which implemented this invention suitably. 第３の実施形態にかかるＢＧＡ型ＬＳＩパッケージの横断面を示す図である。It is a figure which shows the cross section of the BGA type | mold LSI package concerning 3rd Embodiment. 本発明を好適に実施した第４の実施形態にかかるＢＧＡ型ＬＳＩパッケージの縦断面を示す図である。It is a figure which shows the longitudinal cross-section of the BGA type | mold LSI package concerning 4th Embodiment which implemented this invention suitably. 第４の実施形態にかかるＢＧＡ形ＬＳＩパッケージの横断面を示す図である。It is a figure which shows the cross section of the BGA type LSI package concerning 4th Embodiment. 従来のＢＧＡ型ＬＳＩパッケージの外観を示す図である。It is a figure which shows the external appearance of the conventional BGA type | mold LSI package. 従来のＢＧＡ型ＬＳＩパッケージの縦断面を示す図である。It is a figure which shows the longitudinal cross-section of the conventional BGA type | mold LSI package.

符号の説明Explanation of symbols

１ ＢＧＡ型ＬＳＩパッケージ
２ 樹脂
３、４ 外部電極端子
５、５ａ、５ｂ 半導体チップ
６ 基板
７、９ 電極端子
８ ワイヤ
１０ 内部配線
１１ リードフレーム DESCRIPTION OF SYMBOLS 1 BGA type LSI package 2 Resin 3, 4 External electrode terminal 5, 5a, 5b Semiconductor chip 6 Substrate 7, 9 Electrode terminal 8 Wire 10 Internal wiring 11 Lead frame

Claims (9)

一方の面に半導体チップが搭載された基板の該半導体チップが搭載された側の面を樹脂によって封止した半導体装置であって、
前記半導体チップは、内部信号を出力するため、又は該内部信号を出力するために必要な信号を入力するための第１の内部電極端子と、半導体チップとしての機能を実現するための動作信号を出力するため、又は該動作信号を出力するために必要な信号を入力するための第２の内部電極端子とを前記基板との接合面とは異なる面に備え、
前記第１の内部電極端子は、前記基板上に設置された導電性部材と該基板内部の配線を介することなく電気的に接続されており、
前記第２の内部電極端子は、前記基板上に設置された基板電極端子とワイヤを介して接続され、前記基板に設けられた外部電極端子とは該基板内部の配線を介して電気的に接続されており、
前記導電性部材は、前記樹脂を貫通しており、上端部には内部検査用電極端子が設けられていることを特徴とする半導体装置。 A semiconductor device in which a surface on which a semiconductor chip is mounted on a surface on which a semiconductor chip is mounted is sealed with resin.
The semiconductor chip outputs a first internal electrode terminal for inputting an internal signal or inputting a signal necessary for outputting the internal signal, and an operation signal for realizing a function as the semiconductor chip. A second internal electrode terminal for inputting a signal necessary for outputting or outputting the operation signal is provided on a surface different from a bonding surface with the substrate,
The first internal electrode terminal is electrically connected to the conductive member installed on the substrate without going through the wiring inside the substrate,
The second internal electrode terminal is connected to a substrate electrode terminal installed on the substrate via a wire, and is electrically connected to an external electrode terminal provided on the substrate via a wiring inside the substrate. Has been
The semiconductor device according to claim 1, wherein the conductive member penetrates the resin, and an upper end portion is provided with an internal inspection electrode terminal. 一方の面に半導体チップが搭載された基板の該半導体チップが搭載された側の面を樹脂によって封止した半導体装置であって、
前記半導体チップは、内部信号を出力するため、又は該内部信号を出力するために必要な信号を入力するための第１の内部電極端子と、半導体チップとしての機能を実現するための動作信号を出力するため、又は該動作信号を出力するために必要な信号を入力するための第２の内部電極端子とを前記基板との接合面とは異なる面に備え、
前記第１の内部電極端子は、前記半導体チップ上に設置された導電性部材と前記基板を介することなく電気的に接続されており、
前記第２の内部電極端子は、前記基板上に設置された基板電極端子とワイヤを介して接続され、前記基板に設けられた外部電極端子とは該基板内部の配線を介して電気的に接続されており、
前記導電性部材は、前記樹脂を貫通しており、上端部には内部検査用電極端子が設けられていることを特徴とする半導体装置。 A semiconductor device in which a surface on which a semiconductor chip is mounted on a surface on which a semiconductor chip is mounted is sealed with resin.
The semiconductor chip outputs a first internal electrode terminal for inputting an internal signal or a signal necessary for outputting the internal signal, and an operation signal for realizing a function as a semiconductor chip. A second internal electrode terminal for inputting a signal necessary for outputting or outputting the operation signal is provided on a surface different from a bonding surface with the substrate,
The first internal electrode terminal is electrically connected to the conductive member installed on the semiconductor chip without passing through the substrate,
The second internal electrode terminal is connected to a substrate electrode terminal installed on the substrate via a wire, and is electrically connected to an external electrode terminal provided on the substrate via a wiring inside the substrate. Has been
The semiconductor device according to claim 1, wherein the conductive member penetrates the resin, and an upper end portion is provided with an internal inspection electrode terminal. 前記導電性部材が前記第１の内部電極端子の上に設置されたことを特徴とする請求項２記載の半導体装置。   The semiconductor device according to claim 2, wherein the conductive member is disposed on the first internal electrode terminal. 前記導電性部材と前記第１の内部電極端子とがワイヤボンディングによって接続されたことを特徴とする請求項１又は２記載の半導体装置。   The semiconductor device according to claim 1, wherein the conductive member and the first internal electrode terminal are connected by wire bonding. 前記導電性部材は、帯状の部材が側面視略Ｌ字形状に折り曲げられて所定の位置に設置され、前記内部電極端子とワイヤボンディングされた後で前記上端部がさらに折り曲げられて側面視略コの字形状に成型されていることを特徴とする請求項４記載の半導体装置。   The conductive member is formed by bending a belt-like member into a substantially L shape when viewed from the side and installing it at a predetermined position. After the wire bonding with the internal electrode terminal, the upper end portion is further bent and the shape of the conductive member is substantially reduced. The semiconductor device according to claim 4, wherein the semiconductor device is molded into a letter-shape. 前記外部電極端子の上に絶縁層が剥離可能に形成されていることを特徴とする請求項１から５のいずれか１項記載の半導体装置。   6. The semiconductor device according to claim 1, wherein an insulating layer is detachably formed on the external electrode terminal. 前記外部電極端子は、球状であり、前記基板の前記樹脂によって封止されていない側の面に形成されたＢＧＡ型であることを特報とする請求項１から６のいずれか１項記載の半導体装置。   7. The semiconductor according to claim 1, wherein the external electrode terminal has a spherical shape and is a BGA type formed on a surface of the substrate that is not sealed by the resin. 8. apparatus. 前記外部電極端子は針状であり、前記基板の前記樹脂によって封止されていない側の面に形成されたＰＧＡ型であることを特報とする請求項１から６のいずれか１項記載の半導体装置。   7. The semiconductor according to claim 1, wherein the external electrode terminal has a needle shape and is a PGA type formed on a surface of the substrate that is not sealed by the resin. 8. apparatus. 前記基板が、側面に前記外部電極端子を備えることを特徴とする請求項１から６のいずれか１項記載の半導体装置。   The semiconductor device according to claim 1, wherein the substrate includes the external electrode terminal on a side surface.
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