TW419661B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- TW419661B TW419661B TW088103961A TW88103961A TW419661B TW 419661 B TW419661 B TW 419661B TW 088103961 A TW088103961 A TW 088103961A TW 88103961 A TW88103961 A TW 88103961A TW 419661 B TW419661 B TW 419661B
- Authority
- TW
- Taiwan
- Prior art keywords
- voltage
- power supply
- memory
- mentioned
- circuit
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 230000015654 memory Effects 0.000 claims abstract description 205
- 230000004913 activation Effects 0.000 claims abstract description 52
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- 238000003860 storage Methods 0.000 claims description 38
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- 238000003199 nucleic acid amplification method Methods 0.000 claims description 3
- 210000004027 cell Anatomy 0.000 claims 29
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 claims 9
- 239000004020 conductor Substances 0.000 claims 2
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- 229910052797 bismuth Inorganic materials 0.000 claims 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 210000000352 storage cell Anatomy 0.000 claims 1
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- 102100021568 B-cell scaffold protein with ankyrin repeats Human genes 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000008832 zhongfu Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40618—Refresh operations over multiple banks or interleaving
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2227—Standby or low power modes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4067—Refresh in standby or low power modes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4068—Voltage or leakage in refresh operations
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09869498A JP4017248B2 (ja) | 1998-04-10 | 1998-04-10 | 半導体装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW419661B true TW419661B (en) | 2001-01-21 |
Family
ID=14226622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW088103961A TW419661B (en) | 1998-04-10 | 1999-03-15 | Semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| US (11) | US6195306B1 (enExample) |
| JP (1) | JP4017248B2 (enExample) |
| KR (3) | KR100583338B1 (enExample) |
| TW (1) | TW419661B (enExample) |
Families Citing this family (124)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3853513B2 (ja) | 1998-04-09 | 2006-12-06 | エルピーダメモリ株式会社 | ダイナミック型ｒａｍ |
| JP4017248B2 (ja) * | 1998-04-10 | 2007-12-05 | 株式会社日立製作所 | 半導体装置 |
| JP2000243085A (ja) * | 1999-02-22 | 2000-09-08 | Hitachi Ltd | 半導体装置 |
| US6535415B2 (en) | 1999-02-22 | 2003-03-18 | Hitachi, Ltd. | Semiconductor device |
| JP3319429B2 (ja) * | 1999-04-23 | 2002-09-03 | 日本電気株式会社 | 半導体記憶装置 |
| JP4034923B2 (ja) * | 1999-05-07 | 2008-01-16 | 富士通株式会社 | 半導体記憶装置の動作制御方法および半導体記憶装置 |
| DE19934723A1 (de) * | 1999-07-23 | 2001-02-01 | Infineon Technologies Ag | Steuerbare Stromquellenschaltung und hiermit ausgestatteter Phasenregelkreis |
| JP2001211640A (ja) * | 2000-01-20 | 2001-08-03 | Hitachi Ltd | 電子装置と半導体集積回路及び情報処理システム |
| TW527601B (en) * | 2000-01-31 | 2003-04-11 | Fujitsu Ltd | Internal supply voltage generating circuit in a semiconductor memory device and method for controlling the same |
| JP4804609B2 (ja) * | 2000-02-16 | 2011-11-02 | 富士通セミコンダクター株式会社 | セルアレイ電源の上昇を防止したメモリ回路 |
| JP4485637B2 (ja) * | 2000-02-24 | 2010-06-23 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置及び半導体装置の内部電源生成方法 |
| US6477108B2 (en) | 2000-09-01 | 2002-11-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including memory with reduced current consumption |
| KR100353538B1 (ko) * | 2000-10-24 | 2002-09-27 | 주식회사 하이닉스반도체 | 반도체 장치의 전압 발생 조절 회로 |
| KR100380409B1 (ko) * | 2001-01-18 | 2003-04-11 | 삼성전자주식회사 | 반도체 메모리 소자의 패드배열구조 및 그의 구동방법 |
| KR100396897B1 (ko) * | 2001-08-14 | 2003-09-02 | 삼성전자주식회사 | 페리(ｐｅｒｉ)용 전압 발생 회로와 이를 구비하는 반도체메모리 장치 및 전압 발생 방법 |
| KR100403343B1 (ko) * | 2001-09-13 | 2003-11-01 | 주식회사 하이닉스반도체 | 램버스 디램 |
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| JP2003100075A (ja) * | 2001-09-25 | 2003-04-04 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP2003273245A (ja) * | 2002-03-15 | 2003-09-26 | Hitachi Ltd | 半導体記憶装置 |
| KR100437463B1 (ko) * | 2002-07-18 | 2004-06-23 | 삼성전자주식회사 | 반도체 메모리 장치 내부전원전압발생기를 제어하는 회로및 방법 |
| KR100437468B1 (ko) * | 2002-07-26 | 2004-06-23 | 삼성전자주식회사 | 9의 배수가 되는 데이터 입출력 구조를 반도체 메모리 장치 |
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| KR100558475B1 (ko) * | 2003-04-16 | 2006-03-07 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 배치 방법 |
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| US20070177445A1 (en) | 2007-08-02 |
| US7082074B2 (en) | 2006-07-25 |
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| KR20040044421A (ko) | 2004-05-28 |
| JP4017248B2 (ja) | 2007-12-05 |
| US20060250876A1 (en) | 2006-11-09 |
| US20010001262A1 (en) | 2001-05-17 |
| US6195306B1 (en) | 2001-02-27 |
| US7072202B2 (en) | 2006-07-04 |
| US6680875B2 (en) | 2004-01-20 |
| US7688670B2 (en) | 2010-03-30 |
| JPH11297071A (ja) | 1999-10-29 |
| KR100583337B1 (ko) | 2006-05-25 |
| KR100590640B1 (ko) | 2006-06-19 |
| US20040109383A1 (en) | 2004-06-10 |
| US20050231991A1 (en) | 2005-10-20 |
| US6870790B2 (en) | 2005-03-22 |
| KR100583338B1 (ko) | 2006-05-25 |
| US7411856B2 (en) | 2008-08-12 |
| US20050249017A1 (en) | 2005-11-10 |
| US7411855B2 (en) | 2008-08-12 |
| US20070183247A1 (en) | 2007-08-09 |
| US20010008497A1 (en) | 2001-07-19 |
| US7298662B2 (en) | 2007-11-20 |
| US20080273413A1 (en) | 2008-11-06 |
| US20030039158A1 (en) | 2003-02-27 |
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