JP4017248B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
JP4017248B2
JP4017248B2 JP09869498A JP9869498A JP4017248B2 JP 4017248 B2 JP4017248 B2 JP 4017248B2 JP 09869498 A JP09869498 A JP 09869498A JP 9869498 A JP9869498 A JP 9869498A JP 4017248 B2 JP4017248 B2 JP 4017248B2
Authority
JP
Japan
Prior art keywords
voltage
power supply
command
memory
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP09869498A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11297071A (ja
JPH11297071A5 (enExample
Inventor
真志 堀口
正行 中村
禎幸 大熊
一彦 梶谷
儀延 中込
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP09869498A priority Critical patent/JP4017248B2/ja
Priority to TW088103961A priority patent/TW419661B/zh
Priority to KR1019990012711A priority patent/KR100583338B1/ko
Priority to US09/289,660 priority patent/US6195306B1/en
Publication of JPH11297071A publication Critical patent/JPH11297071A/ja
Priority to US09/759,244 priority patent/US20010008497A1/en
Priority to US09/759,897 priority patent/US20010001262A1/en
Priority to US10/259,579 priority patent/US6680875B2/en
Priority to US10/724,781 priority patent/US6870790B2/en
Priority to KR1020040024692A priority patent/KR100590640B1/ko
Priority to KR1020040024693A priority patent/KR100583337B1/ko
Publication of JPH11297071A5 publication Critical patent/JPH11297071A5/ja
Priority to US11/084,138 priority patent/US7072202B2/en
Priority to US11/183,802 priority patent/US7082074B2/en
Priority to US11/483,649 priority patent/US7298662B2/en
Priority to US11/727,430 priority patent/US7411856B2/en
Priority to US11/727,429 priority patent/US7411855B2/en
Application granted granted Critical
Publication of JP4017248B2 publication Critical patent/JP4017248B2/ja
Priority to US12/165,681 priority patent/US7688670B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4067—Refresh in standby or low power modes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4068—Voltage or leakage in refresh operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
JP09869498A 1998-04-10 1998-04-10 半導体装置 Expired - Lifetime JP4017248B2 (ja)

Priority Applications (16)

Application Number Priority Date Filing Date Title
JP09869498A JP4017248B2 (ja) 1998-04-10 1998-04-10 半導体装置
TW088103961A TW419661B (en) 1998-04-10 1999-03-15 Semiconductor device
KR1019990012711A KR100583338B1 (ko) 1998-04-10 1999-04-10 반도체 장치
US09/289,660 US6195306B1 (en) 1998-04-10 1999-04-12 Semiconductor device
US09/759,244 US20010008497A1 (en) 1998-04-10 2001-01-16 Semiconductor device
US09/759,897 US20010001262A1 (en) 1998-04-10 2001-01-16 Semiconductor device
US10/259,579 US6680875B2 (en) 1998-04-10 2002-09-30 Semiconductor device, such as a synchronous DRAM, including a control circuit for reducing power consumption
US10/724,781 US6870790B2 (en) 1998-04-10 2003-12-02 Semiconductor device having a power down mode
KR1020040024692A KR100590640B1 (ko) 1998-04-10 2004-04-10 반도체 장치
KR1020040024693A KR100583337B1 (ko) 1998-04-10 2004-04-10 반도체 장치
US11/084,138 US7072202B2 (en) 1998-04-10 2005-03-21 Semiconductor device having a power down mode
US11/183,802 US7082074B2 (en) 1998-04-10 2005-07-19 Semiconductor device having a power down mode
US11/483,649 US7298662B2 (en) 1998-04-10 2006-07-11 Semiconductor device with power down arrangement for reduce power consumption
US11/727,430 US7411856B2 (en) 1998-04-10 2007-03-27 Semiconductor device with improved power supply arrangement
US11/727,429 US7411855B2 (en) 1998-04-10 2007-03-27 Semiconductor device with improved power supply arrangement
US12/165,681 US7688670B2 (en) 1998-04-10 2008-07-01 Semiconductor device with improved power supply control for a plurality of memory arrays

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP09869498A JP4017248B2 (ja) 1998-04-10 1998-04-10 半導体装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2004112617A Division JP4050717B2 (ja) 2004-04-07 2004-04-07 半導体装置
JP2004112616A Division JP4026772B2 (ja) 2004-04-07 2004-04-07 Ｄｒａｍ

Publications (3)

Publication Number Publication Date
JPH11297071A JPH11297071A (ja) 1999-10-29
JPH11297071A5 JPH11297071A5 (enExample) 2005-02-17
JP4017248B2 true JP4017248B2 (ja) 2007-12-05

Family

ID=14226622

Family Applications (1)

Application Number Title Priority Date Filing Date
JP09869498A Expired - Lifetime JP4017248B2 (ja) 1998-04-10 1998-04-10 半導体装置

Country Status (4)

Country Link
US (11) US6195306B1 (enExample)
JP (1) JP4017248B2 (enExample)
KR (3) KR100583338B1 (enExample)
TW (1) TW419661B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9793092B2 (en) 2014-01-22 2017-10-17 Hitachi High-Tech Science Corporation Charged particle beam apparatus and processing method

Families Citing this family (123)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3853513B2 (ja) 1998-04-09 2006-12-06 エルピーダメモリ株式会社 ダイナミック型ｒａｍ
JP4017248B2 (ja) * 1998-04-10 2007-12-05 株式会社日立製作所 半導体装置
JP2000243085A (ja) * 1999-02-22 2000-09-08 Hitachi Ltd 半導体装置
US6535415B2 (en) 1999-02-22 2003-03-18 Hitachi, Ltd. Semiconductor device
JP3319429B2 (ja) * 1999-04-23 2002-09-03 日本電気株式会社 半導体記憶装置
JP4034923B2 (ja) * 1999-05-07 2008-01-16 富士通株式会社 半導体記憶装置の動作制御方法および半導体記憶装置
DE19934723A1 (de) * 1999-07-23 2001-02-01 Infineon Technologies Ag Steuerbare Stromquellenschaltung und hiermit ausgestatteter Phasenregelkreis
JP2001211640A (ja) * 2000-01-20 2001-08-03 Hitachi Ltd 電子装置と半導体集積回路及び情報処理システム
TW527601B (en) * 2000-01-31 2003-04-11 Fujitsu Ltd Internal supply voltage generating circuit in a semiconductor memory device and method for controlling the same
JP4804609B2 (ja) * 2000-02-16 2011-11-02 富士通セミコンダクター株式会社 セルアレイ電源の上昇を防止したメモリ回路
JP4485637B2 (ja) * 2000-02-24 2010-06-23 富士通マイクロエレクトロニクス株式会社 半導体装置及び半導体装置の内部電源生成方法
US6477108B2 (en) 2000-09-01 2002-11-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including memory with reduced current consumption
KR100353538B1 (ko) * 2000-10-24 2002-09-27 주식회사 하이닉스반도체 반도체 장치의 전압 발생 조절 회로
KR100380409B1 (ko) * 2001-01-18 2003-04-11 삼성전자주식회사 반도체 메모리 소자의 패드배열구조 및 그의 구동방법
KR100396897B1 (ko) * 2001-08-14 2003-09-02 삼성전자주식회사 페리(ｐｅｒｉ)용 전압 발생 회로와 이를 구비하는 반도체메모리 장치 및 전압 발생 방법
KR100403343B1 (ko) * 2001-09-13 2003-11-01 주식회사 하이닉스반도체 램버스 디램
JP2003099414A (ja) * 2001-09-21 2003-04-04 Mitsubishi Electric Corp 半導体集積回路
JP2003100075A (ja) * 2001-09-25 2003-04-04 Mitsubishi Electric Corp 半導体記憶装置
JP2003273245A (ja) * 2002-03-15 2003-09-26 Hitachi Ltd 半導体記憶装置
KR100437463B1 (ko) * 2002-07-18 2004-06-23 삼성전자주식회사 반도체 메모리 장치 내부전원전압발생기를 제어하는 회로및 방법
KR100437468B1 (ko) * 2002-07-26 2004-06-23 삼성전자주식회사 9의 배수가 되는 데이터 입출력 구조를 반도체 메모리 장치
US6962399B2 (en) * 2002-12-30 2005-11-08 Lexmark International, Inc. Method of warning a user of end of life of a consumable for an ink jet printer
KR100558475B1 (ko) * 2003-04-16 2006-03-07 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 배치 방법
US7177981B2 (en) * 2003-05-09 2007-02-13 Via-Cyrix, Inc. Method and system for cache power reduction
JP2005005622A (ja) * 2003-06-13 2005-01-06 Toyota Industries Corp リミッタ回路及びその半導体集積回路
US7030664B2 (en) * 2003-06-30 2006-04-18 Sun Microsystems, Inc. Half-rail differential driver circuit
JP2005092963A (ja) * 2003-09-16 2005-04-07 Renesas Technology Corp 不揮発性記憶装置
US6862238B1 (en) * 2003-09-25 2005-03-01 Infineon Technologies Ag Memory system with reduced refresh current
KR100560297B1 (ko) * 2003-10-29 2006-03-10 주식회사 하이닉스반도체 지연고정루프용 전원 공급 회로를 구비한 반도체 소자
JP4632114B2 (ja) * 2003-11-25 2011-02-16 エルピーダメモリ株式会社 半導体集積回路装置
DE102004004785A1 (de) * 2004-01-30 2005-08-25 Infineon Technologies Ag Spannungs-Pumpen-Anordnung für Halbleiter-Bauelemente
JP2005222315A (ja) * 2004-02-05 2005-08-18 Sony Corp 不揮発性メモリ制御方法および装置
DE102004047764B4 (de) * 2004-09-30 2006-08-10 Infineon Technologies Ag Speicheranordnung, Verfahren zum Betrieb und Verwendung einer solchen
US7257678B2 (en) * 2004-10-01 2007-08-14 Advanced Micro Devices, Inc. Dynamic reconfiguration of cache memory
US7158434B2 (en) * 2005-04-29 2007-01-02 Infineon Technologies, Ag Self-refresh circuit with optimized power consumption
JP4746038B2 (ja) 2005-06-08 2011-08-10 富士通セミコンダクター株式会社 半導体記憶装置および電子機器
US7609567B2 (en) * 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US7590796B2 (en) * 2006-07-31 2009-09-15 Metaram, Inc. System and method for power management in memory systems
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US7392338B2 (en) * 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US7386656B2 (en) * 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US7472220B2 (en) * 2006-07-31 2008-12-30 Metaram, Inc. Interface circuit system and method for performing power management operations utilizing power management signals
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8090897B2 (en) * 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US9542352B2 (en) * 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
WO2007002324A2 (en) * 2005-06-24 2007-01-04 Metaram, Inc. An integrated memory core and memory interface circuit
US8077535B2 (en) * 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US7580312B2 (en) * 2006-07-31 2009-08-25 Metaram, Inc. Power saving system and method for use with a plurality of memory circuits
KR100725362B1 (ko) 2005-07-11 2007-06-07 삼성전자주식회사 동적 메모리 장치 및 이를 포함하는 통신 단말기
KR100729356B1 (ko) * 2005-08-23 2007-06-15 삼성전자주식회사 플래시 메모리 장치의 레이아웃 구조
DE112006002300B4 (de) * 2005-09-02 2013-12-19 Google, Inc. Vorrichtung zum Stapeln von DRAMs
JP2007095075A (ja) * 2005-09-29 2007-04-12 Hynix Semiconductor Inc 内部電圧生成装置
KR100715147B1 (ko) * 2005-10-06 2007-05-10 삼성전자주식회사 전류소모를 감소시키는 내부전원전압 발생회로를 가지는멀티칩 반도체 메모리 장치
KR100642395B1 (ko) * 2005-10-12 2006-11-10 주식회사 하이닉스반도체 반도체 장치
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US7555659B2 (en) * 2006-02-28 2009-06-30 Mosaid Technologies Incorporated Low power memory architecture
KR100715525B1 (ko) 2006-03-28 2007-05-04 엠텍비젼 주식회사 독립적인 입출력 파워와 클럭을 가지는 다중 포트 메모리장치
KR100886628B1 (ko) * 2006-05-10 2009-03-04 주식회사 하이닉스반도체 반도체 장치의 내부전압 생성회로
US7440354B2 (en) * 2006-05-15 2008-10-21 Freescale Semiconductor, Inc. Memory with level shifting word line driver and method thereof
JP5261888B2 (ja) * 2006-05-18 2013-08-14 富士通セミコンダクター株式会社 半導体記憶装置
US20080028137A1 (en) * 2006-07-31 2008-01-31 Schakel Keith R Method and Apparatus For Refresh Management of Memory Modules
US20080025136A1 (en) * 2006-07-31 2008-01-31 Metaram, Inc. System and method for storing at least a portion of information received in association with a first operation for use in performing a second operation
US20080028135A1 (en) * 2006-07-31 2008-01-31 Metaram, Inc. Multiple-component memory interface system and method
US7724589B2 (en) * 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
KR100826649B1 (ko) * 2006-11-24 2008-05-06 주식회사 하이닉스반도체 딥 파워다운 모드 제어 회로
US7900018B2 (en) 2006-12-05 2011-03-01 Electronics And Telecommunications Research Institute Embedded system and page relocation method therefor
KR100941977B1 (ko) * 2006-12-05 2010-02-12 한국전자통신연구원 임베디드 시스템 및 그를 위한 페이지 재배치 방법
KR100818103B1 (ko) * 2006-12-15 2008-04-01 주식회사 하이닉스반도체 전압 제어 회로와 전압 제어 방법 및 전압 제어 회로를포함하는 반도체 메모리 장치
JP2008159145A (ja) * 2006-12-22 2008-07-10 Elpida Memory Inc 半導体記憶装置
JP2008159128A (ja) * 2006-12-22 2008-07-10 Elpida Memory Inc 半導体記憶装置
KR100872165B1 (ko) * 2006-12-28 2008-12-09 삼성전자주식회사 저항체를 이용한 비휘발성 메모리 장치
EP1953762B1 (en) * 2007-01-25 2013-09-18 Imec Memory device with reduced standby power consumption and method for operating same
KR100849224B1 (ko) * 2007-02-01 2008-07-31 삼성전자주식회사 메모리 카드 시스템의 메모리 카드에 전원을 공급하는 방법및 메모리 카드 시스템
US8209479B2 (en) * 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
JP2009038306A (ja) * 2007-08-03 2009-02-19 Elpida Memory Inc 半導体記憶装置
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
KR101450255B1 (ko) * 2008-10-22 2014-10-13 삼성전자주식회사 반도체 메모리 장치의 내부 전원 전압 발생 회로
KR100956786B1 (ko) * 2008-11-12 2010-05-12 주식회사 하이닉스반도체 반도체 메모리 장치
JP5246123B2 (ja) * 2009-01-29 2013-07-24 富士通セミコンダクター株式会社 半導体記憶装置、半導体装置及び電子機器
JP2010192013A (ja) * 2009-02-16 2010-09-02 Panasonic Corp 半導体集積回路
JP2010257528A (ja) * 2009-04-24 2010-11-11 Toshiba Corp 半導体集積回路装置
KR101608218B1 (ko) * 2009-05-29 2016-04-01 삼성전자주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
DE202010017690U1 (de) * 2009-06-09 2012-05-29 Google, Inc. Programmierung von Dimm-Abschlusswiderstandswerten
KR20110033611A (ko) 2009-09-25 2011-03-31 삼성전자주식회사 제어 모드에 따라 전원 발생부를 제어하는 멀티-채널 반도체 집적회로 장치 및 이를 포함하는 메모리 시스템
KR101620348B1 (ko) 2009-10-16 2016-05-12 삼성전자주식회사 내부전원 발생장치, 이를 구비한 멀티채널 메모리 장치 및 이를 채용한 프로세싱 시스템
KR101185553B1 (ko) * 2009-12-29 2012-09-24 에스케이하이닉스 주식회사 내부전압 제어회로
JP5706635B2 (ja) 2010-06-24 2015-04-22 ルネサスエレクトロニクス株式会社 半導体装置及びその内部回路の制御方法
US8422272B2 (en) 2010-08-06 2013-04-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
US8582348B2 (en) 2010-08-06 2013-11-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for driving semiconductor device
KR101157024B1 (ko) * 2010-09-03 2012-06-21 에스케이하이닉스 주식회사 반도체 집적 회로 장치
JP2012203807A (ja) * 2011-03-28 2012-10-22 Elpida Memory Inc メモリモジュール
KR102035612B1 (ko) * 2012-12-21 2019-10-24 에스케이하이닉스 주식회사 셀프 리프레쉬 제어 장치
US10034899B2 (en) 2013-11-27 2018-07-31 BioPharmX, Inc. Solid oral dosage form for breast symptoms
US9671855B2 (en) * 2014-06-30 2017-06-06 Micron Technology, Inc. Apparatuses and methods of entering unselected memories into a different power mode during multi-memory operation
KR20160029396A (ko) * 2014-09-05 2016-03-15 에스케이하이닉스 주식회사 반도체 메모리 장치
KR101619293B1 (ko) 2014-11-12 2016-05-11 현대오트론 주식회사 전원 반도체의 제어 방법 및 제어 장치
US20170206031A1 (en) 2016-01-15 2017-07-20 Samsung Electronics Co., Ltd. Fine grain level memory power consumption control mechanism
JP6802009B2 (ja) * 2016-08-29 2020-12-16 エルジー ディスプレイ カンパニー リミテッド 圧力検出装置及びその駆動方法
EP3901952B1 (en) 2016-10-31 2023-06-07 Intel Corporation Applying chip select for memory device identification and power management control
US10049719B1 (en) * 2017-06-12 2018-08-14 Nanya Technology Corporation Voltage system and method for operating the same
US10431291B1 (en) * 2018-08-08 2019-10-01 Micron Technology, Inc. Systems and methods for dynamic random access memory (DRAM) cell voltage boosting
US10998076B1 (en) * 2019-11-01 2021-05-04 Realtek Semiconductor Corporation Signal calibration method used in memory apparatus
KR20210093607A (ko) 2020-01-20 2021-07-28 삼성전자주식회사 메모리 장치의 워드라인 구동 회로 및 그것의 동작 방법
US12380940B2 (en) * 2022-06-21 2025-08-05 Changxin Memory Technologies, Inc. Semiconductor device
KR20240117196A (ko) 2023-01-25 2024-08-01 삼성전자주식회사 클럭 드라이버, 이의 동작 방법, 클럭 드라이버를 포함하는 메모리 장치, 및 메모리 시스템

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4781494A (en) * 1986-05-16 1988-11-01 Daymarc Corporation Air-assist accumulating and transfer unit for an electronic device test handler
US5179539A (en) * 1988-05-25 1993-01-12 Hitachi, Ltd., Hitachi Vlsi Engineering Corporation Large scale integrated circuit having low internal operating voltage
JPH03149876A (ja) 1989-11-07 1991-06-26 Hitachi Ltd 半導体集積回路装置
JP2758504B2 (ja) 1990-07-06 1998-05-28 松下電器産業株式会社 半導体記憶装置
KR100231393B1 (ko) * 1991-04-18 1999-11-15 나시모토 류조 반도체집적회로장치
JPH07105682A (ja) * 1993-10-06 1995-04-21 Nec Corp ダイナミックメモリ装置
JP3577112B2 (ja) 1994-09-08 2004-10-13 株式会社ルネサステクノロジ 同期型半導体記憶装置
KR0172333B1 (ko) * 1995-01-16 1999-03-30 김광호 반도체 메모리 장치의 전원 승압 회로
JPH08195083A (ja) 1995-01-17 1996-07-30 Toshiba Microelectron Corp 半導体記憶装置
JP3412064B2 (ja) 1995-09-04 2003-06-03 日本テキサス・インスツルメンツ株式会社 半導体装置及び半導体メモリ装置
JP3834103B2 (ja) 1995-10-06 2006-10-18 株式会社ルネサステクノロジ 半導体記憶装置
KR100200922B1 (ko) * 1995-12-27 1999-06-15 윤종용 반도체 메모리장치의 펌핑전압발생기
KR100234389B1 (ko) * 1996-09-13 1999-12-15 윤종용 전압 검출 회로
JP3319960B2 (ja) * 1996-10-17 2002-09-03 富士通株式会社 半導体装置
JPH10269800A (ja) * 1997-03-27 1998-10-09 Mitsubishi Electric Corp 半導体記憶装置
JP3235516B2 (ja) 1997-06-12 2001-12-04 日本電気株式会社 半導体集積回路
JP4017248B2 (ja) * 1998-04-10 2007-12-05 株式会社日立製作所 半導体装置
JP3149876B1 (ja) 2000-11-13 2001-03-26 スズキ株式会社 内燃機関のチェーンテンショナ装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9793092B2 (en) 2014-01-22 2017-10-17 Hitachi High-Tech Science Corporation Charged particle beam apparatus and processing method

Also Published As

Publication number Publication date
KR19990083120A (ko) 1999-11-25
US20070177445A1 (en) 2007-08-02
US7082074B2 (en) 2006-07-25
KR20040044420A (ko) 2004-05-28
KR20040044421A (ko) 2004-05-28
US20060250876A1 (en) 2006-11-09
US20010001262A1 (en) 2001-05-17
US6195306B1 (en) 2001-02-27
US7072202B2 (en) 2006-07-04
US6680875B2 (en) 2004-01-20
US7688670B2 (en) 2010-03-30
JPH11297071A (ja) 1999-10-29
KR100583337B1 (ko) 2006-05-25
KR100590640B1 (ko) 2006-06-19
US20040109383A1 (en) 2004-06-10
US20050231991A1 (en) 2005-10-20
US6870790B2 (en) 2005-03-22
KR100583338B1 (ko) 2006-05-25
US7411856B2 (en) 2008-08-12
US20050249017A1 (en) 2005-11-10
US7411855B2 (en) 2008-08-12
US20070183247A1 (en) 2007-08-09
US20010008497A1 (en) 2001-07-19
US7298662B2 (en) 2007-11-20
US20080273413A1 (en) 2008-11-06
US20030039158A1 (en) 2003-02-27
TW419661B (en) 2001-01-21

Similar Documents

Publication Publication Date Title
JP4017248B2 (ja) 半導体装置
US6115316A (en) Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type
US6804158B2 (en) Semiconductor circuit device with improved special mode
US6178108B1 (en) Semiconductor memory device
EP1039471B1 (en) Semiconductor integrated circuit and semiconductor memory device including overdriving sense amplifier
US7099234B2 (en) Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM
US6219292B1 (en) Semiconductor memory device having reduced power requirements during refresh operation by performing refresh operation in a burst method
US20110080797A1 (en) Semiconductor device having sense amplifiers
KR20040038055A (ko) 저전력 셀프 리프레쉬 장치를 구비한 반도체 메모리 장치
US5956281A (en) Semiconductor memory device capable of setting substrate voltage shallow in disturb test mode and self refresh mode
US6894942B2 (en) Refresh control circuit and method for semiconductor memory device
JP4805881B2 (ja) Ｄｒａｍチップ
JP4026772B2 (ja) Ｄｒａｍ
JP4050717B2 (ja) 半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040310

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040310

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20040310

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060525

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060721

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070125

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070326

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070913

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070918

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100928

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100928

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100928

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110928

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110928

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120928

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130928

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term