JP2009038306A - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP2009038306A JP2009038306A JP2007203316A JP2007203316A JP2009038306A JP 2009038306 A JP2009038306 A JP 2009038306A JP 2007203316 A JP2007203316 A JP 2007203316A JP 2007203316 A JP2007203316 A JP 2007203316A JP 2009038306 A JP2009038306 A JP 2009038306A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- sense amplifier
- supply line
- memory cell
- mats
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000010586 diagram Methods 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 230000004913 activation Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 241000608282 Sagiyama virus Species 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
Abstract
【解決手段】情報として電荷が蓄積される複数のメモリセルを備える、アレイ状に配置された複数のマット10と、一端が外部電源から供給される電圧を降圧または昇圧する内部電源に共通に接続された複数の電源線30とを有する半導体記憶装置であって、各電源線30は、複数のマット10が形成された領域上に、一定方向に延伸するように配線されており、各電源線30の他端が端マット10a上で共通に接続されている。
【選択図】図1
Description
12 容量素子
13 センスアンプ
10 マット
10a 端マット
20a、20b アレイ用電源配線領域
30 電源線
Claims (3)
- 情報として電荷が蓄積される複数のメモリセルを備える、アレイ状に配置された複数のマットと、
一端が外部電源から供給される電圧を降圧または昇圧する内部電源に共通に接続された複数の電源線と、を有し、
前記複数の電源線は、前記複数のマットが形成された領域上に、一定方向に延伸するように配線されており、該電源線の他端が、前記複数のマットのうちの前記一定方向において最も端に位置するマット上で共通に接続されている、ことを特徴とする、半導体記憶装置。 - 前記複数のマットのそれぞれは、前記複数のメモリセルから情報を読み出すための複数のセンスアンプを有し、
前記複数の電源線が、前記複数のセンスアンプに駆動電圧を供給する電源線である、請求項1に記載の半導体記憶装置。 - 前記端に位置するマット上に形成された電源線の幅が端以外のマット上に形成された電源線の幅より大きい、請求項1または2に記載の半導体記憶装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007203316A JP2009038306A (ja) | 2007-08-03 | 2007-08-03 | 半導体記憶装置 |
US12/222,105 US20090034353A1 (en) | 2007-08-03 | 2008-08-01 | Semiconductor memory device |
KR1020080075516A KR20090014111A (ko) | 2007-08-03 | 2008-08-01 | 반도체 메모리 디바이스 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007203316A JP2009038306A (ja) | 2007-08-03 | 2007-08-03 | 半導体記憶装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2009038306A true JP2009038306A (ja) | 2009-02-19 |
Family
ID=40337975
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007203316A Pending JP2009038306A (ja) | 2007-08-03 | 2007-08-03 | 半導体記憶装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20090034353A1 (ja) |
JP (1) | JP2009038306A (ja) |
KR (1) | KR20090014111A (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011146102A (ja) * | 2010-01-15 | 2011-07-28 | Elpida Memory Inc | 半導体装置及びデータ処理システム |
KR101788726B1 (ko) | 2010-11-26 | 2017-10-23 | 에스케이하이닉스 주식회사 | 쉴딩 패턴을 갖는 반도체 메모리 장치 |
KR102365683B1 (ko) | 2015-11-27 | 2022-02-21 | 삼성전자주식회사 | 디스플레이 구동 칩 |
KR20230060101A (ko) | 2021-10-27 | 2023-05-04 | 삼성전자주식회사 | 반도체 메모리 장치의 서브 워드라인 드라이버 회로 및 반도체 메모리 장치 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH117762A (ja) * | 1997-06-17 | 1999-01-12 | Hitachi Ltd | 半導体記憶装置 |
JPH1117135A (ja) * | 1997-06-20 | 1999-01-22 | Hitachi Ltd | 半導体集積回路 |
JP2000243085A (ja) * | 1999-02-22 | 2000-09-08 | Hitachi Ltd | 半導体装置 |
JP2000323672A (ja) * | 1999-05-11 | 2000-11-24 | Fujitsu Ltd | 半導体集積回路 |
JP2001118999A (ja) * | 1999-10-15 | 2001-04-27 | Hitachi Ltd | ダイナミック型ramと半導体装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4017248B2 (ja) * | 1998-04-10 | 2007-12-05 | 株式会社日立製作所 | 半導体装置 |
JP2003100075A (ja) * | 2001-09-25 | 2003-04-04 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP5688870B2 (ja) * | 2007-07-11 | 2015-03-25 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体記憶装置 |
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2007
- 2007-08-03 JP JP2007203316A patent/JP2009038306A/ja active Pending
-
2008
- 2008-08-01 US US12/222,105 patent/US20090034353A1/en not_active Abandoned
- 2008-08-01 KR KR1020080075516A patent/KR20090014111A/ko active IP Right Grant
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH117762A (ja) * | 1997-06-17 | 1999-01-12 | Hitachi Ltd | 半導体記憶装置 |
JPH1117135A (ja) * | 1997-06-20 | 1999-01-22 | Hitachi Ltd | 半導体集積回路 |
JP2000243085A (ja) * | 1999-02-22 | 2000-09-08 | Hitachi Ltd | 半導体装置 |
JP2000323672A (ja) * | 1999-05-11 | 2000-11-24 | Fujitsu Ltd | 半導体集積回路 |
JP2001118999A (ja) * | 1999-10-15 | 2001-04-27 | Hitachi Ltd | ダイナミック型ramと半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
KR20090014111A (ko) | 2009-02-06 |
US20090034353A1 (en) | 2009-02-05 |
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