CN1300801C - 半导体存储装置中执行部分阵列自更新操作的系统和方法 - Google Patents

半导体存储装置中执行部分阵列自更新操作的系统和方法 Download PDF

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Publication number
CN1300801C
CN1300801C CNB021020566A CN02102056A CN1300801C CN 1300801 C CN1300801 C CN 1300801C CN B021020566 A CNB021020566 A CN B021020566A CN 02102056 A CN02102056 A CN 02102056A CN 1300801 C CN1300801 C CN 1300801C
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signal
self
refresh
row address
period
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Chinese (zh)
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CN1384506A (zh
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黄炯烈
崔钟贤
张贤淳
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40622Partial refresh of memory arrays
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • G11C11/4087Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
CNB021020566A 2001-05-07 2002-01-18 半导体存储装置中执行部分阵列自更新操作的系统和方法 Expired - Lifetime CN1300801C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US28926401P 2001-05-07 2001-05-07
US60/289,264 2001-05-07
US09/925,812 US6590822B2 (en) 2001-05-07 2001-08-09 System and method for performing partial array self-refresh operation in a semiconductor memory device
US09/925,812 2001-08-09

Publications (2)

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CN1384506A CN1384506A (zh) 2002-12-11
CN1300801C true CN1300801C (zh) 2007-02-14

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US (3) US6590822B2 (US06819617-20041116-M00002.png)
EP (1) EP1256957A3 (US06819617-20041116-M00002.png)
JP (1) JP2002334576A (US06819617-20041116-M00002.png)
KR (1) KR100443909B1 (US06819617-20041116-M00002.png)
CN (1) CN1300801C (US06819617-20041116-M00002.png)
TW (1) TW564420B (US06819617-20041116-M00002.png)

Families Citing this family (107)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007071A (ja) * 2001-06-26 2003-01-10 Sharp Corp 半導体メモリ装置
US7426151B2 (en) * 2001-08-14 2008-09-16 Samung Electronics Co., Ltd. Device and method for performing a partial array refresh operation
KR100437610B1 (ko) * 2001-09-20 2004-06-30 주식회사 하이닉스반도체 정상 모드와 부분 어레이 셀프 리프레쉬 모드를 갖는저전력 반도체 메모리 장치
KR100425470B1 (ko) * 2001-11-06 2004-03-30 삼성전자주식회사 Dram 장치에서 리프레쉬 동작시의 잡음 피크를감소시키기 위한 부분 리프레쉬 방법 및 부분 리프레쉬 회로
US6618314B1 (en) * 2002-03-04 2003-09-09 Cypress Semiconductor Corp. Method and architecture for reducing the power consumption for memory devices in refresh operations
US6798711B2 (en) * 2002-03-19 2004-09-28 Micron Technology, Inc. Memory with address management
KR100506057B1 (ko) * 2002-07-15 2005-08-03 주식회사 하이닉스반도체 부분 어레이 셀프 리프레시를 수행하는 반도체 메모리 장치
KR100481923B1 (ko) * 2002-07-15 2005-04-13 주식회사 하이닉스반도체 반도체 메모리 장치
JP4246971B2 (ja) * 2002-07-15 2009-04-02 富士通マイクロエレクトロニクス株式会社 半導体メモリ
KR100535071B1 (ko) * 2002-11-07 2005-12-07 주식회사 하이닉스반도체 셀프 리프레쉬 장치
WO2004070729A1 (ja) * 2003-02-05 2004-08-19 Fujitsu Limited 半導体メモリ
KR100474551B1 (ko) * 2003-02-10 2005-03-10 주식회사 하이닉스반도체 셀프 리프레쉬 장치 및 방법
JP2004273029A (ja) * 2003-03-10 2004-09-30 Sony Corp 記憶装置およびそれに用いられるリフレッシュ制御回路ならびにリフレッシュ方法
US6940773B2 (en) * 2003-04-02 2005-09-06 Infineon Technologies Ag Method and system for manufacturing DRAMs with reduced self-refresh current requirements
KR100543914B1 (ko) * 2003-04-30 2006-01-23 주식회사 하이닉스반도체 리프레쉬 동작시 피크 전류를 줄일 수 있는 반도체 메모리장치
KR100621619B1 (ko) * 2003-11-14 2006-09-13 삼성전자주식회사 리플레쉬 동작을 수행하는 반도체 메모리 장치
US20050108460A1 (en) * 2003-11-14 2005-05-19 Intel Corporation Partial bank DRAM refresh
US7392339B2 (en) * 2003-12-10 2008-06-24 Intel Corporation Partial bank DRAM precharge
US6967885B2 (en) * 2004-01-15 2005-11-22 International Business Machines Corporation Concurrent refresh mode with distributed row address counters in an embedded DRAM
CN100520964C (zh) * 2004-03-11 2009-07-29 富士通微电子株式会社 半导体存储器
KR100611774B1 (ko) * 2004-06-03 2006-08-10 주식회사 하이닉스반도체 반도체 기억 소자의 뱅크 베이스드 부분 어레이 셀프 리프레쉬 장치 및 방법
KR100618858B1 (ko) * 2004-08-31 2006-08-31 삼성전자주식회사 리프레쉬 수행 시 리프레쉬 할 뱅크의 개수를 가변할 수있는 반도체 메모리 장치 및 그 리프레쉬 방법
KR100608370B1 (ko) * 2004-11-15 2006-08-08 주식회사 하이닉스반도체 메모리 장치의 리프레쉬 수행 방법
KR100666325B1 (ko) * 2004-12-15 2007-01-09 삼성전자주식회사 메모리 셀 어레이 블록 할당 방법, 메모리 셀 어레이블록의 어드레싱 방법 및 이를 이용한 반도체 메모리 장치
US7342841B2 (en) * 2004-12-21 2008-03-11 Intel Corporation Method, apparatus, and system for active refresh management
KR101102051B1 (ko) * 2005-01-03 2012-01-04 주식회사 하이닉스반도체 자동 부분 어레이 셀프 리프레쉬 장치
KR20060084071A (ko) * 2005-01-17 2006-07-24 삼성전자주식회사 반도체 메모리에서의 리프레쉬 제어회로 및 그에 따른제어방법
KR100610024B1 (ko) * 2005-01-27 2006-08-08 삼성전자주식회사 셀프 리프레쉬 모드를 가지는 반도체 메모리 장치 및 그의동작 방법
KR100642759B1 (ko) * 2005-01-28 2006-11-10 삼성전자주식회사 선택적 리프레쉬가 가능한 반도체 메모리 디바이스
US7158434B2 (en) * 2005-04-29 2007-01-02 Infineon Technologies, Ag Self-refresh circuit with optimized power consumption
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8169233B2 (en) 2009-06-09 2012-05-01 Google Inc. Programming of DIMM termination resistance values
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
KR101183684B1 (ko) * 2005-07-13 2012-10-18 삼성전자주식회사 디램 메모리 장치 및 부분 어레이 셀프 리프레시 방법
JP4428319B2 (ja) * 2005-08-30 2010-03-10 エルピーダメモリ株式会社 半導体記憶装置およびバンク・リフレッシュ方法
US7379316B2 (en) 2005-09-02 2008-05-27 Metaram, Inc. Methods and apparatus of stacking DRAMs
KR100733447B1 (ko) 2005-09-28 2007-06-29 주식회사 하이닉스반도체 누설전류 방지를 위한 메모리장치의 데이터 출력 멀티플렉서
US7457185B2 (en) * 2005-09-29 2008-11-25 Hynix Semiconductor Inc. Semiconductor memory device with advanced refresh control
WO2007083198A1 (en) * 2006-01-18 2007-07-26 Freescale Semiconductor Inc. Hardware accelerator based method and device for string searching
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
KR100810060B1 (ko) * 2006-04-14 2008-03-05 주식회사 하이닉스반도체 반도체 메모리 소자 및 그의 구동방법
US7492656B2 (en) * 2006-04-28 2009-02-17 Mosaid Technologies Incorporated Dynamic random access memory with fully independent partial array refresh function
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
JP4299849B2 (ja) * 2006-08-22 2009-07-22 エルピーダメモリ株式会社 半導体記憶装置及びそのリフレッシュ制御方法
KR20080029573A (ko) * 2006-09-29 2008-04-03 주식회사 하이닉스반도체 반도체 메모리 장치
JP4869011B2 (ja) * 2006-09-29 2012-02-01 富士通セミコンダクター株式会社 メモリシステム
KR100900784B1 (ko) * 2007-01-03 2009-06-02 주식회사 하이닉스반도체 반도체메모리소자
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
KR20090013342A (ko) * 2007-08-01 2009-02-05 삼성전자주식회사 멀티 포트 반도체 메모리 장치 및 그에 따른 리프레쉬 방법
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
KR100909630B1 (ko) 2007-11-02 2009-07-27 주식회사 하이닉스반도체 어드레스 카운터 회로
US7961541B2 (en) * 2007-12-12 2011-06-14 Zmos Technology, Inc. Memory device with self-refresh operations
KR100914294B1 (ko) * 2007-12-18 2009-08-27 주식회사 하이닉스반도체 오토 리프래쉬 제어 장치
KR100892729B1 (ko) * 2007-12-27 2009-04-10 주식회사 하이닉스반도체 반도체 집적 회로 및 그의 리프레시 방법
KR100914298B1 (ko) * 2007-12-28 2009-08-27 주식회사 하이닉스반도체 셀프리프레시 회로
US8095725B2 (en) * 2007-12-31 2012-01-10 Intel Corporation Device, system, and method of memory allocation
US7969807B2 (en) * 2008-03-05 2011-06-28 Qimonda Ag Memory that retains data when switching partial array self refresh settings
US7755967B2 (en) * 2008-09-29 2010-07-13 Qimonda North America Corp. Memory device refresh method and apparatus
JP5599977B2 (ja) * 2009-01-22 2014-10-01 ピーエスフォー ルクスコ エスエイアールエル 半導体記憶装置
US8468295B2 (en) * 2009-12-02 2013-06-18 Dell Products L.P. System and method for reducing power consumption of memory
KR20110093086A (ko) * 2010-02-11 2011-08-18 삼성전자주식회사 셀프 리프레쉬 동작 모드에서 내부 고 전원전압을 사용하는 반도체 메모리 장치 및 그에 따른 고 전원전압 인가방법
US8369178B2 (en) * 2010-03-08 2013-02-05 Micron Technology, Inc. System and method for managing self-refresh in a multi-rank memory
US9411674B2 (en) * 2010-03-19 2016-08-09 Microsoft Technology Licensing, Llc Providing hardware resources having different reliabilities for use by an application
US20110296098A1 (en) 2010-06-01 2011-12-01 Dell Products L.P. System and Method for Reducing Power Consumption of Memory
KR101190741B1 (ko) * 2010-08-30 2012-10-12 에스케이하이닉스 주식회사 반도체 메모리 장치의 셀프 리프레시 제어회로 및 제어 방법
KR101190680B1 (ko) 2010-08-30 2012-10-16 에스케이하이닉스 주식회사 리프레시 제어회로 및 그를 이용한 반도체 메모리 장치
US8626999B2 (en) 2010-10-08 2014-01-07 Winbond Electronics Corp. Dynamic random access memory unit and data refreshing method thereof
KR101796116B1 (ko) 2010-10-20 2017-11-10 삼성전자 주식회사 반도체 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 그 동작방법
KR101239682B1 (ko) * 2010-12-29 2013-03-06 에스케이하이닉스 주식회사 내부전압생성회로 및 반도체 집적회로
TWI503662B (zh) 2012-12-27 2015-10-11 Ind Tech Res Inst 記憶體控制裝置及方法
WO2014113572A1 (en) 2013-01-16 2014-07-24 Maxlinear, Inc. Dynamic random access memory for communications systems
JP6163073B2 (ja) * 2013-09-26 2017-07-12 キヤノン株式会社 画像処理装置とその制御方法、及びプログラム
KR102289001B1 (ko) 2014-06-09 2021-08-13 삼성전자주식회사 솔리드 스테이드 드라이브 및 그것의 동작 방법
US9824742B1 (en) * 2016-04-28 2017-11-21 Qualcomm Incorporated DRAM access in self-refresh state
KR102650828B1 (ko) 2016-05-20 2024-03-26 삼성전자주식회사 둘 이상의 프로세서에 의해 공유되는 메모리 장치 및 상기 메모리 장치를 포함하는 시스템
CN107799137B (zh) 2016-08-30 2020-09-01 华邦电子股份有限公司 存储器存储装置及其操作方法
US10332582B2 (en) 2017-08-02 2019-06-25 Qualcomm Incorporated Partial refresh technique to save memory refresh power
US10236035B1 (en) * 2017-12-04 2019-03-19 Nanya Technology Corporation DRAM memory device adjustable refresh rate method to alleviate effects of row hammer events
KR102504614B1 (ko) * 2018-04-27 2023-03-02 에스케이하이닉스 주식회사 반도체 장치
US10622052B2 (en) * 2018-09-04 2020-04-14 Micron Technology, Inc. Reduced peak self-refresh current in a memory device
CN115798539A (zh) * 2021-09-10 2023-03-14 长鑫存储技术有限公司 一种信号屏蔽电路以及半导体存储器
KR20230044002A (ko) 2021-09-10 2023-03-31 창신 메모리 테크놀로지즈 아이엔씨 신호 차폐 회로 및 반도체 메모리
CN116543806B (zh) * 2023-06-13 2023-11-21 长鑫存储技术有限公司 刷新掩蔽信号生成电路、半导体存储装置及其刷新方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5511033A (en) * 1993-11-08 1996-04-23 Hyundai Electronics Industries Co., Ltd. Hidden self-refresh method and apparatus for synchronous dynamic random access memory
US5875143A (en) * 1996-07-15 1999-02-23 Motorola, Inc. Dynamic memory device with refresh circuit and refresh method
EP1074993A1 (en) * 1999-08-05 2001-02-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with reduced current consumption in data hold mode
US6215714B1 (en) * 1999-04-14 2001-04-10 Fujitsu Limited Semiconductor memory device capable of reducing power consumption in self-refresh operation

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4758993A (en) 1984-11-19 1988-07-19 Fujitsu Limited Random access memory device formed on a semiconductor substrate having an array of memory cells divided into sub-arrays
US4933907A (en) * 1987-12-03 1990-06-12 Mitsubishi Denki Kabushiki Kaisha Dynamic random access memory device and operating method therefor
US6212089B1 (en) * 1996-03-19 2001-04-03 Hitachi, Ltd. Semiconductor memory device and defect remedying method thereof
US5430681A (en) * 1989-05-08 1995-07-04 Hitachi Maxell, Ltd. Memory cartridge and its memory control method
US5652723A (en) * 1991-04-18 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
JP3400824B2 (ja) * 1992-11-06 2003-04-28 三菱電機株式会社 半導体記憶装置
JPH06333390A (ja) * 1993-05-20 1994-12-02 Fujitsu Ltd ダイナミックメモリリフレッシュ回路
US5469559A (en) * 1993-07-06 1995-11-21 Dell Usa, L.P. Method and apparatus for refreshing a selected portion of a dynamic random access memory
JP3220586B2 (ja) 1993-12-28 2001-10-22 富士通株式会社 半導体記憶装置
US5559981A (en) * 1994-02-14 1996-09-24 Motorola, Inc. Pseudo static mask option register and method therefor
KR0121776B1 (ko) * 1994-05-20 1997-12-05 김영환 동기식 디램의 히든 셀프 리프레쉬 장치
US6243768B1 (en) * 1996-02-09 2001-06-05 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US5627791A (en) * 1996-02-16 1997-05-06 Micron Technology, Inc. Multiple bank memory with auto refresh to specified bank
JPH09306164A (ja) * 1996-05-13 1997-11-28 Internatl Business Mach Corp <Ibm> メモリ・リフレッシュ・システム
TW329487B (en) * 1996-10-29 1998-04-11 Mitsubishi Electric Corp Device for processing data and method therefor
JPH10247384A (ja) * 1997-03-03 1998-09-14 Mitsubishi Electric Corp 同期型半導体記憶装置
US5818777A (en) * 1997-03-07 1998-10-06 Micron Technology, Inc. Circuit for implementing and method for initiating a self-refresh mode
KR19990009770A (ko) * 1997-07-11 1999-02-05 윤종용 반도체 메모리장치의 리프레쉬 블락 선택 회로 및 리프레쉬 방법
US5909449A (en) * 1997-09-08 1999-06-01 Invox Technology Multibit-per-cell non-volatile memory with error detection and correction
US6178130B1 (en) * 1997-10-10 2001-01-23 Rambus Inc. Apparatus and method for refreshing subsets of memory devices in a memory system
US6075744A (en) * 1997-10-10 2000-06-13 Rambus Inc. Dram core refresh with reduced spike current
JP3490887B2 (ja) * 1998-03-05 2004-01-26 シャープ株式会社 同期型半導体記憶装置
US5977864A (en) * 1998-05-15 1999-11-02 Lucent Technologies Inc. High speed comparator with bit-wise masking
JP2000021198A (ja) * 1998-06-30 2000-01-21 Mitsubishi Electric Corp 同期型半導体集積回路装置
JP2000036190A (ja) * 1998-07-17 2000-02-02 Toshiba Corp 半導体装置
KR20000025777A (ko) * 1998-10-14 2000-05-06 김영환 반도체메모리의 셀프 리프레시 제어회로
JP3259696B2 (ja) * 1998-10-27 2002-02-25 日本電気株式会社 同期型半導体記憶装置
JP4424770B2 (ja) * 1998-12-25 2010-03-03 株式会社ルネサステクノロジ 半導体記憶装置
KR100355226B1 (ko) * 1999-01-12 2002-10-11 삼성전자 주식회사 뱅크별로 선택적인 셀프 리프레쉬가 가능한 동적 메모리장치
US6094705A (en) * 1999-03-10 2000-07-25 Picoturbo, Inc. Method and system for selective DRAM refresh to reduce power consumption
KR100548540B1 (ko) * 1999-06-29 2006-02-02 주식회사 하이닉스반도체 리던던시 회로
KR100390985B1 (ko) * 1999-06-30 2003-07-12 주식회사 하이닉스반도체 리프레쉬장치
US6246619B1 (en) * 2000-02-07 2001-06-12 Vanguard International Semiconductor Corp. Self-refresh test time reduction scheme
JP2001338489A (ja) * 2000-05-24 2001-12-07 Mitsubishi Electric Corp 半導体装置
US6888776B2 (en) * 2000-09-06 2005-05-03 Renesas Technology Corp. Semiconductor memory device
US6341097B1 (en) * 2001-01-17 2002-01-22 International Business Machines Corporation Selective address space refresh mode
US6418068B1 (en) * 2001-01-19 2002-07-09 Hewlett-Packard Co. Self-healing memory
US6400593B1 (en) * 2001-02-08 2002-06-04 Intregrated Device Technology, Inc. Ternary CAM cell with DRAM mask circuit
US20020138690A1 (en) * 2001-03-23 2002-09-26 Simmonds Stephen M. System and method for performing a partial DRAM refresh

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5511033A (en) * 1993-11-08 1996-04-23 Hyundai Electronics Industries Co., Ltd. Hidden self-refresh method and apparatus for synchronous dynamic random access memory
US5875143A (en) * 1996-07-15 1999-02-23 Motorola, Inc. Dynamic memory device with refresh circuit and refresh method
US6215714B1 (en) * 1999-04-14 2001-04-10 Fujitsu Limited Semiconductor memory device capable of reducing power consumption in self-refresh operation
EP1074993A1 (en) * 1999-08-05 2001-02-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with reduced current consumption in data hold mode

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