CN1926633A - 半导体存储器以及半导体存储器的操作方法 - Google Patents
半导体存储器以及半导体存储器的操作方法 Download PDFInfo
- Publication number
- CN1926633A CN1926633A CNA2004800423602A CN200480042360A CN1926633A CN 1926633 A CN1926633 A CN 1926633A CN A2004800423602 A CNA2004800423602 A CN A2004800423602A CN 200480042360 A CN200480042360 A CN 200480042360A CN 1926633 A CN1926633 A CN 1926633A
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- Prior art keywords
- voltage
- signal
- refresh
- bit line
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 52
- 239000004065 semiconductor Substances 0.000 title claims description 46
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- 101000596041 Homo sapiens Plastin-1 Proteins 0.000 description 5
- 102100035181 Plastin-1 Human genes 0.000 description 5
- 101100422768 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SUL2 gene Proteins 0.000 description 5
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Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4067—Refresh in standby or low power modes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Abstract
Description
Claims (22)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2004/003168 WO2005088641A1 (ja) | 2004-03-11 | 2004-03-11 | 半導体メモリおよび半導体メモリの動作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1926633A true CN1926633A (zh) | 2007-03-07 |
CN1926633B CN1926633B (zh) | 2010-08-25 |
Family
ID=34975834
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2004800423602A Expired - Fee Related CN1926633B (zh) | 2004-03-11 | 2004-03-11 | 半导体存储器以及半导体存储器的操作方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7548468B2 (zh) |
JP (1) | JP4425911B2 (zh) |
CN (1) | CN1926633B (zh) |
WO (1) | WO2005088641A1 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103137185A (zh) * | 2011-11-21 | 2013-06-05 | 爱思开海力士有限公司 | 半导体存储装置 |
CN112908370A (zh) * | 2019-12-03 | 2021-06-04 | 爱思开海力士有限公司 | 存储器装置和操作该存储器装置的方法 |
CN113268018A (zh) * | 2020-02-14 | 2021-08-17 | 马自达汽车株式会社 | 旋转输出装置的控制装置 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4848564B2 (ja) | 2005-09-29 | 2011-12-28 | 株式会社ハイニックスセミコンダクター | 半導体メモリ装置のリセット制御回路 |
KR100706830B1 (ko) * | 2005-10-19 | 2007-04-13 | 주식회사 하이닉스반도체 | 반도체 메모리의 액티브 구간 제어장치 및 방법 |
JP2009064512A (ja) * | 2007-09-06 | 2009-03-26 | Panasonic Corp | 半導体記憶装置 |
JP5165974B2 (ja) * | 2007-09-10 | 2013-03-21 | パナソニック株式会社 | 半導体記憶装置 |
TWI423256B (zh) * | 2008-10-29 | 2014-01-11 | Etron Technology Inc | 資料感測裝置與方法 |
US8279686B2 (en) * | 2009-02-10 | 2012-10-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuits, systems, and methods for providing bit line equalization voltages |
US8391092B2 (en) * | 2010-07-02 | 2013-03-05 | Elite Semiconductor Memory Technology Inc. | Circuit and method for eliminating bit line leakage current in random access memory devices |
FR2965662A1 (fr) * | 2010-09-30 | 2012-04-06 | St Microelectronics Sa | Circuit d'aide a la lecture pour un dispositif memoire |
TWI469144B (zh) * | 2011-07-06 | 2015-01-11 | Elite Semiconductor Esmt | 用以控制隨機存取記憶體元件中的漏電流之電路和方法 |
JP7314685B2 (ja) * | 2019-07-25 | 2023-07-26 | セイコーエプソン株式会社 | 計時装置、電子機器及び移動体 |
CN113674787B (zh) * | 2021-08-26 | 2023-10-20 | 上海交通大学 | 在dram标准单元上实现非逻辑操作的方法及电路 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01122095A (ja) * | 1987-11-05 | 1989-05-15 | Mitsubishi Electric Corp | リフレッシュ競合裁定回路 |
JPH03122892A (ja) * | 1989-10-06 | 1991-05-24 | Hitachi Ltd | メモリ制御回路 |
JPH05166368A (ja) * | 1991-12-18 | 1993-07-02 | Sharp Corp | 擬似sram |
JP3358248B2 (ja) * | 1993-09-20 | 2002-12-16 | 富士通株式会社 | ダイナミックram |
JPH07296581A (ja) * | 1994-04-22 | 1995-11-10 | Nec Kyushu Ltd | 半導体記憶装置 |
DE19929095B4 (de) * | 1998-06-29 | 2005-12-08 | Fujitsu Ltd., Kawasaki | Halbleiterspeichervorrichtung mit übersteuertem Leseverstärker und Halbleitervorrichtung |
JP4025488B2 (ja) * | 1999-09-30 | 2007-12-19 | 富士通株式会社 | 半導体集積回路およびその制御方法 |
JP4531892B2 (ja) * | 1999-10-29 | 2010-08-25 | 富士通セミコンダクター株式会社 | 半導体集積回路、半導体集積回路の制御方法、および可変遅延回路 |
JP5034149B2 (ja) * | 2000-10-05 | 2012-09-26 | 富士通セミコンダクター株式会社 | 半導体メモリおよびその制御方法 |
KR100452327B1 (ko) * | 2002-07-08 | 2004-10-12 | 삼성전자주식회사 | 반도체 메모리 장치의 내부 전원 전압 발생회로 |
JP4167458B2 (ja) * | 2002-07-24 | 2008-10-15 | 松下電器産業株式会社 | 半導体メモリ装置及び半導体集積回路 |
-
2004
- 2004-03-11 WO PCT/JP2004/003168 patent/WO2005088641A1/ja active Application Filing
- 2004-03-11 JP JP2006510835A patent/JP4425911B2/ja not_active Expired - Fee Related
- 2004-03-11 CN CN2004800423602A patent/CN1926633B/zh not_active Expired - Fee Related
-
2006
- 2006-08-24 US US11/508,927 patent/US7548468B2/en not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103137185A (zh) * | 2011-11-21 | 2013-06-05 | 爱思开海力士有限公司 | 半导体存储装置 |
CN103137185B (zh) * | 2011-11-21 | 2017-03-01 | 爱思开海力士有限公司 | 半导体存储装置 |
CN112908370A (zh) * | 2019-12-03 | 2021-06-04 | 爱思开海力士有限公司 | 存储器装置和操作该存储器装置的方法 |
CN112908370B (zh) * | 2019-12-03 | 2024-01-26 | 爱思开海力士有限公司 | 存储器装置和操作该存储器装置的方法 |
CN113268018A (zh) * | 2020-02-14 | 2021-08-17 | 马自达汽车株式会社 | 旋转输出装置的控制装置 |
Also Published As
Publication number | Publication date |
---|---|
US7548468B2 (en) | 2009-06-16 |
US20060285405A1 (en) | 2006-12-21 |
WO2005088641A1 (ja) | 2005-09-22 |
CN1926633B (zh) | 2010-08-25 |
JPWO2005088641A1 (ja) | 2008-01-31 |
JP4425911B2 (ja) | 2010-03-03 |
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Legal Events
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: FUJITSU MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: FUJITSU LIMITED Effective date: 20081024 |
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C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20081024 Address after: Tokyo, Japan, Japan Applicant after: Fujitsu Microelectronics Ltd. Address before: Kanagawa Applicant before: Fujitsu Ltd. |
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C14 | Grant of patent or utility model | ||
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ASS | Succession or assignment of patent right |
Owner name: SUOSI FUTURE CO., LTD. Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD. Effective date: 20150514 |
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20150514 Address after: Kanagawa Patentee after: Co., Ltd. Suo Si future Address before: Kanagawa Patentee before: Fujitsu Semiconductor Co., Ltd. |
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CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100825 Termination date: 20170311 |
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CF01 | Termination of patent right due to non-payment of annual fee |