CN105679632A - 使用从惰性气体形成的亚稳态体的原子层蚀刻 - Google Patents

使用从惰性气体形成的亚稳态体的原子层蚀刻 Download PDF

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CN105679632A
CN105679632A CN201610031466.7A CN201610031466A CN105679632A CN 105679632 A CN105679632 A CN 105679632A CN 201610031466 A CN201610031466 A CN 201610031466A CN 105679632 A CN105679632 A CN 105679632A
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哈梅特·辛格
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Abstract

本发明公开了用于蚀刻原子层的衬底处理系统和方法。所述方法和系统被配置为将第一气体引入所述室，该气体是适合于蚀刻所述层的蚀刻剂气体，且允许所述第一气体存在于所述室中持续足以造成所述第一气体中的至少一些吸附到所述层的一段时间。用惰性气体实质上置换在所述室内的所述第一气体，然后从惰性气体产生亚稳态体以用所述亚稳态体蚀刻层，同时实质上防止所述等离子体带电物质蚀刻所述层。

Description

使用从惰性气体形成的亚稳态体的原子层蚀刻
本申请是申请号为201280035911.7，申请日为2012年7月11日，申请人为朗姆研究公司，发明创造名称为“使用从惰性气体形成的亚稳态体的原子层蚀刻”的发明专利申请的分案申请。
背景技术
原子层蚀刻是在本领域中已知的用于半导体器件制造的用非常精细的精度执行关键蚀刻的技术。在原子层蚀刻中，在薄层上进行蚀刻，同时尝试避免不必要的亚表面损伤或不希望有的改性。例如，可以执行原子层蚀刻以蚀刻覆盖另一关键层的非常薄的层。例如，在体型蚀刻步骤结束时，当试图清除层，同时确保薄的剩余层的蚀刻不会导致损坏下伏层和/或下伏结构时，也可使用原子层蚀刻。
详而言之，已知使用等离子体的蚀刻具有导致对下伏结构和/或下伏层产生上述的亚表面损伤或改性的潜力。在等离子体蚀刻过程中，栅极电介质下面的硅损失是亚表面损失的例子，即，即使在薄的栅极电介质(通常SiO2)存在下在栅极蚀刻过程中仍然产生的硅凹陷。在某些情况下，公知用大于100eV的离子能量的等离子体蚀刻导致对表面以下约20-40埃的深度的损伤。因此，在典型的栅极氧化层厚度为约10埃的情况下，栅极蚀刻后约10-20埃的硅凹陷是常见的。
本发明涉及用于在半导体器件制造中执行原子层蚀刻的改进的装置和方法。
发明内容
在一种实施方式中，本发明涉及一种用于蚀刻在半导体处理室中的衬底上的层的方法。该方法包括将第一气体引入所述室，该第一气体是适合用于蚀刻所述层的蚀刻剂气体。该方法还包括使所述第一气体能够存在于所述室持续足以造成所述第一气体中的至少一些吸附到层的一段时间。该方法进一步包括用惰性气体实质置换室中的第一气体。该方法另外包括从惰性气体产生亚稳态体(metastables)，并用所述亚稳态体蚀刻所述层。
上述内容只涉及此处披露的本发明的许多实施方式之一，并且不意图限制本发明的范围，在本文的权利要求中阐述了本发明的范围。将在下面本发明的具体实施方式中结合下面附图更详细地描述本发明的这些和其他特征。
附图说明
在附图中的图中通过举例的方式而不是通过限制的方式阐述本发明，其中相同的附图标记表示相似的元件，其中：
图1示出了根据本发明的一种或多种实施方式的适用于执行原子层蚀刻的衬底处理室的例子。
图2示出了根据本发明的一种或多种实施方式的分隔板结构和可选的准直器板的例子。
图3示出了根据本发明的一种或多种实施方式的用亚稳态体定向蚀刻的例子。
图4示出了根据本发明的一种实施方式的用于执行原子层蚀刻的步骤。
具体实施方式
下面将参照附图所示的若干实施方式来详细描述本发明。在下文中，为了提供对本发明的全面理解，阐述了很多特定的细节。然而，对本领域技术人员来说，很显然本发明可以在不具有这些细节的部分或全部的环境之下实现。在其他示例中，则未详细描述公知的工艺步骤和/或结构以免不必要地使本发明难以理解。
下文中描述了多种实施方式，包括方法和技术。应该了解的是，本发明还可包括制造的制品，该制品包括存储用于实施本发明的实施方式的计算机可读指令的计算机可读介质。举例来说，计算机可读介质包括，用于存储计算机可读代码的半导体的、磁性的、光磁性的、光学的或其他形式的计算机可读介质。此外，本发明也包括实现本发明实施方式的装置。这样的装置可包括专用和/或可编程的电路以执行关于本发明实施方式中的任务。这样的装置的例子包括通用计算机和/或适当编程的专用计算装置，并且还包括适用于与本发明的实施方式相关的不同任务的计算机/计算装置和专用的/可编程的电路的组合。
本发明的实施方式涉及用于在衬底(如半导体晶片或平板)的层上执行原子层蚀刻的装置和方法。在一种或多种实施方式中，适合于蚀刻衬底层的蚀刻剂源气体被引入到半导体处理室中。为了蚀刻Si层，例如，蚀刻剂气体可以是Cl2、HCl、CHF3、CH2F2、CH3F、H2、BCl3、SiCl4、Br2、HBr、NF3、CF4，SF6、O2、SO2、COS等中的一种或其混合物。该蚀刻剂气体被允许存在于该室持续足够量的时间以允许所述蚀刻剂气体物质中的至少一些被吸附到要蚀刻的层中。随后，蚀刻剂气体被置换为惰性气体(诸如Ar、He、Kr、Ne、Xe等中的一种或其混合物)。然后，从惰性气体形成亚稳态体以在衬底层上进行原子层蚀刻。该循环可以重复多次，直到原子层蚀刻完成。
在一种或多种实施方式中，亚稳态体是在室中的等离子体产生区域通过从惰性气体点燃的等离子体形成的。然后亚稳态从在等离子体产生区域中产生的等离子体迁移通过在分隔板中的孔以与衬底层接触。但是，高能等离子体的离子被防止接触晶片的表面，以尽量减少对衬底层的无意的蚀刻和/或亚表面损伤和/或改性。在原子层的蚀刻过程中，衬底被布置在室的晶片处理区域和在卡盘上。在接触衬底层表面时，亚稳态体被去激发，并在工艺中，放弃他们的电子能量，以造成在经吸附的(adsorbed)衬底表面处的表面反应，从而蚀刻衬底表面。由于亚稳态的定向能量往往(例如，氩的亚稳态为约0.025eV)比等离子体的高能离子的100-1000eV的能量要低得多，因此当使用惰性气体亚稳态体和吸附层的结合蚀刻时，损伤基本减至最低。
在一种或多种实施方式中，上述的分隔板是具有彼此电绝缘的多个板的多板结构。在本发明的一种或多种实施方式中，多板组件的板中的至少一个被偏置以排斥从等离子体所产生的离子。多板组件的板中的每个具有通孔，以允许亚稳态体从等离子体产生区域穿过到达晶片处理区域。如果需要，在一种实施方式中板的通孔可对齐，或者可以略微偏移。将分隔板的通孔的大小设置成实质上防止高能等离子体物质穿过分隔板并到达衬底表面。
在一种或多种实施方式中，准直器板被设置在分隔板和衬底之间以进行校准亚稳态体，从而只允许基本定向的亚稳态体到达衬底表面，以使蚀刻更具各向异性，即沿垂直于衬底平面的垂直方向。根据需要，准直器板可包括通孔并可接地或偏置。
为了防止由于分隔板和/或准直器板的孔图案造成的表面的非均匀蚀刻，所述分隔板和/或准直器板可以相对于衬底移动(或反之亦然)。分隔板和/或准直器板和/或晶片和晶片卡盘组件的相对的横向运动具有防止在分隔板或准直器板的孔图案仅在衬底表面的特定区域留下痕迹(imprint)的作用。
本发明的一种或多种实施方式包括用于执行如本文所描述的原子层蚀刻方法。本发明的一种或多种实施方式包括具有本文描述的硬件的衬底处理系统和/或衬底处理室并且还可以包括逻辑器(其可以经由专用逻辑电路、可编程逻辑电路来实现，和/或通过包含在计算机可读介质中的计算机可读代码和/或经由总线或数字网络(包括局域网和/或因特网)作为数字信号传送给微处理器/微控制器/计算机用于执行的计算机可读代码控制的微处理器/微控制器/计算机来实现)。
参照下面的附图和讨论可理解本发明的实施方式的特征和优点。
本发明的实施方式使用一种或多种惰性气体的亚稳态体以激发已吸附在衬底层(例如，硅层)的反应物(例如，卤素)的表面反应。尽管在本文中用Si层作为例子，但应理解的是，可以使用本发明的实施方式的原子蚀刻技术蚀刻任何层。在一种或多种实施方式中，将晶片的表面暴露于蚀刻剂气体(例如，Cl2、HCl、CHF3、CH2F2、CH3F、H2、BCl3、SiCl4、Br2、HBr、NF3、CF4、SF6、O2、SO2、COS等中的一种或其混合物)。在一种或多种实施方式中，衬底处理室可填充有蚀刻剂气体或蚀刻剂气体混合物持续短的一段时间(约0.05秒至约180秒)，以允许蚀刻剂气体分子吸附在衬底表面上。在一种或多种实施方式中，衬底处理室可填充有蚀刻剂气体或蚀刻剂气体混合物持续约0.25秒至约5秒，以允许蚀刻剂气体分子吸附在衬底表面上。
图1示出了根据本发明的一种实施方式的示例的衬底处理室，其包括在其上放置衬底104(例如晶片)的卡盘102。或者气体入口106或者108a/108b或入口106和108a/108b两者可用于将气体注入到室中。在一种或多种实施方式中，将惰性气体(如Ar、He、Kr、Ne、Xe等中的一种或其混合物)经由气体入口106注入到等离子体产生区域110中，而蚀刻剂气体经由气体入口108a/108b被引入到衬底处理区域112，以确保蚀刻剂气体不进入等离子体产生区域110。在这种情况下，优选的是，在等离子体产生区域110中的压强至少等于或大于在衬底处理区域112中的压强。等离子体产生区域110至少通过分隔板结构130(和任选地通过准直器板，这将在下文中讨论)与衬底处理区域112分隔开。
在接下来的步骤中，在蚀刻剂气体有足够的时间以吸附在衬底表面上后，蚀刻剂气体通过室排出泵120a/120b抽空。这可与通过进气口106引入惰性气体到等离子体产生区域110相结合来完成。如果蚀刻剂气体抽空完成而没有同时流入惰性气体，则下一个步骤可包括通过进气口106使惰性气体流动进入等离子体产生区域110。
在实质上将来自室的蚀刻剂气体置换为惰性气体时，惰性气体等离子体在等离子体室中产生，且更具体地在等离子体产生区域110中产生。在一种实施方式中，如果至少有80％的蚀刻剂气体被置换为惰性气体，则蚀刻剂气体被认为是实质上由惰性气体置换。在一种实施方式中，如果至少有90％的蚀刻剂气体被置换为惰性气体，则蚀刻剂气体被认为是实质上由惰性气体置换。在一种实施方式中，如果至少有95％的蚀刻剂气体被置换为惰性气体，则蚀刻剂气体被认为是实质上由惰性气体置换。在一种实施方式中，如果至少有99％的蚀刻剂气体被置换为惰性气体，则蚀刻剂气体被认为是实质上由惰性气体置换。
在等离子体中产生的亚稳态物质通过分隔板结构130移动到衬底处理区域112中。在衬底处理区域112中的压强可以使用例如涡轮分子泵、压力控制阀、分隔板的设计和惰性气体流量来控制。
在一种或多种实施方式中，合乎期望的是保持在衬底处理区域内的压强为<10毫乇，使得进入晶片加工区域的亚稳态体的大部分都能够影响衬底而不在晶片处理室中通过气体相碰撞而猝灭。例如，在一种实施方式中，可保持分隔板和衬底之间的距离在约1cm和25cm之间。
用于产生亚稳态体的等离子体源可以选自不同的技术，技术包括电感耦合等离子体(ICP)、电容耦合等离子体、空心阴极放电阵列、微波等离子体、或电子回旋共振(ECR)等离子体或任何其他合适的等离子体源技术。
图1还示出了感应耦合等离子体源150，其代表用于使射频能量与在等离子体产生区域110中产生的等离子体感应耦合的天线。在一种优选的实施方式中，可使用ICP(电感耦合等离子体)或ECR(电子回旋共振)等离子体源，因为它们在低压强下有产生高密度等离子体的能力。在一种或多种实施方式中，在等离子体产生区域110中的压强为介于约0.5毫乇和约100毫乇之间。
分隔板结构130被设计成作为接地表面以通过实质上防止等离子体带电物质到达所述衬底，从而限制通过在分隔板上中的孔泄漏的等离子体的量。在一种实施方式中，如果将要到达衬底表面的等离子体带电物质中的至少60％通过分隔板结构被防止到达衬底，则分隔板结构被认为实质上防止了等离子体带电物质到达衬底。在一种实施方式中，如果将要到达衬底表面的等离子体带电物质中的至少80％通过分隔板结构被防止到达衬底，则分隔板结构被认为实质上防止了等离子体带电物质到达衬底。在一种实施方式中，如果将要到达衬底表面的等离子体带电物质中的至少95％通过分隔板结构被防止到达衬底，则分隔板结构被认为实质上防止了等离子体带电物质到达衬底。在一种实施方式中，如果将要到达衬底表面的等离子体带电物质中的至少99％通过分隔板结构被防止到达衬底，则分隔板结构被认为实质上防止了等离子体带电物质到达衬底。
分隔板结构130的板可以由金属(例如，铝或不锈钢或类似的合适的材料)，或覆膜金属(例如，阳极氧化铝，涂有Y2O3、YF3、CeO2、硅、TiN的铝合金)制造。在一种或多种实施方式中，分隔板的厚度可以为介于1mm和25mm之间。在一种或多种实施方式中，在分隔板中的孔的直径可被选择以最小化或实质上防止等离子体泄漏穿过孔，并且可以是介于20微米到5毫米之间。
在一种或多种实施方式中，分隔板结构202是多层结构(如根据本发明的一种实施方式在图2所示)，据此，两个导电板204和206通过绝缘层208分隔开，使得彼此电绝缘。顶板204与在等离子体产生区域200中的等离子体接触，并电气接地。底板206可用小DC电压偏置以排斥来自等离子体所产生的离子。底板206上所施加的偏置电压可以大于等离子体电位，以防止大多数的离子到达衬底228上方的衬底处理区域210。在一种或多种实施方式中，底板206上所施加的电压可以在约10V至约50V之间。
在一种或多种实施方式中，以例如网孔等形式的准直器板226可设置在分隔板结构202和衬底228之间，以排斥任何等离子体带电物质通过分隔板结构202到达衬底228。如果需要的话，准直器板226可以被偏置以排斥等离子体带电物质或者可以接地。在另一种实施方式中，衬底228可以相对于等离子体电位被正向偏置，以防止等离子体带电物质到达衬底228。
分隔板结构202也用于校准向衬底228发射的中性束。在一种或多种实施方式中，通过在衬底228上保持压强低于10毫乇，优选<1毫乇，由于在1毫乇中性平均自由路径为约25cm，从分隔板结构202所散发的气体和气体在衬底处理区域210中在晶片228上方的气体之间的碰撞被最小化。这确保了亚稳态体到达晶片228的表面，而在从分隔板结构202运送至衬底228的过程中没有任何显著碰撞。
本发明的实施方式采用已被吸附和/或充满有反应物质(例如，卤素)的到达晶片表面上的惰性的亚稳态原子的通量。亚稳态原子携带大的电子能量到晶片以诱导化学反应。Ar亚稳态原子(Ar*，其中“*”表示亚稳态形式)携带，例如，约110.7eV的能量。当Ar*原子与表面相互作用时该能量被传递到晶片表面。
由于Ar*原子以接近热气体速率(0.025eV)行进，与通常用在蚀刻等离子体的高能离子(100-1000eV)相比，亚稳态原子赋予更小的动量和轰击到表面。在许多情况下，认为Ar*原子在撞击晶片时实质上不能导致表面损伤。
如图2所示，为了实现高度定向蚀刻，Ar和Ar*原子束可以使用另一种多孔板进一步校准。在本实施方式中，将与分隔板204和206具有实质上相同的孔图案的准直器板226放置在离分隔板结构202小的距离处。准直器板226被对齐，使得沿分隔板的轴线(即，垂直于分隔板平面)朝向衬底228行进的Ar*具有从在等离子体产生区域中的等离子体到晶片的视线。
更一般地说，仅沿着具有相对于该垂直轴(定义为垂直于分隔板平面的轴线)的小角度的圆锥体行进的Ar*(优选低于+/-3度，更优选小于+/-0.5度)可以通过准直器板226而没有与准直器板226发生任何碰撞。这些Ar*原子用箭头230和232示出。以相对于垂直轴线的更大角度行进的所有其他的Ar*原子(240和242)遭受与准直器板碰撞，并且被去激发，从而在碰撞时变成Ar基态。这个方案允许Ar*的垂直定向通量撞击在晶片表面上(与氩原子一起)，以产生更加垂直、更具各向异性的蚀刻。
Ar*原子的定向通量撞击在配给(dosed)有或吸附有如前面提到的蚀刻剂的特征上。Ar*原子将电子能量传递到表面，诱导例如导致特征的底部而不是在侧壁上的表面蚀刻的化学反应。当通过Ar*诱导的蚀刻(或Ar*诱导的解吸)在表面上的蚀刻剂完全耗尽时，蚀刻反应停止。因为从撞击表面的Ar和Ar*的束传递的动量非常小，所以在表面上实质上不发生损伤。图3示出这个垂直蚀刻方面是由于这一事实，即只有垂直定向的Ar*原子撞击特征304的底部302而不是特征304的侧壁306和308。
为了防止由于分隔板结构202和/或准直器板226中的孔图案造成的表面层的非均匀蚀刻，可以相对于衬底228移动分隔板结构202和/或准直器板226(或反之亦然)。分隔板结构202和/或准直器板226和/或晶片与晶片卡盘组件的相对的横向运动具有防止分隔板结构202或准直器板226的孔图案只在衬底表面的给定的区域留下痕迹的效果。
一般来说，分隔板结构202和/或准直器板226和/或晶片与晶片卡盘组件的相对的横向移动应该足够大，以确保在晶片上的所有相关的位置的Ar*的时间平均的均匀通量。在一般情况下，横向移动的幅度可以至少为与分隔板中的孔之间的距离一样大，在一种或多种实施方式中优选是分隔板中的孔之间的距离的2倍。
图4示出了根据本发明的实施方式的用于执行原子层蚀刻的步骤。在步骤402中，用蚀刻剂源气体填充室并且更具体地填充在晶片上方的室区域，以促进在衬底表面的蚀刻剂气体分子的吸附。在步骤404中，蚀刻剂气体从室抽空，并用惰性气体取代(步骤406)。然后惰性气体被激发和点燃以形成等离子体产生区域中的等离子体从而产生亚稳态体(步骤408)。
如上所述，采用惰性气体亚稳态体通过诱导在衬底的吸附表面上的表面反应来蚀刻衬底层。可采用分隔板结构以防止等离子体的高能物质接触衬底表面，从而最大限度地减少对衬底表面的损坏或过度蚀刻。如果需要的话，也可使用准直器板，以进一步促进蚀刻的方向性，从而产生高度的各向异性蚀刻。
在步骤410中，为了防止由于在分隔板结构和/或准直器板中的孔图案造成的表面层非均匀蚀刻，可相对于衬底横向移动分隔板和/或准直器板，(或反之亦然)。例如，移动可以通过合适的致动器装置(其可以包括马达和任选关联的传动装置)来执行。
从上述可知，本发明的实施方式采用惰性气体的亚稳态体激活已经吸附有蚀刻剂分子的衬底层的表面反应。通过采用亚稳态体的电子能量以在衬底的吸附表面层上执行蚀刻并通过防止等离子体物质在原子层蚀刻期间轰击衬底表面，本发明的实施方式有利地防止了当蚀刻高度精密的层和/或执行关键的原子层蚀刻时由等离子体中的高能物质造成的轰击损伤。
尽管已经通过多种实施方式来描述本发明，但依然有落入本发明的保护范围之内的变形方案、置换方案以及等同方案。如果本文中使用术语“组”，那么这样的术语意图具有其自身通用的能够理解的数学含义，其涵盖零个、一个或者多个一个成员。本发明应该被理解为涵盖了这些变形方案、置换方案以及等同方案。还应该注意的是，有许多实现本发明的方法和装置的替代方式。尽管本文中已经提供了不同的实施例，但其意思是这些实施例是说明性的而并不是对本发明的限制。

Claims (11)

1.一种具有用于蚀刻在衬底上的层的衬底处理室的衬底处理系统，其包含：
卡盘，在所述蚀刻过程中所述衬底被布置在其上；
分隔板结构，其将所述室分隔成等离子体产生区域和衬底处理区域；
等离子体源，其用于在所述等离子体产生区域中产生等离子体；以及
逻辑器，其用于：
将第一气体引入所述室，所述气体是适合于蚀刻所述层的蚀刻剂气体，
允许所述第一气体存在于所述室中持续足以造成所述第一气体中的至少一些吸附到所述层的一段时间，
用惰性气体实质上置换在所述室内的所述第一气体，
从所述惰性气体产生亚稳态体，以及
用所述亚稳态体蚀刻所述层。
2.根据权利要求1所述的衬底处理系统，其中，通过用所述等离子体源从所述惰性气体形成所述衬底处理区域内的等离子体而产生所述亚稳态体。
3.根据权利要求2所述的衬底处理系统，其中，所述亚稳态体在从所述等离子体迁移到所述层时穿过所述分隔板结构。
4.根据权利要求3所述的衬底处理系统，其中，所述分隔板结构具有被配置为实质上防止等离子体带电物质迁移到所述层的多个孔。
5.根据权利要求3所述的衬底处理系统，其中，所述分隔板结构包括彼此电气绝缘的至少两个板，所述两个板具有不同电压电位。
6.根据权利要求3所述的衬底处理系统，其还包括准直器板，其中所述亚稳态体在从所述等离子体迁移到所述层时还穿过所述准直器板，其中，所述准直器板被设置在所述衬底与所述分隔板结构之间。
7.根据权利要求3所述的衬底处理系统，其还包括用于在使用所述亚稳态体的所述蚀刻过程中使所述分隔板和所述准直器板和所述衬底中的至少一个相对其他移动的驱动装置。
8.一种具有衬底处理室的用于蚀刻在衬底上的层的衬底处理系统，在所述蚀刻过程中所述衬底设置在所述室内的卡盘上，该衬底处理系统包括：
分隔板结构，其将所述室分隔成等离子体产生区域和衬底处理区域；
等离子体源，其用于在所述等离子体产生区域中产生等离子体；以及
逻辑器，用于：
将第一气体引入所述室，所述气体是适合于蚀刻所述层的蚀刻剂气体，
允许所述第一气体存在于所述室中持续足以造成所述第一气体中的至少一些吸附到所述层的一段时间，
用惰性气体实质上置换在所述等离子体处理区域内的所述第一气体，
在所述等离子体产生区域中从所述惰性气体产生等离子体，以及
用来自所述等离子体的亚稳态体蚀刻所述层，其中，在实质上防止等离子体带电物质从所述等离子体迁移到所述层时执行所述蚀刻。
9.根据权利要求8所述的衬底处理系统，其中，所述分隔板结构具有被配置为实质上防止等离子体带电物质迁移到所述层的多个孔。
10.根据权利要求8所述的衬底处理系统，其中，所述分隔板结构包括彼此电气绝缘的至少两个板，所述两个板具有不同电压电位。
11.根据权利要求8所述的衬底处理系统，其还包括准直器板，其中所述亚稳态体在从所述等离子体迁移到所述层时还穿过所述准直器板，其中，所述准直器板被设置在所述衬底与所述分隔板结构之间。
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