WO2022007272A1 - 埋入式电路板及其制作方法 - Google Patents

埋入式电路板及其制作方法 Download PDF

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Publication number
WO2022007272A1
WO2022007272A1 PCT/CN2020/127015 CN2020127015W WO2022007272A1 WO 2022007272 A1 WO2022007272 A1 WO 2022007272A1 CN 2020127015 W CN2020127015 W CN 2020127015W WO 2022007272 A1 WO2022007272 A1 WO 2022007272A1
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Prior art keywords
layer
sub
inductance element
circuit layer
circuit
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PCT/CN2020/127015
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English (en)
French (fr)
Inventor
黄立湘
王泽东
缪桦
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深南电路股份有限公司
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Application filed by 深南电路股份有限公司 filed Critical 深南电路股份有限公司
Priority to EP20827982.8A priority Critical patent/EP4156873A4/en
Priority to US17/134,220 priority patent/US11452211B2/en
Publication of WO2022007272A1 publication Critical patent/WO2022007272A1/zh

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    • H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer, layered thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/08—Magnetic details
    • H05K2201/083—Magnetic materials
    • H05K2201/086—Magnetic materials for inductive purposes, e.g. printed inductor with ferrite core
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09072—Hole or recess under component or special relationship between hole and component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • the present application relates to the technical field of embedded inductors, and in particular, to an embedded circuit board and a manufacturing method thereof.
  • the present application provides an embedded circuit board and a manufacturing method thereof, which are compact in structure and high in integration.
  • a method for manufacturing an embedded circuit board includes: providing an inductance element and at least two layers of sub-body, wherein two adjacent sub-body layers are respectively provided with communicating slots at corresponding positions; embedding the inductive element to the inductor frame to form an inductor component; put the inductor component into the slot body of the first layer of sub-body, and glue the inductor component to the first layer of sub-body, wherein, between the inductor frame and the side wall of the slot body The distance is 80-120um; the remaining sub-body is set on the inductance element in turn; each layer of sub-body is pressed to fix the sub-body and the inductive element.
  • the present application provides an embedded circuit board
  • the circuit board includes: at least two layers of sub-body, wherein two adjacent layers of the sub-body are respectively provided with communicating grooves at corresponding positions; an inductance element , which is embedded in the groove body, and the inductance element and the side wall of the groove body are spaced apart.
  • the present application provides a method for manufacturing an embedded circuit board, comprising: providing an inductance element and at least two layers of sub-body with grooves in the same position; placing the inductive element in at least two layers of the sub-body The sub-body of each layer is pressed together to fix the sub-body and the inductive element; wherein, the inductive element and the side wall of the slot body are arranged at intervals.
  • the beneficial effects of the present application are: different from the situation in the prior art, the present application embeds the inductance element in the groove body by opening the corresponding groove bodies in the corresponding positions of the adjacent sub-body, and makes the inductance element and the groove body
  • the sidewalls are arranged at intervals, and the circuit board can be made compact in structure, high in integration, and safe and reliable by being pressed together by a pressing process.
  • FIG. 1 is a schematic structural diagram of an embodiment of an embedded circuit board of the present application
  • FIG. 2 is a schematic structural diagram of another embodiment of the embedded circuit board of the present application.
  • FIG. 3 is a schematic structural diagram of another embodiment of the embedded circuit board of the present application.
  • FIG. 4 is a schematic structural diagram of still another embodiment of the embedded circuit board of the present application.
  • FIG. 5 is a schematic flowchart of an embodiment of a method for manufacturing an embedded circuit board of the present application
  • FIG. 6 is a schematic flowchart of another embodiment of the method for manufacturing an embedded circuit board of the present application.
  • the embedded circuit board 100 includes: at least one layer of sub-body 10 and an inductance element 20 .
  • a through slot 101 is formed at a predetermined position of the sub-body 10 , the inductance element 20 is embedded in the slot 101 , and the inductance element 20 is spaced from the side wall 1011 of the slot 101 .
  • the inductance element 20 is embedded in the groove body 101 by opening the through groove body 101 at the preset position of the sub-body 10 , and the inductance element 20 is connected to the groove body 101 .
  • the sidewalls of the circuit boards are arranged at intervals, and the circuit board can be pressed by a pressing process to make the circuit board compact in structure, high in integration, and safe and reliable.
  • each of the sub-body 10A, 10B, and 10C is provided with a through-groove 101 , and the through-groove 101 on the 10A communicates with the through-groove 101 on the adjacent sub-body 10B.
  • the through grooves 101 on the 10C communicate with the through grooves 101 on the adjacent 10B.
  • the circuit board 100 may have multiple layers of sub-body, which is not limited to the case in this embodiment.
  • the sub-body 10B and 10C are then sleeved on the inductance element 20 through the communicating groove body 101, and finally the sub-body 10A and 10B of each layer are fixed by a pressing process.
  • 10C and the inductance element 20 can make the circuit board compact, highly integrated, safe and reliable.
  • a meltable medium layer 50 is provided between the sub-body 10A and 10B, 10B and 10C, and the sub-body 10 is formed by laminating and laminating the meltable medium layer 50 after the sub-body 10 is sleeved on the inductance element 20 by the groove body 101 .
  • at least part of the meltable dielectric layer 50 flows between the inductance element 20 and the sidewall of the tank body 101 and contacts the inductance element 20 .
  • the meltable dielectric layer 50 fills the space between the inductance element 20 and the side wall of the tank body 101, and after the meltable dielectric layer 50 is solidified again, the sub-layers 10A, 10B, and 10C of each layer are relatively adhered and fixed.
  • the inductance element 20 is surrounded, and the inductance element 20 is fixed to the sub-body 10A, 10B, and 10C of each layer to form a high-strength and compact product structure.
  • the thickness of the meltable medium layer 50 is 40-300um, for example, 240um.
  • the sub-body 10 can be a copper-free core board layer, and the thickness of the copper-free core board layer is 200-500um, for example, 400um.
  • the purpose of selecting the copper-free core board layer for the sub-body 10 is to thicken the thickness of the circuit board 100 and bury the inductor element 20 with a sufficient thickness.
  • the sub-body 10 can also be optionally provided with a copper core board layer, on which lines can be arranged for circuit connection.
  • the embedded circuit board 100 further includes: a first circuit layer 30 and a second circuit layer 40 .
  • the first circuit layer 30 and the second circuit layer 40 respectively cover opposite ends of the groove body 101 , so that the inductance element 20 is located between the first circuit layer 30 and the second circuit layer 40 .
  • connection terminal 201 of the inductance element 20 can be arranged at one end of the inductance element 20 close to the first circuit layer 30 .
  • the first circuit layer 30 is provided with a laser through hole (not shown in the figure), and a conductive column 301 is arranged in the laser through hole.
  • the connection terminal 201 of the element 20 is connected to the first circuit layer 30 through the conductive column 301 .
  • connection terminal 201 of the inductance element 20 is arranged at one end of the inductance element 20 close to the second circuit layer 40, the second circuit layer is provided with a laser through hole, and a conductive column (not shown) is arranged in the laser through hole, The connection terminal 201 of the inductance element 20 is connected to the second circuit layer 40 through the conductive column.
  • connecting terminals 201 may also be provided at one end of the inductance element 20 close to the first circuit layer 30 and at one end close to the second circuit layer 40 , and both at the corresponding positions of the first circuit layer 30 and the second circuit layer 40 Laser through holes are provided, and conductive pillars 301 are arranged in the laser through holes.
  • the connection terminals 201 of the inductance element 20 can be connected to the first circuit layer 30 and the second circuit layer 40 through the conductive pillars 301 .
  • the corresponding positions of the sub-body 10 and the meltable dielectric layer 50 are provided with conductive holes 200 for interlayer connection, and the corresponding positions of the first circuit layer 30 and the second circuit layer 40 and the conductive holes 200 are provided with Conductive blind vias, wherein the connection terminals 201 of the inductance element 20 are electrically connected to the conductive blind vias of the second wiring layer 40 through the conductive blind vias and the conductive vias 200 of the first wiring layer 30 in sequence.
  • the sub-body 10 and the fusible dielectric layer 50 may be patterned to form through holes in the sub-body 10 and the fusible dielectric layer 50, and copper immersion plating may be performed on the through holes to form on the inner walls of the through holes
  • the conductive layer is formed to obtain conductive holes 200 .
  • the connection terminals 201 of the inductance element 20 can pass through the conductive blind holes and the conductive holes 200 in the first circuit layer 30 in sequence. It is electrically connected to the conductive blind holes of the second circuit layer 40 .
  • one or more components are arranged on the side of the first circuit layer 30 away from the tank body or on the side of the second circuit layer 40 away from the tank body, and there may also be multiple components. They are respectively arranged on the side of the first circuit layer 30 away from the tank body and on the side of the second circuit layer 40 away from the tank body, and the components are electrically connected to the inductance element 20 through the first circuit layer 30 or the second circuit layer 40 , wherein the components can be one or more of chips, capacitive elements, resistive elements, and power supply devices.
  • the first dielectric layer 50 is filled between the two sub-body 10, the second dielectric layer 60, the first dielectric layer 50 and the second dielectric are filled between the inductor element 20 and the sidewall 1011 of the groove body Layer 60 is welded by a single press fit.
  • the first dielectric layer 50 is melted to bond the adjacent sub-body 10 together, and part of the first dielectric layer 50 flows between the inductance element 20 and the sidewall 1011 of the tank body, and contacts the inductance element 20.
  • the second dielectric layer 60 is also melted, and the first dielectric layer 50 and the second dielectric layer 60 are bonded together. After cooling and solidification, the first dielectric layer 50 and the second dielectric layer 60 become an integral structure.
  • the first dielectric layer 50 and the second dielectric layer 60 may be of the same material, or may be of different materials.
  • the first dielectric layer 50 and the second dielectric layer 60 are an insulating material or any combination of resin and molding silicone resin glue, wherein the molding silicone resin glue is a colorless and transparent liquid, and when cured It has certain air permeability and elasticity, and it mainly has temperature resistance, weather resistance, electrical insulation, physiological inertia, low surface tension and low surface energy.
  • Resin refers to an organic polymer that has a softening or melting range after being heated, and has a tendency to flow under the action of external force when softened. It is solid, semi-solid, and sometimes liquid at room temperature.
  • At least two identification patterns can be provided at the corresponding positions of the sub-body 10 of each layer, and positioning holes are set based on the identification patterns, and the positioning holes can be used to align the sub-body 10 of each layer and accurately pass through the respective grooves.
  • the body 101 is sheathed on the inductive element 20, and then all the sub-body are pressed together.
  • the positioning holes By arranging the positioning holes, when the sub-body 10 is sleeved on the inductance element 20, the sub-body 10 of each layer can be arranged neatly, and the groove body 101 of the sub-body 10 can be accurately inserted into the inductive element 20 without damaging the element, which improves the accuracy degree and yield.
  • a logo pattern can be set on the sub-body 10
  • the groove bodies 101 of each layer of the sub-body 10 can be set based on the logo pattern, and the shape and size of the groove bodies 101 of each layer of the sub-body 10 are the same. It is used for aligning the sub-body 10 of each layer, accurately nesting the sub-body 10 on the inductance element 20 through the respective groove body 101, and then pressing all the sub-body 10 together.
  • the identification pattern is also used to locate the connection terminal 201 of the inductance element 20. Specifically, an identification pattern can be set on the first-layer sub-body 10A corresponding to the position of the connection terminal 201 of the inductance element 20, and the first-layer sub-body 10A can be set according to the identification pattern. 2. Laser drilling is performed on the first dielectric layer 50 adjacent to the first layer sub-body 10A, and laser drilling is also performed on the first circuit layer 30 or the second circuit layer 40, so that the first layer sub-body 10A is adjacent to the first layer. Laser through holes are formed on the first dielectric layer 50 of the sub-body, and laser through holes are also formed on the first circuit layer 30 or the second circuit layer 40 .
  • the sub-body 10 is a copper clad laminate, and a chemical etching process is used to etch the copper foil layer on the sub-body 10 to form a logo pattern, wherein the chemical etching process refers to a method for removing materials by etching with an etchant.
  • the material of the logo pattern is X-ray transparent material, and the position of the logo pattern can be determined under the irradiation of X-ray.
  • the inductance element 20 is surrounded by an inductance frame 70 , and the inductance frame 70 is used to assist the inductance element 20 in an upright state when the sub-body 10 is sleeved on the inductance element 20 by using the slot 101 , so as to The inductance element 20 is always kept at a preset distance from the side wall 1011 of the tank body.
  • the distance between the inductor frame 70 and the side wall 101 of the slot body is 80-120um.
  • the inductor frame 70 is made of conductive material, and the inductor element 20 is connected to the first circuit layer 30 through the inductor frame 70 and the conductive posts 301 connected to the inductor frame 70 .
  • a laser hole may be provided on the second circuit layer 40
  • a conductive column may be provided in the laser hole
  • the inductance element 20 is connected to the conductive column through one end of the inductance frame 70 close to the second circuit layer 40 to realize electrical connection with the second circuit layer 40 . connect.
  • Laser through holes can also be arranged at the positions of the first circuit layer 30 and the second circuit layer 40 corresponding to the inductor frame 70, and conductive pillars are arranged in the laser through holes, and the inductor element 20 is connected to the conductive pillars through the inductor frame 70, thereby The inductance element 20 is electrically connected to the first wiring layer 30 and the second wiring layer 40 .
  • the fabrication method of the embedded circuit board includes the following steps:
  • S11 Provide inductance components and at least two sub-body with slots in the same position.
  • An inductance element and at least two layers of sub-body are provided, and the at least two layers of sub-body are provided with a through slot at the same position, and the sub-body can be a copper-free core board or other materials that can be used to manufacture circuit boards.
  • the inductance element is embedded on the inductance frame to form an inductance component, and the inductance frame is used to assist the inductance element to maintain an upright state during the process that the sub-body is embedded in the inductance element with the slot body, so that the inductance element is always connected with the inductance element.
  • the side wall of the tank body maintains a preset distance.
  • the purpose of adhering the inductive component to the first-layer sub-body is to prevent the inductive component from being deflected and to keep the inductive component in an upright state.
  • the inductance component and the first layer of sub-body can be bonded with adhesive tape. If the inductive component and the first layer of sub-body are bonded with adhesive tape in this step, the non-bonded part is left, and the inductive element is not easy to be biased or not biased. After pouring, remove the tape through the unbonded part, understandably, the tape needs to be de-energized before pressing. In other embodiments, hot melt adhesive or glue may be used to bond the inductor component and the first layer sub-body.
  • first circuit layer is covered on the outermost first meltable medium layer
  • second meltable medium layer is sequentially covered on the side of the first layer sub-body away from the first circuit layer.
  • identification patterns can be provided at corresponding positions on the first meltable medium layer and the sub-body, and positioning holes are arranged according to the identification patterns, and the positioning holes are used to align each layer of the sub-body with the first meltable medium, so that the When the first meltable dielectric layer and the remaining sub-body are alternately stacked and sleeved on the inductive element, the inductive element can accurately fall into the groove on the sub-body, so as to avoid damage to the element and improve the yield.
  • the sub-body, the first meltable medium layer and the second meltable medium layer can be patterned to form an identification pattern. Through holes are formed, copper plating is performed on the through holes to form a conductive layer on the inner wall of the through holes, and conductive holes are obtained.
  • the connection terminals of the inductance element are electrically connected to the conductive blind holes of the second circuit layer through the conductive blind holes and the conductive holes of the first circuit layer in sequence.
  • laser drilling is performed on the first layer of the sub-body, the first circuit layer and/or the second circuit layer according to the identification pattern on the sub-body layer, so that the first layer of the sub-body, the first circuit layer and/or Laser through holes are formed in the second circuit layer, wherein the marking patterns on the sub-body layer are arranged corresponding to the connection terminals of the inductance element, and conductive pillars are arranged in the laser through holes, so that the connection terminals of the inductance element are connected to the first circuit through the conductive pillars layer and/or second wiring layer.
  • copper clad laminate can be selected as the daughter body, and the copper foil layer on the copper clad laminate is etched by chemical etching process to form a logo pattern, wherein the chemical etching process refers to the method of using etching solution to etch and remove materials.
  • the material of the logo pattern is X-ray permeable material, and under the action of X-ray, the position of the logo pattern can be determined, and it is convenient to set the positioning hole.
  • a second dielectric layer may be filled between the inductance element and the sidewall of the tank body, so that the inductance element is more firmly bonded to the sidewall of the tank body.
  • the second medium layer, the second meltable medium layer and the first meltable medium layer may be one or any combination of resin and molding silicone resin glue.
  • Molding silicone resin glue which is a colorless and transparent liquid, has certain air permeability and elasticity during curing. It mainly has temperature resistance, weather resistance, electrical insulation, physiological inertia, low surface tension and low surface energy.
  • Resin refers to an organic polymer that has a softening or melting range after being heated, and has a tendency to flow under the action of external force when softened. It is solid, semi-solid, and sometimes liquid at room temperature.
  • the second circuit layer, the second meltable dielectric layer, the sub-body layers, the first meltable dielectric layers and the first circuit layers are pressed together to fix the second circuit layer, the sub-body layer, an inductance element and a first circuit layer.
  • the first meltable medium layer will melt, and then each sub-body layer and the first circuit layer will be bonded together, and the second meltable medium layer will also be melted, connecting the second circuit layer with the adjacent circuit layer.
  • the daughter layers are glued together. Part of the first meltable medium layer with certain fluidity enters the tank body, combines with the melted second medium layer, and forms an integrated structure after solidification.
  • S21 Provide inductance components and at least two sub-body with slots in the same position.
  • S23 Arrange several layers of the first meltable medium layer and the remaining sub-body on the inductance element alternately in sequence, and cover the first circuit layer on the outermost first meltable medium layer.
  • a second dielectric layer can be added between the inductance element and the sidewall of the tank body, so that the inductance element is more firmly bonded to the sidewall of the tank body.
  • S24 Perform the first lamination on the first circuit layer, several layers of the first meltable dielectric layers, and each layer of the sub-body layers.
  • the first pressing is performed.
  • the first meltable medium layer is heated and melted, and each adjacent sub-body layer and the first circuit layer are bonded together, the second dielectric layer is also heated and melted, the inductor element and the side wall of the tank body are bonded together, and part of the first meltable dielectric layer enters the tank body and is bonded with the second dielectric layer
  • each first meltable medium layer and the second medium layer form an integrated structure.
  • the first wiring layer, the sub-body, and the inductive element are fixed.
  • S25 Covering the second meltable medium layer and the second circuit layer in sequence on the side of the first layer sub-body away from the first circuit layer.
  • the second meltable medium layer is covered on the side of the first layer sub-body away from the first circuit layer, and the second circuit layer is covered on the side of the second meltable medium layer away from the first layer of the sub-body.
  • S26 Perform a second lamination on the second circuit layer, the second meltable dielectric layer, each sub-body layer, several layers of the first meltable dielectric layer, and the first circuit layer.
  • the cover of the second meltable medium layer and the second circuit layer is completed, and the second pressing is performed.
  • each of the first meltable medium layer and the second medium layer is melted again, and each The daughter layers are more compactly laminated, reducing the thickness of the circuit board, and the second meltable dielectric layer melts, bonding the second circuit layer to the first layer of daughter bodies.
  • the second circuit layer, the sub-body layer, the inductance element and the first circuit layer are fixed.
  • the beneficial effects of the present application are: different from the situation in the prior art, the present application embeds the inductance element in the groove body by opening the corresponding groove bodies in the corresponding positions of the adjacent sub-body, and makes the inductance element and the groove body
  • the sidewalls are arranged at intervals, and the process steps are simple and convenient, which can make the circuit board compact, highly integrated, safe and reliable.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种埋入式电路板（100），该埋入式电路板（100）包括：至少一层子体（10），其中，所述子体（10）的预设位置上开设有贯通的槽体（101）；电感元件（20），嵌设在所述槽体（101）内，且所述电感元件（20）与所述槽体（101）的侧壁（1011）间隔设置。通过上述方式，能够使得所述埋入式电路板结构紧凑，集成度高，使用范围广，安全可靠。

Description

埋入式电路板及其制作方法 技术领域
本申请涉及电感埋入技术领域，特别是涉及一种埋入式电路板及其制作方法。
背景技术
当今电子产品向短小轻薄的方向发展，电路板的密度要求也越来越高，但在电路板的设计中，电感被大量应用，电源类型电路板的电感元件占用电源板40％以上表面积。
发明内容
本申请提供一种埋入式电路板及其制作方法，其结构紧凑且集成度高。
一方面，一种埋入式电路板的制作方法，包括：提供电感元件和至少两层子体，其中两层相邻的子体在对应位置分别开设有相通的槽体；将电感元件嵌设到电感框架上，以组成电感组件；将电感组件置入第一层子体的槽体中，并将电感组件与第一层子体粘合，其中，电感框架与槽体的侧壁之间的距离为80-120um；将剩余子体依次套设在电感元件上；压合各层子体以固定子体和电感元件。
另一方面，本申请提供了一种埋入式电路板，电路板包括：至少两层子体，其中，两层相邻的所述子体在对应位置分别开设有相通的槽体；电感元件，嵌设在所述槽体内，且所述电感元件与所述槽体的侧壁间隔设置。
又一方面，本申请提供了一种埋入式电路板的制作方法，包括：提供电感元件和至少两层带相同位置槽体的子体；将所述电感元件置入至少两层所述子体的槽体内；压合各层所述子体以固定所述子体和所述电感元件；其中，所述电感元件与所述槽体的侧壁间隔设置。
本申请的有益效果是：区别于现有技术的情况，本申请通过在相邻子体的对应位置分别开设相通的槽体，将电感元件嵌设在槽体内，且使 电感元件与槽体的侧壁间隔设置，通过压合工艺压合，可以使得电路板结构紧凑，集成度高，且安全可靠。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本申请埋入式电路板一实施例的结构示意图；
图2是本申请埋入式电路板另一实施例的结构示意图；
图3是本申请埋入式电路板又一实施例的结构示意图；
图4是本申请埋入式电路板再一实施例的结构示意图；
图5是本申请埋入式电路板的制作方法一实施例的流程示意图；
图6是本申请埋入式电路板的制作方法又一实施例的流程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
参阅图1，埋入式电路板100包括：至少一层子体10和电感元件20。
子体10的预设位置上开设有贯通的槽体101，电感元件20嵌设在槽体101内，且电感元件20与槽体101的侧壁1011间隔设置。
区别于现有技术的情况，本申请实施例通过在子体10的预设位置上开设贯通的槽体101，将电感元件20嵌设在槽体101内，且使电感元件20与槽体101的侧壁间隔设置，通过压合工艺压合，可以使得电路板结构紧凑，集成度高，且安全可靠。
进一步地，当子体的数量大于等于2时，至少两层相邻的子体10 在对应位置分别开设有相通的槽体101。
具体地，子体10A、10B、10C上均开设有贯通槽101，10A上的贯通槽101与相邻子体10B上的贯通槽101相通。10C上的贯通槽101与相邻10B的贯通槽101相通。电路板100可以有多层子体，不限于本实施例中的情况。
通过在子体10的预设位置开设贯通的槽体101，再将子体10B、10C通过相通的槽体101套在电感元件20上，最后再通过压合工艺固定各层子体10A、10B、10C和电感元件20，可以使得电路板结构紧凑，集成度高，且安全可靠。
可选地，子体10A与10B、10B与10C之间设有可熔融介质层50，子体10在利用槽体101套设在电感元件20后，通过可熔融介质层50层叠压合而成，至少部分可熔融介质层50流入电感元件20与槽体101的侧壁之间并接触电感元件20。可选的，可熔融介质层50填满电感元件20与槽体101的侧壁之间的空间，可熔融介质层50再次凝固后将各层子体10A、10B、10C相对粘连并固定，同时包围电感元件20，将电感元件20固定到各层子体10A、10B、10C上，形成强度高且紧凑的产品结构。
本实施例中，可熔融介质层50的厚度为40-300um，例如可以是240um。子体10可以是无铜芯板层，无铜芯板层的厚度为200-500um，例如可以是400um。子体10选无铜芯板层的目的是将电路板100厚度加厚，以足够厚度埋入电感元件20。当然，子体10也可选有铜芯板层，其上可以设置线路以进行电路连接。
在一实施例中，埋入式电路板100还包括：第一线路层30、第二线路层40。第一线路层30、第二线路层40分别覆盖槽体101的相对两端，使得电感元件20位于第一线路层30和第二线路层40之间。
电感元件20的连接端子201可以设置在电感元件20靠近第一线路层30的一端，第一线路层30上设有激光通孔(图未示)，激光通孔中设有导电柱301，电感元件20的连接端子201通过导电柱301连接第一线路层30。
可选地，电感元件20的连接端子201设置在电感元件20靠近第二线路层40的一端，第二线路层上设有激光通孔，激光通孔中设有导电柱(图未示)，电感元件20的连接端子201通过导电柱连接第二线路层40。
参阅图2，还可以在电感元件20靠近第一线路层30的一端和靠近第二线路层40的一端均设置连接端子201，在第一线路层30和第二线路层40的对应位置处均设置激光通孔，并在激光通孔中设置导电柱301，电感元件20的连接端子201可以通过导电柱301连接第一线路层30和第二线路层40。
本实施例中，子体10及可熔融介质层50的对应位置均开设有用于层间连接的导电孔200，第一线路层30和第二线路层40与导电孔200的对应位置上设有导电盲孔，其中，电感元件20的连接端子201依序通过第一线路层30的导电盲孔和导电孔200与第二线路层40的导电盲孔电连接。
具体地，可以对子体10和可熔融介质层50进行图形化处理，以在子体10和可熔融介质层50形成贯穿孔，对贯穿孔进行沉铜电镀，以在贯穿孔的内壁上形成导电层，得到导电孔200。在第一线路层30和第二线路层40与导电孔200对应的位置上设置导电盲孔，可以实现电感元件20的连接端子201依序通过第一线路层30的导电盲孔和导电孔200与第二线路层40的导电盲孔电连接。
可选地，设置一个或一个以上元器件(图未示)在第一线路层30远离槽体的一侧上或第二线路层40远离槽体的一侧上，还可以有多个元器件分别设置在第一线路层30远离槽体的一侧上、第二线路层40远离槽体的一侧上，元器件通过第一线路层30或第二线路层40实现与电感元件20电连接，其中，元器件可以是芯片、电容元件、电阻元件、电源器件中的一种或几种。
在一实施例中，两层子体10之间填有第一介质层50，电感元件20与槽体的侧壁1011之间填有第二介质层60，第一介质层50和第二介质层60经一次压合熔接。
在进行高温压合时，第一介质层50融化，将相邻的子体10粘合在一起，部分第一介质层50流入电感元件20与槽体的侧壁1011之间，并接触电感元件20，第二介质层60也融化，第一介质层50与第二介质层60粘合在一起，冷却固化后，第一介质层50与第二介质层60成为一体结构。其中，第一介质层50与第二介质层60可以是相同材料，也可以是不同材料。
可选地，第一介质层50与第二介质层60为树脂、molding硅树脂胶中的一种绝缘材料或任意组合，其中，molding硅树脂胶，其是一种无色透明液体，固化时具有一定的透气性及弹性，其主要具有耐温特性、耐候性、电气绝缘性、生理惰性、低表面张力和低表面能。树脂是指受热后有软化或熔融范围，软化时在外力作用下有流动倾向，常温下是固态、半固态，有时也可以是液态的有机聚合物。
可选地，可以在每层子体10的对应位置设置至少两个标识图形，由标识图形为基准设置定位孔，定位孔可以用于将各层子体10进行对准、准确地通过各自槽体101套在电感元件20，再将所有子体压合。通过设置定位孔，在将子体10套设于电感元件20时，可以使各层子体10整齐排列，且子体10的槽体101能够精准套入电感元件20而不损伤元件，提高准确度和成品率。
在其他的实施例中，可以在子体10上设置标识图形，以标识图形为基准设置各层子体10的槽体101，且各层子体10的槽体101形状与尺寸相同，槽体用于将各层子体10进行对准、准确地通过各自槽体101套设在电感元件20，再将所有子体10压合。
标识图形还用于定位电感元件20的连接端子201，具体地，可在第一层子体10A上对应电感元件20的连接端子201的位置设置标识图形，根据标识图形对第一层子体10A、邻近第一层子体10A的第一介质层50进行激光打孔，对第一线路层30或第二线路层40也进行激光打孔，以使第一层子体10A、邻近第一层子体的第一介质层50上形成激光通孔，第一线路层30或第二线路层40上也形成激光通孔。
可选地，子体10是覆铜板，采用化学蚀刻工艺对子体10上的铜 箔层进行蚀刻，以形成标识图形，其中，化学蚀刻工艺是指采用蚀刻液蚀刻去除材料的方法。标识图形的材料为可透X光材料，在X光线照射下，可以确定标识图形的位置。
参阅图3-4，电感元件20的外部围设有电感框架70，电感框架70用于在子体10利用槽体101套设在电感元件20的过程中辅助电感元件20保持竖立的状态，以使电感元件20始终与槽体的侧壁1011保持预设距离。
其中，电感框架70与槽体的侧壁101之间的距离为80-120um。
电感框架70为导电材料，电感元件20通过电感框架70和与电感框架70连接的导电柱301连接第一线路层30。或者，可以在第二线路层40上设置激光孔，在激光孔中设置导电柱，电感元件20通过电感框架70靠近第二线路层40的一端连接导电柱，实现与第二线路层40的电连接。
还可以在第一线路层30和第二线路层40对应电感框架70的位置处均设置激光通孔，并在激光通孔中设置导电柱，电感元件20通过电感框架70与导电柱连接，从而实现电感元件20与第一线路层30和第二线路层40的电连接。
参阅图5，该埋入式电路板的制作方法包括以下步骤：
S11：提供电感元件和至少两层带相同位置槽体的子体。
提供电感元件，以及至少两层子体，且至少两层子体在相同的位置开设有贯通的槽体，子体可以是无铜芯板或其他可用于制造电路板的材料。
S12：将电感元件置入至少两层子体的槽体内，其中，电感元件与槽体的侧壁间隔设置。步骤如下：
(1)将电感元件置入第一层子体的槽体中。
可选地，将电感元件嵌设到电感框架上，组成电感组件，电感框架用于在子体利用槽体套设在电感元件的过程中辅助电感元件保持竖立的状态，以使电感元件始终与槽体的侧壁保持预设距离。
将电感组件置入第一层子体的槽体中，并将电感组件与第一层子体 粘合。将电感组件与第一层子体粘合的目的是防止电感组件偏倒，使电感组件保持竖立状态。
在一实施例中，可以使用胶带粘合电感组件和第一层子体，若此步骤使用胶带粘合电感组件和第一层子体，留出不粘合部分，电感元件不易偏倒或不偏倒后，通过不粘合部分去掉胶带，可以理解的是，胶带需在压合之前去电。在其它实施例中，可以采用热熔胶或胶水粘合电感组件和第一层子体。
(2)将剩余子体依次套设在电感元件上。
在一实施例中，可以按照以下步骤实施：
将若干层第一可熔融介质层以及剩余子体依次交替层叠套设在电感元件上，将第一线路层盖设在最外侧的第一可熔融介质层上，将第二可熔融介质层、第二线路层依次盖设在第一层子体远离第一线路层的一侧。
在其它实施例中，可以按照以下步骤实施：
依次放置第二线路层、第二可熔融介质层以及第一层子体，将电感元件容置于第一层子体的槽体，将剩余若干层第一可熔融介质层以及剩余子体依次交替层叠套设在电感元件上，将第一线路层盖设在最外侧的第一可熔融介质层上
可选地，可以在第一可熔融介质层和子体上的对应位置设置标识图形，根据标识图形设置定位孔，定位孔用以将各层子体和第一可熔融介质对准，从而在将第一可熔融介质层以及剩余子体依次交替层叠套设在电感元件上时，电感元件可精准落入子体上的槽体，以免造成元件损伤，从而提高成品率。
进一步地，可以对子体和第一可熔融介质层、第二可熔融介质层进行图形化处理，形成标识图案，通过标识图案在子体和第一可熔融介质层、第二可熔融介质层形成贯穿孔，对贯穿孔进行沉铜电镀，以在贯穿孔的内壁上形成导电层，得到导电孔，在第一线路层和第二线路层与导电孔对应的位置上设置导电盲孔，可以实现电感元件的连接端子依序通过第一线路层的导电盲孔和导电孔与第二线路层的导电盲孔电连接。
可选地，根据子体层上的标识图形对第一层子体、第一线路层和/或第二线路层进行激光打孔，以在第一层子体、第一线路层和/或第二线路层形成激光通孔，其中，子体层上的标识图形与电感元件的连接端子对应设置，在激光通孔中设置导电柱，以使电感元件的连接端子通过导电柱连接第一线路层和/或第二线路层。
其中，子体可以选用覆铜板，采用化学蚀刻工艺对覆铜板上的铜箔层进行蚀刻，以形成标识图形，其中，化学蚀刻工艺是指采用蚀刻液蚀刻去除材料的方法。标识图形的材料为可透X光材料，在X光线作用下，可以确定标识图形的位置，便于设置定位孔。
可以在电感元件与槽体的侧壁之间填入第二介质层，以使电感元件更加稳固地与槽体侧壁粘合。
其中，第二介质层、第二可熔融介质层和第一可熔融介质层可以是树脂、molding硅树脂胶中的一种或任意组合。molding硅树脂胶，其是一种无色透明液体，固化时具有一定的透气性及弹性，其主要具有耐温特性、耐候性、电气绝缘性、生理惰性、低表面张力和低表面能。树脂是指受热后有软化或熔融范围，软化时在外力作用下有流动倾向，常温下是固态、半固态，有时也可以是液态的有机聚合物。
S13：压合各层子体以固定子体和电感元件。
具体地，对第二线路层、第二可熔融介质层、各层子体层、若干层第一可熔融介质层以及第一线路层进行压合，以固定第二线路层、子体层、电感元件以及第一线路层。
在进行高温压合时，第一可熔融介质层会融化，进而将各子体层、第一线路层粘合在一起，第二可熔融介质层也会融化，将第二线路层与邻近的子体层粘合在一起。具有一定流动性的第一可熔融介质层部分进入槽体，与融化的第二介质层结合，固化后形成一体结构。
参阅图6，步骤如下：
S21：提供电感元件和至少两层带相同位置槽体的子体。
与前一实施例相同，此处不再赘述。
S22：将电感元件置入第一层子体的槽体中。
与前一实施例相同，此处不再赘述。
S23：将若干层第一可熔融介质层以及剩余子体依次交替层叠套设在电感元件上，第一线路层盖设在最外侧的第一可熔融介质层上。
在盖设最外层第一可熔融介质层前，可在电感元件与槽体的侧壁之间加入第二介质层，以使电感元件更加稳固地与槽体侧壁粘合。
S24：对第一线路层、若干层第一可熔融介质层以及各层子体层进行第一次压合。
第一线路层、各第一可熔融介质层、子体层以及盖设完成后，进行第一次压合，高温压合过程中，第一可熔融介质层受热融化，将各相邻子体层以及第一线路层粘合在一起，第二介质层也受热融化，将电感元件与槽体侧壁粘合在一起，且部分第一可熔融介质层进入槽体与第二介质层粘合，冷却后，各第一可熔融介质层与第二介质层形成一体结构。第一线路层、子体以及电感元件被固定。
S25：将第二可熔融介质层、第二线路层依次盖设在第一层子体远离第一线路层的一侧。
将第二可熔融介质层盖设在第一层子体远离第一线路层的一侧，第二线路层盖设在第二可熔融介质层远离第一层子体的一侧。
S26：对第二线路层、第二可熔融介质层、各层子体层、若干层第一可熔融介质层以及第一线路层进行第二次压合。
完成第二可熔融介质层和第二线路层盖设，进行第二次压合，第二次高温压合过程中，各第一可熔融介质层与第二介质层再次融化，可以进一步将各子体层压合得更加紧凑，降低电路板的厚度，第二可熔融介质层融化，将第二线路层与第一层子体粘合起来。以固定第二线路层、子体层、电感元件以及第一线路层。
本申请的有益效果是：区别于现有技术的情况，本申请通过在相邻子体的对应位置分别开设相通的槽体，将电感元件嵌设在槽体内，且使电感元件与槽体的侧壁间隔设置，通过压合工艺压合，工艺步骤简洁方便，可以使得电路板结构紧凑，集成度高，且安全可靠。
以上仅为本申请的实施方式，并非因此限制本申请的专利范围，凡 是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种埋入式电路板的制作方法，其特征在于，包括：
    提供电感元件和至少两层子体，其中两层相邻的所述子体在对应位置分别开设有相通的槽体；
    将所述电感元件嵌设到电感框架上，以组成电感组件；
    将所述电感组件置入第一层所述子体的槽体中，并将所述电感组件与所述第一层所述子体粘合，其中，所述电感框架与所述槽体的侧壁之间的距离为80-120um；
    将剩余所述子体依次套设在所述电感元件上；
    压合各层所述子体以固定所述子体和所述电感元件。
  2. 一种埋入式电路板，其特征在于，所述埋入式电路板包括：
    至少一层子体，其中，所述子体的预设位置上开设有贯通的槽体；
    电感元件，嵌设在所述槽体内，且所述电感元件与所述槽体的侧壁间隔设置。
  3. 根据权利要求1所述的埋入式电路板，其特征在于，
    所述子体的数量大于等于2；
    相邻两层所述子体之间设有可熔融介质层，至少两层所述子体在利用所述槽体套设在所述电感元件后，通过所述可熔融介质层层叠压合而成，至少部分所述可熔融介质层流入所述电感元件与所述槽体的侧壁之间并接触所述电感元件。
  4. 根据权利要求2所述的埋入式电路板，其特征在于，
    所述可熔融介质层的厚度为40-300um；
    所述子体是无铜芯板层，所述无铜芯板层的厚度为200-500um。
  5. 根据权利要求2所述的埋入式电路板，其特征在于，所述埋入式电路板还包括：
    第一线路层和第二线路层，且所述第一线路层、所述第二线路层分别覆盖所述槽体的相对两侧，使得所述电感元件位于所述第一线路层和所述第二线路层之间；
    所述电感元件具有连接端子，所述电感元件的连接端子与所述第一 线路层和/或所述第二线路层电连接。
  6. 根据权利要求4所述的埋入式电路板，其特征在于，所述第一线路层和/或所述第二线路层上设有激光通孔，所述激光通孔中设有导电柱；
    所述电感元件的连接端子通过所述导电柱连接第一线路层和/或所述第二线路层。
  7. 根据权利要求4所述的埋入式电路板，其特征在于，
    所述子体及所述可熔融介质层的对应位置均开设有用于层间连接的导电孔；
    所述第一线路层和所述第二线路层与所述导电孔的对应位置上设有导电盲孔；
    其中，所述电感元件的连接端子依序通过所述第一线路层的导电盲孔和所述导电孔与所述第二线路层的导电盲孔电连接。
  8. 根据权利要求4所述的埋入式电路板，其特征在于，所述埋入式电路板还包括：
    至少一个元器件，设置在所述第一线路层和/或第二线路层远离所述槽体的一侧上，通过所述第一线路层和/或所述第二线路层与所述电感元件电连接；
    其中，所述元器件为芯片、电容元件、电阻元件、电源器件中的至少一种。
  9. 根据权利要求1所述的埋入式电路板，其特征在于，
    所述子体的数量大于等于2；
    相邻两层所述子体之间填有第一介质层；
    所述电感元件与所述槽体的侧壁之间填有第二介质层；
    所述第一介质层和所述第二介质层经一次压合熔接。
  10. 根据权利要求2至9任一项所述的埋入式电路板，其特征在于，
    至少两层所述子体上设有标识图形以及定位孔，所述定位孔是由所述标识图形为基准而设置，所述定位孔用于将各层所述子体进行对准、准确地用通过各自所述槽体套在所述电感元件，再将所有所述子体压 合；
    或者，至少两层所述子体上设有标识图形，各层所述子体的槽体是由所述标识图形为基准而设置，且各层所述子体的槽体形状与尺寸相同，所述槽体用于将各层所述子体进行对准、准确地通过各自所述槽体套在所述电感元件，再将所有所述子体压合。
  11. 根据权利要求10所述的埋入式电路板，其特征在于，
    所述标识图形还用于定位所述电感元件的连接端子，可根据所述标识图形对第一层所述子体、邻近所述第一层所述子体的第一介质层进行激光打孔，并对所述第一线路层和/或第二线路层进行激光打孔，以使所述第一层所述子体、邻近所述第一层所述子体的第一介质层上形成激光通孔，所述第一线路层和/或所述第二线路层上也形成激光通孔。
  12. 根据权利要求10所述的埋入式电路板，其特征在于，
    所述标识图形的材料为可透X光材料。
  13. 根据权利要求1所述的埋入式电路板，其特征在于，
    所述电感元件的外部围设有电感框架，所述电感框架用于在所述子体利用所述槽体套设在所述电感元件的过程中辅助所述电感元件保持竖立的状态，以使所述电感元件始终与所述槽体的侧壁保持预设距离；
    其中，所述电感框架与所述槽体的侧壁之间的距离为80-120um。
  14. 一种埋入式电路板的制作方法，其特征在于，所述方法包括：
    提供电感元件和至少两层带相同位置槽体的子体；
    将所述电感元件置入至少两层所述子体的槽体内；
    压合各层所述子体以固定所述子体和所述电感元件；
    其中，所述电感元件与所述槽体的侧壁间隔设置。
  15. 根据权利要求14所述的方法，其特征在于，所述将所述电感元件置入至少两层所述子体的槽体内的步骤包括：
    将所述电感元件置入第一层所述子体的槽体中；
    将剩余所述子体依次套设在所述电感元件上。
  16. 根据权利要求15所述的方法，其特征在于，所述将所述电感元件置入第一层所述子体的槽体中步骤包括：
    将所述电感元件嵌设到电感框架上，以组成电感组件，其中，所述电感框架用于在所述子体利用所述槽体套设在所述电感元件的过程中辅助所述电感元件保持竖立的状态，以使所述电感元件始终与所述槽体的侧壁保持预设距离；
    将所述电感组件置入第一层所述子体的槽体中，并将所述电感组件与所述第一层所述子体粘合。
  17. 根据权利要求16所述的方法，其特征在于，所述将所述电感组件与所述第一层所述子体粘合的步骤包括：
    使用胶带粘合所述第一层所述子体底面以封堵所述第一层所述子体的槽体下端，将所述电感组件自所述第一层的顶端置入所述第一层的槽体并接触所述胶带；或者，
    使用热熔胶或胶水粘合所述电感组件与所述第一层所述子体。
  18. 根据权利要求15所述的方法，其特征在于，所述将剩余所述子体依次套设在所述电感元件上的步骤包括：
    将若干层第一可熔融介质层以及剩余所述子体依次交替层叠套设在所述电感元件上，第一线路层盖设在最外侧的所述第一可熔融介质层上；
    所述压合各层所述子体以固定所述子体和所述电感元件的步骤包括：
    对所述第一线路层、若干层所述第一可熔融介质层以及各层子体进行第一次压合，以固定所述第一线路层、所述子体以及所述电感元件；
    所述将剩余所述子体依次套设在所述电感元件上的步骤还包括：
    将第二可熔融介质层、第二线路层依次盖设在第一层所述子体远离所述第一线路层的一侧；
    所述压合各层所述子体以固定所述子体和所述电感元件的步骤还包括：
    对所述第二线路层、所述第二可熔融介质层、各层所述子体、若干层所述第一可熔融介质层以及所述第一线路层进行第二次压合，以固定所述第二线路层、所述子体、所述电感元件以及所述第一线路层。
  19. 根据权利要求15所述的方法，其特征在于，所述将剩余所述子体依次套设在所述电感元件上的步骤包括：
    将若干层第一可熔融介质层以及剩余所述子体依次交替层叠套设在所述电感元件上；
    将第一线路层盖设在最外侧的所述第一可熔融介质层上；
    将第二可熔融介质层、第二线路层依次盖设在第一层所述子体远离所述第一线路层的一侧；
    所述压合各层所述子体以固定所述子体和所述电感元件的步骤包括：
    对所述第二线路层、所述第二可熔融介质层、各层所述子体、若干层所述第一可熔融介质层以及所述第一线路层进行压合，以固定所述第二线路层、所述子体、所述电感元件以及所述第一线路层。
  20. 根据权利要求17或18所述的方法，其特征在于，所述方法还包括：
    根据所述子体上的标识图形对所述第一线路层和/或所述第二线路层进行激光打孔，以在所述第一线路层和/或所述第二线路层形成激光通孔，其中，所述子体上的标识图形与所述电感元件的连接端子对应设置；
    在所述激光通孔中设置导电柱，以使所述电感元件的连接端子通过所述导电柱连接第一线路层和/或所述第二线路层。
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