WO2003067656A1 - Carte de montage pour puce a semiconducteur, realisation correspondante, et module a semiconducteur - Google Patents
Carte de montage pour puce a semiconducteur, realisation correspondante, et module a semiconducteur Download PDFInfo
- Publication number
- WO2003067656A1 WO2003067656A1 PCT/JP2002/000973 JP0200973W WO03067656A1 WO 2003067656 A1 WO2003067656 A1 WO 2003067656A1 JP 0200973 W JP0200973 W JP 0200973W WO 03067656 A1 WO03067656 A1 WO 03067656A1
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- WIPO (PCT)
- Prior art keywords
- insulating resin
- semiconductor chip
- base material
- resin base
- conductive
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Definitions
- the present invention provides a circuit board suitable for mounting a semiconductor chip such as an IC chip on a wiring / turn provided on an insulating resin substrate, a method of manufacturing the circuit board, and a circuit board on which the semiconductor chip is mounted.
- the present invention relates to a semiconductor module formed by alternately stacking members. Conventional technology
- Japanese Patent Application Laid-Open No. 10-256429 discloses a package in which a semiconductor chip is embedded in a ceramic substrate.
- Such a package has a BGA structure in which a semiconductor chip is buried in a recess formed in a ceramic substrate, and the semiconductor chip is connected to a conductor circuit provided on the substrate by flip-chip mounting.
- heat dissipation from a semiconductor chip can be improved, and that it is possible to cope with narrow pitch wiring.
- a ceramic substrate in which a semiconductor chip according to the prior art described above is embedded is used as a package substrate, and is used to connect a terminal on a semiconductor chip side formed at a fine pitch to a printed circuit board.
- the drawn wiring is to be electrically connected to an external board via solder poles (BGA) and pins (PGA), and therefore, it is not recognized that such a board is laminated. It is not a structure that allows the stacking of semiconductor chips by stacking substrates. Therefore, even if they are stacked, there is a problem that peeling or the like occurs in the connection between the substrates, and the electrical connection and reliability are reduced.
- a technique of manufacturing a semiconductor module in which IC chips are stacked is disclosed in, for example, JP-A-9-219490 and JP-A-10-135267.
- Japanese Patent Application Laid-Open No. H10-163341 discloses such a conventional technology.
- Examples of such a conventional technology include a TSOP (Thin Small Outline Package), a TCP (Tape Carrier Package), and a BGA (Ball Grid Array).
- TSOP Thin Small Outline Package
- TCP Transmission Carrier Package
- BGA All Grid Array
- FIG. 1 and FIG. 2 show a stacked package manufactured by the above-described conventional technique.
- Fig. 1 shows a stack of packages molded with resin.
- Fig. 2 (a) and Fig. 2 (b) show side and plan views of the module board on which the stacked package of Fig. 1 is mounted.
- the OOA and 10OB include an IC mounting section 106, an IC chip 102 mounted on the upper surface thereof, leads 101 for connecting the IC chip 102 to external components, and leads to the IC chip 102.
- ⁇ C package 100A On top of the ⁇ C package 100A having such a structure, another IC package 100B is stacked and mounted on the substrate 105.
- the upper and lower packages 100A and 100B are connected to the substrate 105 by their respective leads 101, if a misalignment occurs when the packages 100A and 100B are stacked, a short circuit occurs between the leads ⁇ 01. There was a risk of doing so.
- the present invention has been made in view of the above-mentioned problems of the conventional technology, and its main purpose is to make sure that electrical connection with a semiconductor chip can be made and to draw out from the semiconductor chip. It is an object of the present invention to provide a semiconductor chip mounting substrate capable of further stacking the wirings.
- Another object of the present invention is to propose a method of manufacturing a semiconductor chip mounting substrate having excellent connection reliability.
- Still another object of the present invention is to provide a semiconductor module which is obtained by alternately laminating a substrate on which a semiconductor chip is mounted and an interlayer member and hot-pressing them, and which is capable of achieving high-density and thinning and having excellent connection reliability. Is to provide.
- the present inventors have conducted intensive studies in order to achieve the above-mentioned object, and as a result, instead of a conventional configuration in which a semiconductor chip is molded with a resin, a circuit board on which the semiconductor chip is mounted in advance, By alternately laminating an interlayer member having an opening capable of accommodating a semiconductor chip through an adhesive layer and hot-pressing the laminated body, the semiconductor chip is embedded in the opening of the interlayer member, and By ensuring electrical connection between semiconductor chips via via holes or conductor posts formed in interlayer members, the distance between semiconductor chips can be shortened, and problems due to wiring resistance and inductance can be reduced. As a result, it has been found that electric signals can be transmitted at high speed without delay, and that the wiring board can be made denser, more functional, and thinner. And conceived the present invention to the following contents and gist configuration. Disclosure of the invention
- the substrate for mounting a semiconductor chip of the present invention has, on one surface side of an insulating resin base material, a region for mounting a semiconductor chip almost at the center thereof, and a first conductive material in the mounting region.
- a bump is formed, and a wiring pattern is extended from the first conductive bump toward the periphery of the insulating resin base material.
- the wiring pattern is formed on the other surface of the insulating resin base material.
- a via hole filled with a conductive substance is provided in an opening reaching the via, and a via hole electrically connected to the via hole and protruding from the other surface of the insulating resin base material is provided.
- a semiconductor chip mounting substrate provided with 2 conductive bumps,
- a conductive bump for mounting a semiconductor chip is formed at a substantially central portion thereof, and the conductive bump extends from the conductive bump to a peripheral portion of the insulating resin base material.
- a wiring pattern extending toward the wiring pattern is provided on the other surface of the insulating resin base material, and a via hole formed by filling a conductive material in an opening reaching the wiring pattern is provided, and the via hole is formed.
- This is a semiconductor chip mounting substrate provided with conductive pads electrically connected to the semiconductor chip.
- a part of the wiring pattern is formed in the form of a conductive pad.
- a wiring pattern is formed not only on one surface side of the insulating resin base material but also on the other surface side, and electrically connected to the conductor pads located immediately above the via holes. It is desirable to be connected, that is, it is desirable to form a wiring pattern on both sides of the insulating resin base material.
- the via hole may be selected from Cu, Sn, Pb, Ag, Au, Zn, In, Bi, solder, and a tin alloy. It is desirable that both are formed from one kind of metal.
- the via hole should be formed to include at least a metal having a lower melting point than copper. It is preferable to form a two-layer structure by filling electrolytic copper plating near the bottom and filling electrolytic plating of a metal having a lower melting point than copper in the portion near the opening end. Further, the via hole is preferably formed by electrolytic plating or electroless plating, and is particularly preferably formed by electrolytic plating.
- the conductive bump is at least one selected from Cu, Sn, Pb, Ag, Au, Zn, In, B solder or a tin alloy. It is desirable to be formed of one kind of metal, and it is also desirable to form these metals by electrolytic plating or electroless plating.
- first conductive bump for mounting the semiconductor chip and the second conductive bump for connection with the interlayer member may be formed of the same metal, or may be formed of metals having different melting points. You may. In particular, it is desirable that the first conductive bump has a lower melting point than the second conductive bump and is formed of metal. The melting point is preferably in the range of 150 to 240 ° C.
- an adhesive layer is formed on the other surface of the insulating resin base material. It is preferably at least one resin selected from a resin, a thermosetting polyphenylene ether, a composite resin of an epoxy resin and a thermoplastic resin, a composite resin of an epoxy resin and a silicone resin, and a BT resin.
- a roughened layer is formed on the surface of the wiring pattern.
- a first conductive bump for mounting a semiconductor chip disposed at a substantially central portion of the base material is formed on a wiring pattern formed on one surface of the insulating resin base material;
- a semiconductor chip mounting substrate is provided in which an opening reaching the wiring pattern from the other surface is provided with a via hole filled with a conductive material, and a second conductive bump is provided on the via hole.
- a light-transmitting resin film is attached to the other surface of the insulating resin substrate with copper foil attached to one surface, and the other surface of the insulating resin substrate is irradiated with laser from above the resin film. Forming an opening reaching the copper foil and cleaning the resin residue in the opening.
- the insulating resin base material obtained in the step ⁇ is subjected to electrolytic plating treatment, and the opening is filled with the electrolytic plating film in the opening, and the second electrode corresponding to the terminal position of the semiconductor chip to be mounted is mounted. Forming a conductive bump of 1,
- an etching resist layer corresponding to a predetermined wiring pattern extending from the first conductive bump toward the peripheral portion of the insulating resin base material is formed. Forming the predetermined wiring pattern by removing the copper foil portion where the etching resist layer has been formed and not present by etching.
- a first conductive bump for mounting a semiconductor chip disposed at a substantially central portion of the base is formed on a wiring pattern formed on one surface of the insulating resin base, and the first conductive bump is formed on the wiring pattern.
- a via hole filled with a conductive material is provided in an opening reaching the wiring pattern from the other surface of the insulating resin substrate, and a second conductive hole is located immediately above the via hole and protrudes from the other surface of the insulating resin base material.
- electrolytic copper plating is applied to fill the openings with an electrolytic plating film to form via holes and then electrolytic sprinkling.
- Forming a plating resist layer having an opening corresponding to a terminal position of a semiconductor chip to be mounted;
- An electrolytic sprinkling process is performed on the insulating resin base material to fill the opening of the plating resist layer with an electrolytic sprinkling film, and the first conductive film corresponding to the terminal position of the mounted semiconductor chip is formed. Forming a conductive bump,
- an etching resist layer corresponding to a predetermined wiring pattern extending from the first conductive bump toward the peripheral portion of the insulating resin base material is formed, Removing the copper foil portion where the etching resist layer is not formed by an etching process to form the wiring pattern;
- a conductive bump for mounting a semiconductor chip is formed almost in the center, and the conductive bump force and the wiring pattern toward the periphery of the insulating resin base material are formed.
- a via hole including a conductive substance filled in an opening reaching the wiring pattern is provided, and is electrically connected to the via hole.
- An opening that reaches the copper foil from the other side of the insulating resin base material with the copper foil adhered to one side is formed, and the opening is filled with an electrically conductive material to form a via hole, and the conductive property is increased.
- ⁇ a step of forming the predetermined wiring pattern by removing a portion of the copper foil where the etching resist layer is not formed by an etching process
- a conductive bump for forming a semiconductor chip is formed at the approximate center of the surface, and wiring / turning is performed from the conductive / amplifier to the peripheral portion of the insulating resin base material.
- a via hole including a conductive material filled in an opening reaching the wiring pattern is provided, and is electrically connected to the via hole.
- An electrolytic plating process is performed while a protective film is adhered to the other surface of the insulating resin base material, and the openings are filled with an electrolytic plating film so that a conductive film corresponding to the terminal position of the mounted semiconductor chip is provided. 3 ⁇ 4 process to form a flexible bump,
- the conductive bumps extend from the conductive bumps toward the periphery of the insulating resin base material.
- An etching resist layer corresponding to a predetermined wiring pattern extending is formed. Forming an etching resist layer corresponding to a predetermined wiring pattern including a conductive pad located immediately above the via hole on the copper foil adhered to the other surface of the insulating resin base material.
- the one surface side of the insulating resin base material is moved from the conductive bump to the peripheral portion of the insulating resin base material. Forming a predetermined wiring pattern extending toward the substrate, and forming a predetermined wiring pattern including a conductive pad on the other surface side of the insulating resin base material;
- the semiconductor module of the present invention comprises:
- a first conductive bump on which the semiconductor chip is mounted is formed substantially at the center of one surface of the insulating resin base material, and is extended from the conductive bump to the peripheral portion of the insulating resin base material.
- a via hole made of a conductive material filled in an opening reaching the wiring pattern from the other surface of the insulating resin substrate is formed, and a second hole is formed immediately above the via hole.
- An opening capable of accommodating the semiconductor chip is formed substantially at the center of the insulating resin base material, and a conductive hole is formed in a peripheral portion of the insulating resin base material in a through hole passing through the insulating resin base material.
- a first conductive bump on which the semiconductor chip is mounted is formed substantially at the center of one surface of the insulating resin base material, and is extended from the conductive bump to the peripheral portion of the insulating resin base material.
- a via hole made of a conductive material filled in an opening reaching the wiring pattern from the other surface of the insulating resin base material is formed, and a conductive pad is located immediately above the via hole.
- a semiconductor chip mounting substrate formed with An opening for accommodating the semiconductor chip is formed substantially at the center of the insulating resin base material, and at the periphery of the insulating resin base material, in a through hole penetrating the insulating resin base material.
- a semiconductor module characterized by being alternately laminated via an adhesive layer, and manufactured by hot-pressing the laminated body
- a first conductive bump for mounting a semiconductor chip is formed substantially at the center of one surface of the insulating resin base material, and a wiring pattern extending from the conductive bump to a peripheral portion of the insulating resin base material is formed.
- a via hole made of a conductive material filled in an opening reaching the wiring pattern from the other surface of the insulating resin base material is formed, and a second conductive film is located immediately above the via hole.
- An opening capable of accommodating the semiconductor chip is formed substantially at the center of one surface of the insulating resin base material, a predetermined wiring pattern is formed on the periphery of the insulating resin base material, An opening reaching the wiring pattern from the other surface is formed with a via hole filled with a conductive substance, and an interlayer member formed immediately above the via hole and having a conductive bump formed thereon.
- It is characterized by being manufactured by alternately laminating via an adhesive and hot pressing the laminated body.
- the semiconductor chip mounting substrate is formed of a hard insulating resin base material
- the interlayer member is formed of a hard insulating resin base material or an uncured base material. It is desirable to be formed from prepreg.
- a part of the wiring pattern corresponding to the via hole is desirably formed in the form of a conductive pad.
- the semiconductor chip mounting substrate has a wiring pattern formed not only on one surface but also on the other surface, and is connected to a conductor pad immediately above the via hole.
- the via hole is desirably formed of at least one metal selected from Cu, Sn, Pb, Ag, Au, Zn, In, Bi, solder, and tin alloy.
- the via hole be formed to include at least a metal having a melting point lower than that of copper. It is preferably formed of two layers: copper plating and electrolytic plating of a metal having a lower melting point than copper filled near the opening end.
- the via hole is preferably formed by electrolytic plating or electroless plating, more preferably by electrolytic plating, particularly preferably by electrolytic copper plating. It is.
- the conductive bump is made of at least one metal selected from Cu, Sn, Pb, Ag, Au, Zn, In, Bi, solder, and a tin alloy. It is desirable to be formed from these.
- the conductive bump is formed by electrolytic plating or electroless plating, and particularly, electrolytic tin plating or electrolytic solder plating is a preferred embodiment.
- the first and second conductive bumps may be formed from the same metal, or may be formed from metals having different melting points. In particular, it is desirable that the first conductive bump is formed of a metal having a lower melting point than that of the second conductive bump.
- the first and second conductive bumps preferably have a melting point in the range of 150 to 240 ° C.
- an adhesive layer be formed on the other surface of the substrate for mounting a semiconductor chip. Also, it is desirable that an adhesive be formed on one or both surfaces of the interlayer member.
- These adhesives are selected from epoxy resin, polyimide resin, thermosetting polyphenylene ether, composite resin of epoxy resin and thermoplastic resin, composite resin of epoxy resin and silicone resin, and BT resin. Desirably, at least one resin is used.
- the through-hole provided in the interlayer member is formed in a substantially truncated cone shape, and the conductor post protruding from the through-hole has one aperture. Is desirably formed smaller than the other diameter.
- the through-hole provided in the interlayer member is formed into a shape such that a small-diameter cylinder and a large-diameter cylinder are coaxially joined, and the conductor post protruding from the through-hole is formed on one side. Is desirably formed smaller than the other.
- the ratio between one diameter of the conductor post and the other diameter is 1: 2 to 1: 3.
- FIG. 1 is a schematic side sectional view of an IG package according to the prior art.
- FIG. 2 (a) is a schematic side view of a substrate on which a conventional IG package is mounted
- FIG. 2 (b) is also a schematic plan view.
- FIGS. 3 (a) to 3 (e) are views showing a part of the manufacturing process of the semiconductor chip mounting substrate according to the first embodiment of the present invention.
- FIG 4 (j) are views showing a part of the manufacturing process of the semiconductor chip mounting board according to the first embodiment.
- FIG. 5 is a schematic explanatory view for explaining mounting of a semiconductor chip on a mounting substrate.
- 6 (a) to 6 (a) are diagrams showing a part of a manufacturing process of an interlayer member to be laminated together with the semiconductor chip mounting substrate in the first embodiment.
- FIG. 7 (a) is a perspective view showing a state in which the semiconductor chip mounting board, the interlayer member, and the I / O wiring board according to the first embodiment are stacked
- FIG. 7 (b) is a perspective view showing FIG. FIG. 3 is a cross-sectional view showing a semiconductor module manufactured by hot-pressing the laminate shown in FIG.
- 8 (a) to 8 (a) to 8 (c) are views showing a part of a manufacturing process of an interlayer member used in Embodiment 2 of the present invention.
- FIG. 9 (a) is a perspective view showing a state in which the semiconductor chip mounting board, the interlayer member, and the I / O wiring board according to the second embodiment are stacked
- FIG. 9 (b) is a perspective view showing FIG. 9 (a).
- FIG. 3 is a cross-sectional view showing a semiconductor module manufactured by hot-pressing the laminate shown in FIG.
- FIGS. 10 ( a ) to 10 (W) are views showing a part of a manufacturing process of an interlayer member used in Embodiment 3 of the present invention.
- FIG. 11 (a) is a perspective view showing a state in which a semiconductor chip mounting circuit board, an interlayer member, and an I / O wiring board according to Example 3 are stacked
- FIG. FIG. 1 is a cross-sectional view showing a semiconductor module manufactured by heating and pressing the laminate shown in FIG.
- FIGS. 12 (a) to 12 (e) are views showing a part of a manufacturing process of a semiconductor chip mounting substrate according to a fourth embodiment of the present invention.
- FIG. 13 to 13 are views showing a part of the manufacturing process of the semiconductor chip mounting board according to the fourth embodiment.
- FIG. 14A is a perspective view showing a state in which the semiconductor chip mounting board, the interlayer member, and the I / O wiring board according to the fourth embodiment are stacked
- FIG. FIG. 4 is a cross-sectional view showing a semiconductor module manufactured by heating and pressing the laminate shown in FIG.
- FIGS. 15 (a) to (e) are views showing a part of a manufacturing process of a semiconductor chip mounting substrate according to a sixth embodiment of the present invention.
- FIGS. 16 (f) to (i) are views each showing a part of a manufacturing process of a semiconductor chip mounting board according to the sixth embodiment.
- FIG. 17 (a) is a perspective view showing a state in which the semiconductor chip mounting board, the interlayer member and the I / O wiring board according to the sixth embodiment are stacked
- FIG. FIG. 4 is a cross-sectional view showing a semiconductor module manufactured by heating and pressing the laminate shown in FIG.
- FIGS. 18 (a) to 18 (f) are views showing a part of a manufacturing process of an interlayer member used in Embodiment 7 of the present invention.
- FIG. 19 to FIG. 22 are views showing a part of a process of manufacturing a semiconductor module from the semiconductor chip mounting board, the interlayer member, and the copper foil according to the seventh embodiment.
- the feature of the substrate for mounting a semiconductor chip according to the present invention is that, in a state where a semiconductor chip such as an IC chip is mounted on conductive bumps in advance, it is laminated and pressed together with an interlayer member having an opening capable of accommodating the semiconductor chip.
- an interlayer member having an opening capable of accommodating the semiconductor chip.
- a semiconductor chip mounting area is provided at substantially the center of one surface of the insulating resin substrate, A large number of conductive bumps for mounting (hereinafter, referred to as r first conductive bumps J) are formed around the mounting area, and are electrically connected to the first conductive bumps.
- the wiring pattern extends from the mounting area toward the periphery of the substrate.
- an opening reaching the wiring pattern from the other surface of the insulating substrate is provided, and a filled via hole filled with a conductive substance is formed in the opening, and an interlayer member is provided immediately above the via hole.
- a conductive bump for connection to be electrically connected (hereinafter, referred to as a “second conductive bump”) is formed.
- a circuit board on which such a semiconductor chip is mounted is alternately laminated with an interlayer member having an opening capable of accommodating the semiconductor chip to form a multilayer, and, if necessary, a mother board for the outermost layer.
- an interlayer member having an opening capable of accommodating the semiconductor chip to form a multilayer, and, if necessary, a mother board for the outermost layer.
- I / O wiring boards such as I / O wiring boards
- a substrate on which a semiconductor chip mainly having an arithmetic function is mounted is arranged on the surface side, and a substrate on which a semiconductor chip mainly having a memory function is mounted is arranged on the inner layer side.
- an electric connection between the semiconductor chips is provided. This is carried out by laminating and hot-pressing the members in a state where the interlayer members provided through the conductive passages for electrical connection are arranged.
- an opening capable of accommodating a semiconductor chip is provided at a substantially central portion of the insulating resin base material, and is filled in a through hole provided through the insulating resin base material.
- a preferred embodiment is an interlayer member in which a via hole is formed by filling a conductive material in the opening to be formed, and a conductive bump is formed immediately above the via hole.
- the semiconductor chip mounted via the first conductive bump of the mounting substrate is housed in the opening of the adjacent interlayer member. It is connected to a conductor post or via hole provided in the interlayer member through a buried wiring pattern, a via hole, and a second conductive bump extending toward the peripheral portion of the substrate, and further connected to the semiconductor of the adjacent mounting substrate. Since the semiconductor chip is connected to the chip, the distance between the semiconductor chips is reduced, and defects due to wiring resistance and inductance are reduced. As a result, electric signals can be transmitted at high speed without delay.
- the semiconductor module formed by laminating the layers and the interlayer member has substantially the same configuration as that of the first embodiment.
- a wiring pattern is formed on one surface of an insulating resin base material,
- the semiconductor chip mounting region has a connection region for making an electrical connection with another circuit board, and an opening is formed to reach the wiring pattern from the semiconductor chip mounting region and the connection region, respectively.
- a via hole including a conductive material filled in the opening is formed.
- a first conductive bump for mounting a semiconductor chip and a second conductive bump electrically connected to another circuit board are respectively provided just above the via hole, and are provided, respectively.
- the wiring pattern is formed so as to extend from the center of the insulating resin base material to the peripheral portion so as to electrically connect the via holes corresponding to the first and second conductive bumps.
- both the first and second conductive bumps are formed on the surface of the insulating resin substrate opposite to the surface on which the wiring pattern is formed.
- the first conductive bump on which the semiconductor chip is mounted is connected to the wiring bump through a via hole immediately below the first conductive bump.
- the wiring pattern is extended from the center to the periphery of the insulating resin base material, and is electrically connected to the via hole corresponding to the second conductive bump.
- an opening capable of accommodating a semiconductor chip is provided substantially at the center of one surface of the insulating resin base material.
- a predetermined wiring pattern including at least a conductive pad is formed in a peripheral portion, and a via hole formed by filling a conductive material into an opening reaching the wiring pattern from the other surface of the insulating resin base material is formed. It is desirable to use an interlayer member having a conductive bump formed immediately above the via hole.
- the insulating resin substrate used for the semiconductor chip mounting substrate of the present invention can be used as long as it is an organic insulating resin substrate.
- a hard insulating resin base material is formed from a completely hardened resin material rather than a conventional semi-cured prepreg, the use of such a material allows the hard insulating resin base material to be formed on the insulating resin base material.
- the final thickness of the insulating resin substrate does not fluctuate due to the pressing pressure, so that the via hole displacement can be minimized and the via land diameter can be reduced. Therefore, the wiring density can be improved by reducing the wiring pitch, and the thickness of the base material can be kept substantially constant, so that the opening for forming the filled via hole is formed by laser processing. The laser irradiation conditions can be easily set.
- a copper foil is adhered to one surface of the insulating resin base material via an appropriate resin adhesive, and a wiring pattern is formed by an etching process described later.
- a single-sided copper-clad laminate in which the copper foil is stuck on the insulating resin substrate in advance can be used.
- the copper foil adhered on the insulating resin base material is subjected to a mat treatment so as to improve the adhesion and prevent the laminated substrate from warping.
- Single-sided copper clad product The use of a laminated plate is the most preferred embodiment.
- the above single-sided laminated board is made by impregnating a glass cloth with a thermosetting resin such as epoxy resin base material, phenol resin, and bismaleimide-triazine resin, and laminating a prepreg and copper foil as a B stage and heating and pressing. This is a substrate obtained by pressing.
- This single-sided copper clad laminate is a rigid substrate, and is easy to handle and most advantageous in cost.
- a metal layer can be formed on the surface of the insulating resin substrate by vapor deposition of a metal and then using electrolytic plating.
- the thickness of the insulating resin substrate is from 10 to 200 m, preferably from 15 to "! 00 j! Im, and most preferably from 20 to 80 / m. This is because if it is too thick, it is difficult to form a fine opening and fill it with a conductive substance, and it is not possible to reduce the thickness of the laminated semiconductor module.
- the thickness of the copper foil forming the wiring pattern is 5 to 36 ⁇ m, preferably 8 to 30 ⁇ m, and more preferably 12 to 25) U m, the reason of which will be described later. As described above, when the opening for forming the via hole is formed by laser processing, if the opening is too thin, the hole penetrates. On the other hand, if the opening is too thick, it is difficult to form a fine pattern by etching.
- the via hole forming opening (opening) is formed by adhering a light-transmitting resin film to the surface of the insulating resin substrate opposite to the surface to which the copper foil is attached, and irradiating the resin film with laser. .
- the resin film provided with the opening by the laser irradiation functions as a printing mask when a conductive paste is filled in the opening reaching the foil from the surface of the insulating resin base material to form a via hole,
- a conductive material is filled in the opening and a conductive bump is formed immediately above the surface of the via hole, it functions to adjust the protruding height of the bump. It is desirable to have a pressure-sensitive adhesive layer that can be separated from the adhesive layer.
- the resin film is formed, for example, from a polyethylene terephthalate resin film (hereinafter, referred to as ⁇ film) in which the thickness of an adhesive layer is 1 to 20 / m and the thickness of the film itself is 10 to 50 / m. Preferably.
- ⁇ film polyethylene terephthalate resin film
- the amount of protrusion of the conductive bumps from the surface of the insulating resin substrate depends on the thickness of the PET film. If the thickness is less than 10 // m, the amount of protrusion is too small and the connection is poor. To On the contrary, if the thickness exceeds 50 m, the fine conductive pattern cannot be formed because the molten conductive bumps spread too much at the connection interface.
- the laser processing machine a carbon dioxide laser processing machine, a UV laser processing machine, an excimer laser processing machine, or the like can be used.
- the carbon dioxide laser processing machine is most suitable for industrial use because it can be processed at a high processing speed and at a low price, and is the most desirable laser processing machine for the present invention.
- the diameter of the opening formed in the insulating resin base material having a thickness in the above range by such a carbon dioxide laser is desirably in the range of 50 to 200 ⁇ m.
- the pulse energy is 0.5 to 100 mJ
- the pulse width is "! To 100 is
- the pulse interval is 0.5 ms or more
- the number of shots is 3 to 50.
- the opening diameter is limited is that if it is less than 50 m, it is difficult to fill the opening with conductive paste and the connection reliability is low.If it exceeds 200 jUm, the density increases. Is difficult.
- desmear treatment Before filling the opening with a conductive substance to form a via hole, desmear treatment to remove resin residue remaining on the inner wall surface of the opening, for example, immersion in an oxidizing agent such as acid, permanganic acid, or chromic acid It is desirable from the point of connection reliability to perform treatment by a chemical removal method that uses a chemical removal method or a physical removal method that uses plasma discharge or corona discharge.
- the adhesive layer or the protective film is stuck on the insulating resin substrate, it is preferable to perform dry desmear treatment using plasma discharge or corona discharge, for example.
- plasma cleaning using a plasma cleaning device is particularly preferable.
- an opening for forming a via hole by laser processing but it is also possible to make a hole by a mechanical method such as drilling and punching.
- a method of forming a via hole by filling a conductive substance in the opening subjected to the desmear treatment there are a plating filling method by plating and a method of filling conductive paste.
- plating filling take measures to prevent contact with the plating solution by attaching a protective film in advance to prevent plating from depositing on the copper foil on the insulating resin material.
- the inside is filled with plating to form via holes.
- the above-mentioned plating filling can be performed by either an electrolytic plating treatment or an electroless plating treatment, but the electrolytic plating treatment is desirable.
- electrolytic plating for example, metals such as Sn, Pb, Ag, Au, Cu, Zn, In, Bi, solder and tin alloy can be used, and electrolytic copper plating is particularly preferable.
- the above-mentioned electrolytic plating may be filled with a single metal, but first the electrolytic copper plating is filled into the opening and filled to the vicinity of the opening end, and then the remaining space in the opening is filled with a metal having a lower melting point than copper.
- a metal having a lower melting point than copper For example, it can be filled with electrolytic tin plating or electrolytic soldering.
- electrolytic plating is performed using copper foil formed on the insulating resin substrate as a plating lead. Since this copper foil (metal layer) is formed over the entire surface of one surface of the insulating resin base material, the current density becomes uniform, and the opening is filled with electrolytic plating at a uniform height. Can be.
- the surface of the metal layer in the opening may be activated with an acid or the like.
- the electrolytic plating (metal) that has risen outward from the surface of the insulating resin substrate is polished and removed by a belt sander, puff polishing, or the like, and is flattened or removed from the surface of the insulating resin substrate. Can also be left slightly higher.
- a conductive paste composed of one or more metal particles selected from silver, copper, gold, nickel, and various solders can be used.
- metal particles those obtained by coating the surface of the metal particles with a dissimilar metal are also used. Can be used. Specifically, metal particles obtained by coating copper particles with a noble metal such as gold or silver can be used.
- the conductive paste an organic conductive paste obtained by adding a thermosetting resin such as an epoxy resin or a polyphenylene sulfide (PPS) resin to metal particles is preferable.
- a thermosetting resin such as an epoxy resin or a polyphenylene sulfide (PPS) resin
- PPS polyphenylene sulfide
- the conductive bumps formed on the exposed surfaces of the via holes are bumps for securing electrical connection with interlayer members (hereinafter referred to as “second conductive bumps J”), and are subjected to plating treatment or conductive bumps. It is formed by printing a conductive paste. At this time, it is preferable that the opening formed in the protective film by laser irradiation is formed by filling a plating having a height related to the thickness of the protective film by plating.
- the above-mentioned plating filling can be performed by either an electrolytic plating treatment or an electroless plating treatment, but the electrolytic plating treatment is desirable.
- electrolytic plating for example, Sn, Pb, Ag, Au, Cu, Zn, In, Bi, solder, a tin alloy or the like can be used, and electrolytic plating is preferable.
- the height of the second conductive bump is preferably in the range of 3 to 60 #m. The reason is that if it is less than 3 / im, variations in the height of the bump cannot be tolerated due to deformation of the bump, and if it exceeds 60 m, the resistance value will be high and the bump will not be formed when the bump is formed. This is because it spreads in the direction and causes a short circuit.
- the second conductive bump can be formed by filling a conductive paste into an opening formed in the protective film by laser irradiation instead of the plating process.
- variations in the height of electroplating can be corrected by adjusting the amount of the conductive paste to be filled, and the heights of a large number of conductive bumps can be made uniform.
- the bump made of the conductive paste is preferably in a semi-cured state. This is because the conductive paste can penetrate the softened organic adhesive layer during hot pressing that is hard even in a semi-cured state.
- the contact area increases due to deformation during hot pressing, and the variation in bump height, which can only reduce the conduction resistance, can be corrected. You.
- the conductive bumps can be formed by a method of dipping in a solder melt.
- Pb-Sn solder As the low melting point metal, Pb-Sn solder, Ag-Sn solder, indium solder and the like can be used.
- first conductive bumps J for mounting semiconductor chips such as IC chips, which are formed on the surface (metal layer) of the insulating resin substrate on which the copper foil is adhered, It can be performed by plating treatment, printing of a conductive paste, snorting, or the like, but is preferably performed by plating.
- a photosensitive dry film or apply a liquid photosensitive resist to the copper foil application surface of the insulating resin substrate, and then make an electrical connection with the semiconductor chip by mask exposure and development processing.
- a plating resist layer having an opening for forming a bump is formed, and the bump is formed in the opening by plating.
- the non-pump formation by the above-mentioned plating can be performed by either electrolytic plating or electroless plating, but electrolytic plating is desirable.
- electrolytic plating for example, Sn, Pb, Ag, Au, Cu, Zn, In, Bi, solder or a tin alloy can be used, and electrolytic plating is the most preferred embodiment.
- the shape of the first conductive bump a cylinder, an elliptical cylinder, a rectangular parallelepiped, or a cube can be adopted, and the height is desirably in the range of 1 to 30 // m.
- the reason is that if the length is less than 1 m, the conductive bump cannot be formed uniformly, and if it exceeds 30 m, the occurrence of migration whiskers increases. In particular, a height of 5 im is most preferable.
- the diameter is preferably in the range of 50 to 200 m, and most preferably 80 ⁇ m.
- the plating resist layer is completely removed using an alkali such as NaOH or KOH, an acid such as sulfuric acid, nitric acid, acetic acid, or a solvent such as alcohol. You.
- the first conductive bump is preferably formed by electrolytic sprinkling similarly to the second conductive bump from the viewpoint of easy temperature control, but the first conductive bump is formed by the second conductive bump. It can also be formed of a metal having a lower melting point than the conductive bump. The melting point of such a metal is desirably in the range of 150 to 240 ° C.
- the semiconductor chip must be mounted. This is advantageous in that only the first conductive bump can be melted and the shape of the second conductive bump can be maintained.
- the wiring pattern formed on the surface of the insulating resin substrate to which the copper foil is to be adhered is obtained by attaching a photosensitive dry film to the copper foil surface or applying a liquid photosensitive resist and then mounting a mask having a predetermined wiring pattern. After forming a plating resist layer by placing and exposing and developing, a copper foil in a portion where an etching resist is not formed is etched.
- the above wiring pattern is composed of a number of conductor pads (lands) formed corresponding to the terminals of the semiconductor chip mounted at the substantially central part of the substrate, and fine fine pads extending therefrom toward the outer periphery of the substrate. It has an outer lead with a line width and a number of conductor pads (lands) formed corresponding to via hole positions near the end of the outer lead.
- the first conductive bump is formed, and the latter pad is connected to a conductive post or a conductive bump of the laminated interlayer member, as described later.
- the wiring pattern preferably has a thickness of 12 m, preferably 5 to 30 // m. Further, it is desirable that the ratio (1_0) between the line width and the line distance is 50 1 150 // ⁇ 100 m / 100 / m. Further, the land formed on the wiring pattern preferably has a diameter of 150-500 ⁇ m, and more preferably 350 ⁇ m.
- the etching for forming the pattern is performed with at least one selected from aqueous solutions of sulfuric acid and hydrogen peroxide, persulfate, cupric chloride and ferric chloride.
- a roughened layer can be formed on the surface of the wiring pattern.
- the adhesiveness of the adhesive layer for bonding the mounted circuit board and the interlayer member can be improved, and the occurrence of delamination can be prevented.
- the roughening treatment includes, for example, soft etching treatment, blackening (oxidation) -reduction treatment, formation of an acicular alloy made of copper-nickel-phosphorus (interplate, trade name, manufactured by Ebara Uzilite), manufactured by MEC Corporation. ⁇ Mech Etch Bond J It is desirable to roughen the surface with an etchant.
- a metal layer may be further coated on the wiring pattern on which the roughened layer has been formed.
- the metal to be formed may be coated with any metal selected from titanium, aluminum, zinc, iron, indium, thallium, cobalt, nickel, tin, lead and bismuth.
- the thickness of the coating metal layer is preferably in the range of 0.01 to 3 #. The reason is that if it is less than 0.01 ⁇ m, it may not be possible to completely cover the roughened layer.If it exceeds 3 / m, the concave portion of the formed roughened layer will be filled with the coating metal, This is because the chemical layer may be offset. A particularly desirable range is between 0.03-1 Um.
- the roughened layer may be coated with a tin-substituted solution composed of tin borofluoride and thiourea.
- an adhesive layer may be formed on the surface of the insulating resin substrate opposite to the surface to which the copper foil is attached.However, a resin is applied to the substrate surface and dried to obtain an uncured state. It is desirable to use
- the adhesive layer is preferably formed from an organic adhesive, such as epoxy resin, polyimide resin, thermosetting polyphenylene ether (PPE), or epoxy resin. It is preferable that the resin be at least one resin selected from a composite resin of a resin and a thermoplastic resin, a composite resin of an epoxy resin and a silicone resin, and a BT resin.
- an organic adhesive such as epoxy resin, polyimide resin, thermosetting polyphenylene ether (PPE), or epoxy resin.
- PPE thermosetting polyphenylene ether
- NMP NMP, DMF, acetone, and ethanol
- NMP NMP, DMF, acetone, and ethanol
- a curtain coater As a method of applying the uncured resin as the organic adhesive, a curtain coater, a spin coater, a roll coater, a spray coater, screen printing, or the like can be used.
- the formation of the adhesive layer is performed by laminating the adhesive sheet. It can also be done by
- the thickness of the adhesive layer is desirably 5 to 50 // m.
- the adhesive layer is preferably pre-cured (precured) to facilitate handling.
- the semiconductor chip mounted on the circuit board is surface-mounted on the wiring pattern via the first conductive bump.
- Examples of the method of connecting the bump and the chip include a method in which the semiconductor chip and the circuit board are aligned with each other and a method in which the bump is heated and melted beforehand, and a method in which the chip and the circuit board are joined. There is.
- the temperature applied at this time is preferably in the range of 60 to 220 ° C. If the temperature is lower than 60 ° C, the conductive metal does not melt, and if the temperature is higher than 220 ° C, the conductive metal forming the bump may cause a short circuit between the adjacent bumps.
- a temperature in the range of 80 to 200 ° C. is more preferable. If the temperature is within the range, the connection can be made by melting while maintaining the shape retention of the bump.
- the gap between the semiconductor chip and the interlayer member is filled with a sealing resin as needed, thereby preventing a mismatch in the coefficient of thermal expansion between the semiconductor chip and the interlayer member.
- a sealing resin a thermosetting resin, a thermoplastic resin, an ultraviolet curing resin, a photosensitive resin, or the like can be used.
- liquid resins containing epoxy resin, silicone resin, polyimide resin, phenol resin, fluorine resin, etc., and non-conductive resin films (for example, NCF) formed from these resins in sheet form, etc. can be used.
- the insulating resin base material used for the interlayer member to be laminated together with the circuit board on which the semiconductor chip is mounted can be used as long as it is an organic insulating base material similar to the semiconductor chip mounting substrate.
- a prepreg in a semi-cured state that can be used only with a conductive resin base material can be used.
- the shape of the insulating resin base material which is slightly thicker than the height from the upper surface of the semiconductor chip mounting circuit board to the upper surface of the mounted semiconductor chip, is formed to be the same as that of the semiconductor chip mounting circuit board. .
- the thickness of the insulating resin base material constituting the interlayer member is 10 to 500 m, preferably 50 to 200 m, and most preferably 100 to 150 / m. When it becomes thinner than these ranges This is because the strength is reduced and handling becomes difficult. On the other hand, if the thickness is too large, it becomes difficult to form fine through-holes and fill the through-holes with the conductive paste.
- the through-holes formed in the interlayer member are formed by adhering a light-transmitting resin film to both surfaces of the insulating resin base material and irradiating a laser from above the resin film, similarly to the via hole forming openings. You.
- the resin film provided with an opening by the above laser irradiation fills the conductive base into the through hole and projects from the surface of the insulating resin base material to form the conductor post, and the height of the protrusion is set. And has a pressure-sensitive adhesive layer that is separated from the adhesive layer after a predetermined step.
- the resin film is preferably formed of, for example, a PET film having a pressure-sensitive adhesive layer thickness of 1 to 20 im and a film thickness of 10 to 50 / m.
- the amount of protrusion of the conductor posts from the surface of the insulating resin substrate depends on the thickness of the PET film. If the thickness is less than 10 m, the amount of protrusion is too small to connect. Conversely, if the thickness exceeds 50 // m, fine conductor patterns cannot be formed because the molten conductor posts spread too much at the connection interface.
- the diameter of the through hole formed in the insulating resin base material having the thickness in the above range is preferably in the range of 50 to 250 m.
- the laser irradiation conditions at this time are preferably pulse energy of 0.5 to 100 mJ, pulse width of 1 to 100 jus, pulse interval of 0.5 ms or more, and shot number of 3 to 50. .
- the reason why the diameter of the through hole is limited is that if the diameter is less than 50 ⁇ m, it becomes difficult to fill the opening with the conductive base, and the connection reliability is reduced. This is because it becomes difficult to increase the density.
- the above-mentioned through-hole is a case where the shape of the through-hole is a columnar shape in which upper and lower openings have the same diameter, and a conductive post is formed by filling such a through-hole with a conductive paste.
- the diameter of the conductor posts projecting upward and downward from the surface of the insulating resin base material is the same.
- the shape of the through-hole can be formed so that the upper and lower openings have different diameters.
- a truncated conical through-hole ⁇ ⁇ ⁇ having a tapered cross section is formed in a shape in which a small-diameter cylinder and a large-diameter cylinder are coaxially joined.
- a diameter ratio of a portion protruding upward and downward is preferably 1: 2 to 1: 3. 2.5 is more preferable.
- the conductive paste can be filled so that there are no voids, and when laminating with the semiconductor mounting circuit board, the displacement of the contact portion by pressing is suppressed. This is because connection reliability can be improved.
- the interlayer member When the interlayer member is formed from an uncured prepreg, it may not be necessary to perform a desmear treatment in particular before filling the through-hole with a conductive paste to form a conductor post.
- a desmear treatment in particular before filling the through-hole with a conductive paste to form a conductor post.
- the interlayer member is formed of a hard resin base such as a glass cloth base epoxy resin, for example, a chemical removal method of dipping in an oxidizing agent such as an acid, a permanganic acid, and a chromic acid, Alternatively, desmearing by a physical removal method using plasma discharge, corona discharge, or the like is desirable from the viewpoint of ensuring connection reliability.
- dry desmear treatment using, for example, plasma discharge or corona discharge.
- plasma cleaning using a plasma cleaning device is particularly preferable.
- a conductive paste composed of one or more metal particles selected from silver, copper, gold, nickel, and various solders can be used.
- metal particles those obtained by coating the surface of metal particles with a dissimilar metal can be used.
- metal particles obtained by coating copper particles with a noble metal such as gold or silver can be used.
- an organic conductive paste obtained by adding a thermosetting resin such as an epoxy resin or a polyphenylene sulfide (PPS) resin to metal particles is preferable.
- the height of the body post provided on the interlayer member that is, the amount of protrusion from the surface of the insulating resin substrate is determined depending on the thickness of the PET film, and a range of 10 to 50)! Im is desired. Better. The reason is that if the thickness is less than 10 im, the amount of protrusion is too small, resulting in poor connection.Conversely, if the thickness exceeds 50 / m, the molten conductive bumps will spread too much at the connection interface. This is because a fine pattern cannot be formed.
- the conductor post formed from the conductive paste is preferably in a semi-cured state. This is because the conductive paste can penetrate the softened organic adhesive layer during hot pressing, which is hard even in a semi-cured state. In addition, the contact area increases due to deformation during hot pressing, so that not only the conduction resistance can be reduced, but also the variation in bump height can be corrected.
- the above-mentioned semiconductor chip mounting circuit board and the interlayer member are alternately laminated, and then another circuit board such as an I / O wiring board is laminated on the outermost layer, and they are collectively pressed or collectively pressed. Later, a semiconductor module is formed by arranging solder balls and T-pins on conductive pads such as an I / O wiring board.
- a lamination form of the semiconductor chip mounting circuit board and the interlayer member For example, a semiconductor chip mounting circuit board having no via hole formed in the uppermost layer is used. The semiconductor chip mounting surface is arranged downward, and interlayer members are arranged below the semiconductor chip mounting surface. The interlayer member accommodates the semiconductor chip mounted on the mounting circuit board in the central opening. Below this, the mounted circuit board and the interlayer member are further overlapped in the same manner, and the I / O wiring board is arranged at the lowermost layer.
- both the wiring pattern of the insulating resin base material is formed and the inside of the through hole penetrating the insulating resin base material is filled.
- a double-sided circuit board is used in which wiring patterns formed on both sides of the insulating resin base material are electrically connected by via holes made of plating or conductive paste, and correspond to the positions of the conductive bumps of the interlayer member. Part of the wiring pattern is formed in the form of a conductive pad.
- a conductor foil such as a copper foil is adhered to the surface of the lowermost interlayer member from which the second conductive bump protrudes, via an adhesive, and the like.
- a semiconductor pad is formed by etching a conductive foil to form a conductive pad corresponding to the second conductive knob, and solder balls or T pins are arranged on the conductive pad.
- the mounting circuit board, interlayer members and I / O wiring board must be The positioning holes provided are optically detected by a CCD camera or the like, and the alignment is performed while proceeding.
- Such a laminate is pressed at a pressure of 0.5 to 5 MPa while being heated at a temperature of 50 to 250 ° C., and all the circuit boards are integrated by a single press molding.
- the heating temperature is preferably from 160 to 200 ° C.
- a nickel-gold layer is formed on the conductor pads of the lowermost I / O wiring board, and a solder pole or a T-pin is bonded on the gold-nickel layer to form an external board, for example. It can be a connection terminal to the motherboard.
- a circuit board 2 for mounting a semiconductor chip on which a semiconductor chip 3 is mounted and an interlayer member 20 are alternately overlapped, and
- the structure is made into a lead body by stacking the I / O wiring boards 30 and heating and pressing them all at once.
- an insulating resin base material 5 having a copper foil 6 adhered to one surface thereof is used as a starting material.
- the insulating resin base material 5 is, for example, a glass cloth epoxy resin base material, a glass cloth bismaleimide triazine resin base material, a glass cloth polyphenylene ether resin base material, an aramide nonwoven fabric—an epoxy resin base material, an aramide nonwoven fabric—a polyimide resin
- a rigid (hard) laminated substrate selected from the substrates can be used, but a glass cloth epoxy resin substrate is most preferred.
- the thickness of the insulating resin substrate 5 is most preferably 20 to 80 im, and the thickness of the copper foil 6 is most preferably 12 to 25 im.
- insulating resin base material 5 and the copper foil 6 in particular, a single-sided copper-clad obtained by laminating a prepreg having a glass cloth impregnated with an epoxy resin into a B-stage and a copper foil and pressing under heat is provided. It is preferable to use the laminate 4.
- the reason is that the position of the wiring pattern and the via hole does not shift during the handling after the copper foil 6 is etched as described later, and the position accuracy is excellent.
- a protective film 7 is attached to the surface of the insulating resin substrate 5 opposite to the surface to which the copper foil 6 is attached (see FIG. 3 (a)).
- the protective film 7 is used for adjusting the height of a conductive bump described later, and for example, a polyethylene phthalate (PET) film having an adhesive layer on the surface can be used.
- PET film 7 used is such that the thickness of the pressure-sensitive adhesive layer is 1 to 20 jUm and the thickness of the film itself is 10 to 50 / im.
- This laser processing is performed by a pulse oscillation type carbon dioxide laser processing apparatus.
- the laser irradiation conditions are as follows: pulse energy is 0.5 to 1 OOmJ, pulse width is 1 to 1 OOjUs, and pulse interval is 0.5 ms. As described above, it is desirable that the number of shots be in the range of 3 to 50.
- the diameter of the opening 8 that can be formed under such processing conditions is desirably 50 to 200 ⁇ m.
- Desmearing is performed to remove resin residue remaining on the inner wall surface of the opening 8 formed in the step (3).
- dry desmear treatment using plasma discharge, corona discharge, or the like is preferable from the viewpoint of securing connection reliability.
- the opening 11 formed in the plating resist layer "! 0" is filled with an electrolytic sprinkling film by an electrolytic sprinkling process, and a copper chip 6 1 conductive bus A pump 12 is formed (see FIG. 3 (e)). After that, the dry film forming the plating resist layer 10 is peeled off (see FIG. 4 (f)).
- a photoresist layer 14 was formed by, for example, an electrodeposition method so as to cover the first conductive bumps 12 for mounting the semiconductor chip and the copper foil 6 (see FIG. 4 (g)). Then, exposure and development are performed along a predetermined circuit pattern (see FIG. 4 (h)). Next, a wiring pattern 15 having a predetermined wiring pattern is formed by etching the copper foil 6 that is not protected by the photoresist layer 14 (see FIG. 4 (i)). Layer 14 is removed.
- etching solution at least one aqueous solution selected from aqueous solutions of sulfuric acid hydrogen peroxide, persulfate, cupric chloride, and ferric chloride is desirable.
- a part of the wiring pattern 15 is formed on a conductive pad or connection land 15a for connecting to a conductive bump 26 of the interlayer member 20 described later, and the inner diameter is almost the same as the via hole diameter.
- the outer diameter is preferably formed in the range of 50 to 250 / m.
- the surface of the wiring pattern 15 formed in the step (9)) is subjected to a roughening treatment to form a roughened layer 17, and thereafter, the insulating resin base material is formed.
- the PET film 7 is peeled off from the surface opposite to the copper foil application surface, and an adhesive layer 18 is formed on the surface from which the PET film 7 has been peeled off. Manufacturing is completed (see Fig. 4 (j)).
- the above-mentioned roughening treatment is for improving the adhesion to the adhesive layer formed on the interlayer member and preventing the delamination during multilayering.
- Examples of the roughening method include a soft etching process, a blackening (oxidation) -reduction process, and a needle-like alloy plating of copper-nickel-phosphorus (manufactured by Ebara Uzilite: trade name, Interpret). Forming, surface roughening by an etching solution called “Mech Etch Bond” manufactured by Mec Corporation.
- the roughened layer is preferably formed using an etchant.
- the surface of a wiring pattern is formed using an etchant from a mixed aqueous solution of a cupric complex and an organic acid. It can be formed by etching. Heel The etching solution can dissolve the copper wiring pattern under the condition of coexistence of oxygen such as spraying or publishing, and the reaction is presumed to proceed as follows.
- A represents a complexing agent (acting as a chelating agent), and ri represents a coordination number.
- the generated cuprous complex dissolves under the action of an acid and combines with oxygen to form a cupric complex, which again contributes to copper oxidation.
- the cupric complex used in the present invention is preferably a cupric complex of an azole.
- the etching solution comprising the organic acid-cupric complex can be prepared by dissolving a cupric complex of an azole and an organic acid (halogen ion if necessary) in water.
- Such an etchant is formed, for example, from an aqueous solution obtained by mixing 10 parts by weight of an imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride.
- the circuit board 2 for mounting a semiconductor chip according to the present invention is manufactured according to the above-mentioned steps (1) to (10), and the semiconductor chip 3 is, as shown in FIG.
- the output terminal 3 a of the semiconductor chip 3 is fixed by an adhesive 16, and is electrically connected to the wiring pattern 15 by being embedded in the first conductive bump 12.
- a sheet-like sealing resin 16 is provided between the circuit board 2 and the semiconductor chip 3.
- a material in which a hard insulating resin base material 21 is formed in a plate shape is used similarly to the circuit board 2 for mounting a semiconductor chip (see FIG. 6 (a)). .
- the J * of the insulating resin base material 21 is determined from the upper surface of the semiconductor chip mounting circuit board 2 to the upper surface of the semiconductor chip 3 due to the necessity of accommodating the semiconductor chip 3 in a central opening 27 described later.
- the upper surface and the lower surface of the insulating resin base material 21 are set to be approximately equal to the area of the printed circuit board 2 that is opposed to the substrate when the lamination is performed. ing.
- an adhesive layer 22 is formed on both surfaces of the insulating resin base material 21, and a PET film 23 is attached on the upper surface thereof for protection (see FIG. 6 (b)).
- the connection land of the semiconductor chip mounting substrate 22, that is, the position corresponding to the conductor pad ⁇ 5 a and the second conductive pump 13 is placed on the PET film 23 by, for example, a pulsed carbon dioxide gas laser processing device.
- a through hole 24 penetrating in the thickness direction of the insulating resin base material 21 is formed (see FIG. 6 (c)).
- the conductive paste 25 is filled in the through hole 24 (see FIG. 6D).
- the filling of the conductive paste is performed from the front and back sides by screen printing, for example.
- the conductive paste 25 is formed with conductor posts 26 protruding from the front surface and the back surface of the adhesive layer 22 by the thickness of the PET film 23 (see FIG. 6 (e)). .
- an opening 27 having a size capable of accommodating the semiconductor chip 3 is formed in the central portion of the insulating resin base material 21 by, for example, laser irradiation, and the manufacture of the interlayer member 20 is completed (FIG. 6 (f)).
- the semiconductor chip mounted circuit board 2 manufactured as described above and the interlayer member 20 are alternately overlapped (see FIG. 7A).
- a semiconductor chip mounting circuit board 2 in which no via hole is formed is arranged with the surface on which the semiconductor chip 3 is mounted facing downward, and an interlayer member 20 is arranged thereunder.
- the semiconductor chip mounting circuit board 2 having via holes formed therein and the interlayer member 20 are arranged, and the I / O wiring board 30 is arranged at the lowermost layer.
- the interlayer member 20 facing the uppermost semiconductor chip mounting board 2 accommodates the conductor chip 3 previously mounted and fixed on the semiconductor chip mounting circuit board 2 in the opening 27 thereof,
- the upper protruding end of the post 26 faces the connection land 15a of the semiconductor chip mounting circuit board 2, and the lower protruding end of the conductor post 26 has an adjacent lower semiconductor chip mounting circuit board 2 below it.
- the conductive bumps 13 are superposed so as to face each other.
- an interlayer member 20 is provided at the upper end of the conductor post 26. Is facing the connection land ⁇ 5a of the adjacent semiconductor chip mounting circuit board 2 above, and the lower projecting end of the conductor post 26 is connected to the conductor pad of the lowermost IZO wiring board 30 located therebelow. It is superimposed so that it faces 31.
- the IZO wiring board 30 has a structure in which a via hole 34 is formed at a predetermined position of an insulating resin substrate 33, and a predetermined wiring circuit (not shown) and a conductive pad 31 are formed above and below the via hole 34.
- the adhesive layer 22 of the interlayer member 20 is pressed by collectively vacuum-pressing the semiconductor chip mounting substrate 2, the inter-layer member 20, and the 0 wiring substrate 30 which are superimposed in the above positional relationship. After curing, it is bonded to the circuit board 2 for mounting a semiconductor chip and the IZO wiring board 30 to form the semiconductor module 1 (see FIG. 7 (b)).
- the wiring pattern 5 of the uppermost semiconductor chip mounting board 2 is electrically connected to the wiring pattern of the lower semiconductor chip mounting circuit board 2 via the conductor posts 26 formed on the adjacent interlayer member 20. It is electrically connected to the wiring pattern of the I / O wiring board 30 via the conductor boss 26 formed on the lower interlayer member 20.
- solder holes 32 for connection to an external board are formed on the lands 31 on the lower surface side of the I / O wiring board 30.
- the adhesive layer 22 is formed on both surfaces of the insulating resin substrate 21. Attach the protective film 23. Thereafter, a through hole 24 is formed at a predetermined position by laser processing, and after filling the through hole 24 with a conductive paste 25, the protective film 23 is peeled off. For this reason, the conductor posts 26 are formed so as to protrude from the surface of the adhesive layer 22 by the thickness of the protective film 23, whereby the interlayer member 20 is laminated together with the semiconductor chip mounting board 2 and the IZO wiring board 30.
- the contact between the conductor pad 15a of the circuit board 2 for mounting a semiconductor chip and the conductor post 26 of the interlayer member 20 and the contact between the conductor pad 31 of the IZO wiring board 30 and the conductor post 26 of the interlayer member 20 are made. Since the contact between them is not hindered by the presence of the adhesive layer 22, the connection reliability between the conductor pad and the conductor post can be improved.
- the two semiconductor chip-mounted circuit boards 2 and the two interlayer members 20 are stacked, and the I / O wiring board 30 is further stacked to form a five-layer structure.
- the semiconductor module according to the present invention is not limited to the above-described laminated state. At least the semiconductor chip mounting substrate 2 according to the present invention and the interlayer member 20 are laminated, and in addition to the above, other forms of I / O wiring Substrates may be combined.
- a single-sided copper-clad laminate 4 obtained by laminating a copper foil with a prepreg in which a glass cloth is impregnated with an epoxy resin to form a B-stage and hot pressing is used as a starting point for a circuit board 2 for mounting a semiconductor chip. Used as material.
- the thickness of the insulating resin base material 5 was 75 ⁇ m, and the thickness of the copper foil 12 was 12 j! Im (see FIG. 3 (a)).
- a 22 / m-thick PET film 7 is attached to the surface of the insulating resin substrate 5 opposite to the surface to which the copper foil 6 is attached.
- This PET film 7 is composed of an adhesive layer having a thickness of lOjLim and a PET film base having a thickness of 12 ⁇ m.
- a pulse oscillation type carbon dioxide laser is irradiated from above the PET film 7 under the following laser processing conditions to form an opening 8 for forming a via hole, and the hole 8 remains on the inner wall of the opening.
- a plasma cleaning process was performed (see Fig. 3 (b)).
- Pulse interval 0.5 ms or more
- Via holes 9 were formed with 1 50 JUm and a via hole distance of 500 ⁇ m.
- the PET film 7 After peeling off the PET film 7 adhered to the conductive foil 6 of the insulating resin base material 5, the PET film 7 is peeled off. 7 is attached. Then, a plating resist layer 10 having an opening 11 is formed on the surface of the insulating resin substrate 5 to which the copper foil 6 is to be attached (see FIG. 3 (d)). An electrolytic sprinkling process is performed under the plating conditions, and the opening 11 is filled with an electrolytic sprinkling film.
- the copper foil 6 has a diameter (bump diameter) of 80 / im, a height of 20 ⁇ m, A first conductive bump 12 having a distance (pitch) between bumps of 140 im was formed (see FIG. 3 (e)).
- a photoresist layer 14 is formed by an electrodeposition method (see FIG. 4 (g)). Exposure and development are performed along the circuit pattern (see Fig. 4 (h)).
- the copper foil 6 not protected by the photoresist layer 14 is etched to form a wiring pattern 15 having a predetermined wiring pattern, and then the photoresist layer 14 is removed (FIG. 4 ( i)).
- etching solution at least one aqueous solution selected from aqueous solutions of sulfuric acid hydrogen peroxide, persulfate, cupric chloride, and ferric chloride is desirable.
- the surface of the wiring pattern 15 is roughened with an etchant to form a roughened layer 17, and thereafter, the PET film 7 is peeled off from the surface opposite to the surface to which the copper foil is adhered, thereby forming a semiconductor chip.
- the mounting circuit board 2 was manufactured (see Fig. 4 (j)).
- the first conductive bump 1 is formed by potting ink.
- a semiconductor chip 3 was mounted on the surface of 2, and a semiconductor chip-mounted circuit board was fabricated (see FIG. 5).
- an adhesive resin layer 22 having a thickness of 15 m is formed on both sides of an insulating resin substrate 21 formed of a glass cloth base epoxy resin having a thickness of 130 // m in a plate shape. Forming the adhesive layer
- a protective film 23 having a thickness of 23 Um is affixed on top of 22 and irradiated with a pulsed carbon dioxide laser under the following laser processing conditions to obtain a cylindrical through-hole with a diameter of 100 m. (See FIGS. 6 (a) to 6 (c)).
- Pulse interval 0.5 ms or more
- conductor posts 26 projecting from the surface of the adhesive layer 22 by the thickness of the protective film 23 are formed on the upper and lower surfaces of the insulating resin base material 21 (FIG. 4). (e)).
- an opening 27 capable of accommodating the semiconductor chip 3 was similarly formed at substantially the center of the insulating resin base material by laser irradiation, thereby producing an interlayer member 20 (see FIG. 6 (0)). .
- a nickel-gold layer (not shown) is formed on the conductor pad 31 of the I / O wiring board 30 at the lowermost layer of the laminate obtained in (13), and the nickel On the gold layer, solder balls 32 connected to the mother-port terminals were formed to produce a semiconductor module 1 having a BGA structure (see FIG. 7 (b)).
- Example 1 The same processing as in (1) to (9) of Example 1 was performed to produce a mounting circuit board 2 on which the semiconductor chip 3 was mounted (see FIGS. 3 (a) to 4 (k)). .
- a glass cloth base material is impregnated with epoxy resin and heated to a semi-cured state to form a plate, and a prepreg having a thickness of 150 / m is used as an insulating resin base material for the interlayer member 20. This was prepared as 21 (see Fig. 8 (a)).
- a protective film 23 having a thickness of 23 / m is attached to both sides of the insulating resin base material 21 made of the above pre-preda (see FIG. 8 (b)), and the pulse oscillation type carbon dioxide is applied under the following laser processing conditions.
- Moth A laser beam was irradiated from below the insulating resin substrate 21 to form a truncated conical through-hole 24 with a diameter of 250 m on the lower surface and 100 m on the upper surface (see Fig. 8 (c)). ).
- Pulse interval 0.5 ms or more
- the conductive paste 25 mainly composed of Cu particles was filled in the through-hole 24 formed in the above (2) by screen printing in which a metal mask was placed on the protective film 23 (FIG. 8 (d) reference). Thereafter, when the protective film 23 is peeled off, the conductor posts 26 (projections 26a, 26b) projecting from the surface of the adhesive layer 22 by the thickness of the protective film 23 are formed on the upper and lower surfaces of the insulating resin base material 21. (See Fig. 8 (e)).
- the diameters of the protruding portions 26a and 26b of the conductor posts 26 substantially correspond to the diameters of the truncated conical through holes 24, and the upper protruding portion 26a is formed smaller than the lower protruding portion 26b.
- an opening 27 capable of accommodating the semiconductor chip 3 was formed substantially at the center of the insulating resin base material by laser irradiation to produce an interlayer member 20 (FIG. 8 (f)). reference).
- Example 1 Thereafter, the same processing as in (1 3) to (14) of Example 1 was performed to produce a semiconductor module 1 having a BGA structure (see FIGS. 9 (to 9)).
- the through hole 24 formed in the interlayer member 20 is formed in a tapered shape in which the inner diameter of the opening on the lower surface side is larger than the opening on the upper surface side.
- the diameter of the portion 26b is formed larger than the diameter of the protrusion 26a on the upper surface side. Accordingly, the projecting portion 26a of the conductor post 26 having a smaller diameter is connected to the conductor pad ⁇ 5a of the upper semiconductor chip mounting substrate 2, and the projecting portion 26 having a larger diameter is connected to the lower semiconductor chip mounting substrate 2.
- the interlayer members 20 are stacked and heated and pressed so as to be connected to the second second conductive bumps 13. As a result, even if a displacement occurs due to pressing during lamination, the displacement error can be absorbed, and good connection between the semiconductor chip mounting substrate 2 and the interlayer member 20 can be achieved. Can be secured. (Example 3)
- Example 2 The same processing as in (1) to (9) of Example 1 was performed to produce a semiconductor mounting substrate 2.
- an insulating resin substrate 21 formed of a plate-like glass cloth substrate epoxy resin was used (see FIG. 8 (a)).
- an adhesive layer 22 having a thickness of 15 m is formed on both sides of an insulating resin substrate 21 having a thickness of 130 / im, and a thickness of 23 ⁇ m is formed on the adhesive layer 22. (See Fig. 8 (b)), and irradiate a loose oscillation type carbon dioxide laser from below the insulating resin base material 21 under the following laser processing conditions to form a stepped cylindrical through-hole. 24 formed.
- the through hole 24 is formed of a cylindrical concave portion 55 having a diameter of 250 m.
- the through hole 24 penetrates coaxially from the bottom surface of the concave portion 55 in the thickness direction of the insulating resin base material 21. However, it has a stepped shape as a whole from a cylindrical through hole 56 of 100 jum (see FIG. 8 (c)).
- the conductive paste 25 mainly composed of Ag particles is filled by screen printing from the lower protective film 23 of the material 21, and the conductive paste is similarly formed by screen printing from the upper protective film 23 of the insulating resin base material 21.
- the paste 25 was filled (see FIG. 8 (d)).
- the conductor posts 26 protruding ends 26a and 26b projecting from the surface of the adhesive layer 22 by the thickness of the protective film 23 are formed on the upper surface of the insulating resin base 21. And formed on the lower surface (see Fig. 8 (e)).
- the diameter of the projecting portions 26a and 26b of the conductor post 26 corresponds to the diameter of the truncated conical through hole 24, and the upper projecting portion 26a is formed smaller than the lower projecting portion 26b.
- an opening 27 capable of accommodating the semiconductor chip 3 was formed substantially at the center of the insulating resin base material 21 by laser irradiation to produce the interlayer member 20 (see FIG. 80D).
- Example 1 Thereafter, the same processing as in (13) to (14) of Example 1 was performed to fabricate a semiconductor module 1 having a BGA structure (see FIGS. 9 (a) and 9 (b)).
- the through hole 24 formed in the interlayer member 20 is formed in a stepped cylindrical shape in which the inner diameter of the opening 55 on the lower surface side is larger than that of the opening 56 on the upper surface side.
- the diameter of the projecting portion 26b on the lower surface side is formed larger than the diameter of the projecting portion 26a on the upper surface side.
- the projecting portion 26a of the conductor post 26 having a smaller diameter is connected to the conductor pad 15a of the semiconductor chip mounting substrate 2, and the projecting portion 26b of the larger diameter is
- the interlayer members 20 are stacked and heated and pressed so as to be connected to the second conductive bumps "! 3" of the chip mounting board 2.
- displacement occurs due to the press during stacking. In this case, the displacement error can be absorbed, and good connectivity between the semiconductor chip mounting substrate 2 and the interlayer member 20 can be ensured.
- the thickness of the insulating resin base material 5 was 40 m, and the thickness of the copper foil 12 was 12 m.
- a 22 // m thick PET film 7 is attached to the surface of the insulating resin substrate 5 opposite to the surface to which the copper foil 6 is attached.
- This PET film 7 is composed of an adhesive layer having a thickness of 10 m and a PET film base having a thickness of 12 Um.
- Pulse interval 0.5 ms or more
- the phenolic resin is applied to the entire resin surface of the insulating resin substrate 5.
- an adhesive layer 11 made of epoxy resin is formed, and then the PET film 7 attached to the copper foil 6 attachment surface of the insulating resin substrate 5 is peeled off (see FIG. 12 (c)). .
- a copper foil 13 having a thickness of 12 m is pressed on the adhesive layer 11 1 so that copper foils 13 are provided on both sides of the board, and the copper foils 13 are provided in the via holes 9.
- the double-sided copper-clad laminate 16 electrically connected by conductors shall be used (see Fig. 12 (d)).
- a photosensitive dry film is stuck on the copper foil 6 on the upper surface side of the insulating resin base material 5 to form bumps for electrical connection with the semiconductor chip 3 by mask exposure and development processing. Forming a plating resist layer 10 having an opening 11 for it (see FIG. 12 (e)).
- the following electrolytic plating conditions are applied to the openings 11 formed in the plating resist layer 10. And electrolyze A sprinkling treatment is performed to fill the electrolytic sprinkling film. Then, while removing the plating resist layer 10 and peeling off the protective film 7, the copper foil 6 has a diameter (bump diameter) of 80 / m, a height of 20 jti m, and a distance between the bumps (pitch). A first conductive bump "12" of 140 / m was formed (see FIG. 12 (f)).
- a photoresist layer 14 is formed on both sides of the double-sided laminated board 16 by, for example, an electrodeposition method (see FIG. 13 (g)), and then a predetermined circuit pattern is formed. Exposure and development are performed along (see Figure 13 (h)). Thereafter, the copper foil 6 not protected by the photoresist layer 14 is etched to form a wiring pattern 15 having a predetermined wiring pattern on both surfaces by etching, and then the photoresist layer 14 is removed ( See Figure 13 (i)).
- the etching solution at least one aqueous solution selected from aqueous solutions of sulfuric acid hydrogen peroxide, persulfate, cupric chloride, and ferric chloride is desirable.
- a part of the wiring pattern 15 is formed on a conductor pad or a connection land 15a for connecting to a conductor post 26 of the interlayer member 20 described later.
- the diameter is formed to 250 jU m.
- step (10) Next, if necessary, the surface of the wiring pattern 15 formed in the step (9) is roughened to form a roughened layer (not shown), and wiring is formed on both surfaces. The manufacture of the semiconductor chip mounting circuit board 40 having the pattern 15 is completed.
- the semiconductor module 1 having the BGA structure was manufactured by performing the same processing as in (10) to (14) in Example 1 except that the desmear treatment was not performed (FIG. 14 (a)). ) ⁇ (b)).
- the inside of the opening 8 is filled with electrolytic copper plating, and the filling depth is made to be flush with the surface of the insulating resin base material 5, and then subjected to electrolytic soldering treatment, so that the electrolytic copper plating is performed. Except for using an insulating resin substrate 21 made of a plate-like glass cloth substrate epoxy resin as the interlayer member 20, except that the via hole 9 was formed by electrolytic soldering to cover the surface, and the via hole 9 was formed. The same processing as in Example 4 was performed to produce a semiconductor module 1 having a BGA structure.
- the semiconductor chip mounting substrate has a wiring pattern including the second conductive bumps 12 for mounting the semiconductor chip 3 formed on one surface thereof, and a wiring pattern formed on the other surface. Also, since the wiring pattern is formed, the size of the stacked semiconductor module can be avoided, and a thin and high-density semiconductor module can be obtained. Also, when forming the wiring pattern on both surfaces of the insulating resin base material, the conductive material to be filled into the via hole forming opening is made of a metal having a lower melting point than copper, so that the metal is covered and the insulating resin is formed. Adhesion with the copper foil to be attached to the substrate surface can be improved.
- the thickness of the insulating resin substrate 5 was 40 ⁇ m, and the thickness of the copper foil 12 was 12 / m (see FIG. 15 (a)).
- a pulse oscillation type carbon dioxide laser is irradiated from above the resin surface of the insulating resin base material 5 under the following laser processing conditions to form an opening 8 for forming a via hole.
- Plasma cleaning was performed to remove the resin remaining on the inner wall of the opening (see Fig. 15 (b)).
- Pulse interval 0.5 ms or more
- a 22 / m-thick PET film 7 is applied as an etching protection film to the surface to which the copper foil 6 is attached, and then the electrolytic copper plating is performed with an electrolytic plating aqueous solution having the following composition under the following plating conditions.
- the inside of the opening 8 was filled with electrolytic copper plating to form a via hole 9 having a diameter of 150 / m and a distance between via holes of 500 m.
- the electrolytic copper plating is filled to such an extent that it slightly protrudes from the surface of the insulating resin substrate 5 (see FIG. 13 (c)).
- a photoresist layer 14 is formed by an electrodeposition method (see FIG. 16 (g)). Exposure and development are performed along the specified circuit pattern (see Fig. 16 (h)). Next, the copper foil 6 that is not protected by the photoresist layer 14 is etched to form a wiring pattern 15 having a predetermined wiring pattern, and then the photoresist layer 14 is removed ( See Figure 16 (i)).
- etching solution at least one aqueous solution selected from aqueous solutions of sulfuric acid hydrogen peroxide, persulfate, cupric chloride, and ferric chloride is desirable.
- the surface of the wiring pattern 15 is roughened with an etchant to form a roughened layer (not shown), and then the PET film 7 is peeled off from the surface opposite to the copper foil application surface.
- a circuit board 2 for mounting a semiconductor chip was manufactured.
- a glass cloth substrate is impregnated with an epoxy resin, and is heated and semi-cured to form a plate shape.
- a semiconductor module 1 having a BGA structure was manufactured by performing the same processing as in (1 10) to 14) of Example 1 except that 20 was formed and no desmear processing was performed (FIG. 17). (ab)).
- the semiconductor chip mounting substrate 2 is formed with the conductor pads having a relatively large connection area, that is, the connection lands 5a and 19 are formed.
- the conductor post 26 formed on the adjacent interlayer member 20 is connected to the pad, and the conductor post 26 having a relatively small connection area formed on the interlayer member 20 is connected to the conductor pad 31 of the IZO wiring board 30.
- the wiring 26 Since the wiring 26 is connected, the wiring patterns of the plurality of stacked semiconductor chip mounting substrates 2 and the wiring patterns of the IZO wiring substrate 30 are reliably electrically connected. Therefore, electrical connection failure can be significantly reduced, and a semiconductor module with high connection reliability can be manufactured.
- Example 1 The same processing as the steps (1) to (9) of Example 1 was performed to manufacture a circuit board A for mounting a semiconductor.
- a PET film 6 as an etching protection film is attached to the surface of the insulating resin base material 5 opposite to the surface to which the copper foil 6 is attached, and in that state, an etching resist layer is applied to the surface of the copper foil 6.
- a roughened layer (not shown) is formed on the surface of the wiring pattern 15 by etching, and an adhesive layer 22 is formed on the surface of the insulating resin base material 5 on which the conductive bumps 13 are formed. After that, an opening 27 is formed almost at the center of the insulating resin base material 5 to produce the interlayer member B.
- the four mounting boards A1 to A4 on which the semiconductor chip 3 is mounted are alternately laminated with the four interlayer members B1 to B4, and a central opening is formed outside the uppermost layered circuit board B4. Formed With the other interlayer member B5 not placed, while the copper foil 6 is placed on the outside of the lowermost semiconductor chip mounting circuit board A1 (see FIG. 19), while heating at a temperature of 180 ° C. , And pressurized at 2MPa, and all substrates were compacted by one press molding (see Fig. 20).
- a PET film 7 as an etching protection film is attached to the surface of the circuit board for lamination 5 on the uppermost layer of the laminate obtained in (6) above, and the copper of the circuit board A1 on the semiconductor chip on the lowermost layer. After an etching resist layer 14 corresponding to a predetermined wiring pattern is formed on the foil surface, a conductive pad 15a is formed by etching.
- the PET film 7 attached to the surface of the uppermost layered circuit board B5 is peeled off, the etching resist layer 14 is removed, and then the surface of the uppermost interlayer member B5 and the lowermost layer are removed.
- a solder resist layer 54 having an opening exposing the solder pad portion 15a is formed on the surface of a certain semiconductor chip mounting circuit board A1, and a conductive bump 50 and a solder pole 52 are respectively formed on the exposed solder pad portion.
- nickel layer consisting of nickel-gold J on each of the above solder pads.
- the nickel layer is preferably 1 to 7 // m, and the desired gold layer is 0.01 to 0.06 // m. The reason for this is that if the nickel layer is too thick, it causes an increase in the resistance value, and if it is too thin, it tends to peel off. This is because the adhesion effect of the metal is reduced.
- a solder body is supplied on a metal layer made of nickel-gold which is provided on such a solder pad portion 15a, and the solder member is melted and solidified, so that the uppermost interlayer member B5 has a conductive bump.
- the semiconductor module 1 was manufactured by providing the solder balls 52 on the mounting board A1 of the lowermost layer and the mounting board A1 of the lowermost layer, respectively.
- the diameter (pump diameter) is 80 / m
- the height is 20 ⁇ m
- the distance between bumps (pitch) is 1 by printing.
- the first conductive bumps 12 of 40 m were formed and the second conductive bumps 13 of 150 m / m in diameter, 5 m in height, and a distance between bumps of 500 m were formed.
- a semiconductor chip mounting circuit board 2 and a semiconductor module 1 were produced in the same manner as in Example 7.
- Example 9 Under the following plating conditions, electrolytic soldering is applied, and the opening 11 is filled with an electrolytic soldering film.
- the copper foil 6 has a diameter (bump diameter) of 80 m. Except that the first conductive bump 12 having a height of 20 m and a distance between bumps (pitch) of 140 // m was formed, the processing was performed in the same manner as in Example 1 to obtain a circuit board for mounting a semiconductor chip. 2 and semiconductor module 1 were produced.
- the present invention in a state where the semiconductor chip is securely mounted on the conductive bumps of the mounting circuit board, it is possible to form a multilayer with the interlayer member having the opening for accommodating the semiconductor chip.
- the distance between the semiconductor chips can be shortened, and the electrical connectivity can be improved, problems caused by wiring resistance and inductance can be reduced, and electric signals can be transmitted at high speed without delay.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/344,892 US7049528B2 (en) | 2002-02-06 | 2002-02-06 | Semiconductor chip mounting wiring board, manufacturing method for same, and semiconductor module |
CNB02801796XA CN100550355C (zh) | 2002-02-06 | 2002-02-06 | 半导体芯片安装用基板及其制造方法和半导体模块 |
PCT/JP2002/000973 WO2003067656A1 (fr) | 2002-02-06 | 2002-02-06 | Carte de montage pour puce a semiconducteur, realisation correspondante, et module a semiconducteur |
EP02711337A EP1489657A4 (en) | 2002-02-06 | 2002-02-06 | SEMICONDUCTOR CHIP MOUNTING PLATE, METHOD FOR THE PRODUCTION THEREOF AND SEMICONDUCTOR MODULE |
US11/280,248 US7656032B2 (en) | 2002-02-06 | 2005-11-17 | Semiconductor chip mounting wiring board, manufacturing method for same, and semiconductor module |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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PCT/JP2002/000973 WO2003067656A1 (fr) | 2002-02-06 | 2002-02-06 | Carte de montage pour puce a semiconducteur, realisation correspondante, et module a semiconducteur |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US10344892 A-371-Of-International | 2002-02-06 | ||
US11/280,248 Division US7656032B2 (en) | 2002-02-06 | 2005-11-17 | Semiconductor chip mounting wiring board, manufacturing method for same, and semiconductor module |
Publications (1)
Publication Number | Publication Date |
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WO2003067656A1 true WO2003067656A1 (fr) | 2003-08-14 |
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ID=27677637
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP2002/000973 WO2003067656A1 (fr) | 2002-02-06 | 2002-02-06 | Carte de montage pour puce a semiconducteur, realisation correspondante, et module a semiconducteur |
Country Status (4)
Country | Link |
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US (2) | US7049528B2 (ja) |
EP (1) | EP1489657A4 (ja) |
CN (1) | CN100550355C (ja) |
WO (1) | WO2003067656A1 (ja) |
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Also Published As
Publication number | Publication date |
---|---|
US7049528B2 (en) | 2006-05-23 |
US20030168254A1 (en) | 2003-09-11 |
CN100550355C (zh) | 2009-10-14 |
EP1489657A4 (en) | 2011-06-29 |
US7656032B2 (en) | 2010-02-02 |
EP1489657A1 (en) | 2004-12-22 |
US20060076671A1 (en) | 2006-04-13 |
CN1625805A (zh) | 2005-06-08 |
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