JP3704864B2 - 半導体素子の実装構造 - Google Patents

半導体素子の実装構造 Download PDF

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Publication number
JP3704864B2
JP3704864B2 JP02808797A JP2808797A JP3704864B2 JP 3704864 B2 JP3704864 B2 JP 3704864B2 JP 02808797 A JP02808797 A JP 02808797A JP 2808797 A JP2808797 A JP 2808797A JP 3704864 B2 JP3704864 B2 JP 3704864B2
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Prior art keywords
semiconductor element
lands
substrate
mounting structure
inspection
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Expired - Fee Related
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JP02808797A
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JPH10223801A (ja
Inventor
浅井　　康富
真治 太田
長坂　　崇
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Denso Corp
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Denso Corp
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Priority to JP02808797A priority Critical patent/JP3704864B2/ja
Priority to US09/021,989 priority patent/US6376906B1/en
Publication of JPH10223801A publication Critical patent/JPH10223801A/ja
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Publication of JP3704864B2 publication Critical patent/JP3704864B2/ja
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Description

【０００１】
【発明の属する技術分野】
本発明は、絶縁性基板上にフリップチップＩＣなどの半導体素子を実装した半導体素子の実装構造に関する。
【０００２】
【従来の技術】
アルミナを用いたセラミック積層基板（以下、アルミナ積層基板という）に半導体素子を実装した従来の構成を図６に示す。
アルミナ積層基板１には、導体が充填されたビアホール（以下、ビアという）２と内層配線３による内部配線が形成されており、アルミナ積層基板１の表面にはビア２と接続された導体ランド４が形成されている。この導体ランド４にフリップチップＩＣ７のはんだバンプ８が位置合わせされ、フリップチップＩＣ７がアルミナ積層基板１にフリップチップ接合されている。
【０００３】
また、フリップチップＩＣ７のサイズが大きくなると、フリップチップＩＣ７の熱膨張係数とアルミナ積層基板１の熱膨張係数の差によりはんだバンプ８の熱歪みが大きくなるため、アルミナ積層基板１とフリップチップＩＣ７の間に、フリップチップＩＣ７のはんだバンプ８を補強するための補強用樹脂９が注入されている。
【０００４】
アルミナ積層基板１の表面には、フリップチップＩＣ７を検査するために用いられる検査ランド６が形成されており、この検査ランド６は、配線５を介して導体ランド４と接続されている。
【０００５】
【発明が解決しようとする課題】
このような従来の構成において、冷熱サイクル試験を行ったところ、検査ランド６への配線５と補強用樹脂９のフィレット部Ａとが接しているところから剥離が進展し、その結果、補強用樹脂９の十分な補強が得られず、はんだにクラックが生じるという問題が発生した。これは、補強用樹脂９と導体である配線５の接着密度が、補強用樹脂９とアルミナの接着密度に比べ、非常に低いためであると考えられる。
【０００６】
なお、上記したフリップチップＩＣの実装構造に限らず、絶縁性基板上にベアチップの半導体素子を実装し、絶縁性基板上に形成したボンディングパッド（ワイヤランド）にワイヤを用いて半導体素子を電気的に接続した後、半導体素子を樹脂封止する実装構造においても、絶縁性基板の表面にワイヤランドから検査ランドに至る配線を形成する場合には、上記したのと同様、封止樹脂が剥離し、ワイヤがオープンする問題が生じる。
【０００７】
本発明は上記問題に鑑みたもので、検査ランドへの配線部分での樹脂剥離を防止することを目的とする。
【０００８】
【課題を解決するための手段】
上記目的を達成するため、請求項１に記載の発明においては、フリップチップＩＣ（７）とアルミナ基板（１）の間に補強用樹脂（９）を注入してなる実装構造において、補強用樹脂（９）のフィレット部（Ａ）をバイパスして複数の検査ランド（６）と複数の導体ランド（４）とをそれぞれ電気的に接続するように、アルミナ基板（１）に内部配線（２、３）を形成し、補強用樹脂（９）のフィレット部（Ａ）が複数の検査ランド（６）への配線と接しなく、すべてアルミナ基板（１）と接していることを特徴としている。
【０００９】
従って、検査ランド（６）への配線と補強用樹脂（９）とが接しないため、補強用樹脂（９）の剥離を防止することができる。請求項２に記載の発明においては、ベアチップなどの半導体素子（１１）を封止樹脂（１４）にて封止してなる実装構造において、封止樹脂（１４）の端部（Ｂ）をバイパスして複数の検査ランド（６）と複数の導体ランド（１０）とをそれぞれ電気的に接続するように、絶縁性基板（１）に内部配線（２、３）を形成し、封止樹脂（１４）の端部（Ｂ）が複数の検査ランド（６）への配線と接しなく、すべて絶縁性基板（１）と接していることを特徴としている。
【００１０】
従って、検査ランド（６）への配線と封止樹脂（１４）とが接しないため、封止樹脂（１４）の剥離を防止することができる。
なお、絶縁性基板（１）としては、単層、積層のものを用いることができるが、積層基板とした場合には、請求項３に記載の発明のように、絶縁性基板（１）に形成されたビア（２）と内層配線（３）を介して検査ランド（６）を導体ランド（４、１０）に電気的に接続する構造とすることができる。
【００１１】
【発明の実施の形態】
以下、本発明を図に示す実施形態について説明する。
（第１実施形態）
図２（ａ）に、フリップチップＩＣ７をアルミナ積層基板１に実装する状態を示し、図２（ｂ）に、アルミナ積層基板１の平面構成を示す。
【００１２】
図２（ａ）、（ｂ）に示すように、アルミナ積層基板１には、ビア２と内層配線３による内部配線が形成されており、アルミナ積層基板１の表面にはビア２と接続された導体ランド４、検査ランド６が形成されている。ビア２と内層配線３は、アルミナ積層基板１に実装された種々の電子部品、例えば半導体素子、コンデンサ、抵抗などを電気的に接続するとともに、上記した導体ランド４と検査ランド６を電気的に接続する。なお、導体ランド４、検査ランド６は、銅、銀、ニッケル、金、白金、パラジウム、あるいはＳｎを主成分とした材料を用いて形成されている。
【００１３】
フリップチップＩＣ７の電極には、はんだバンプ８が形成されており、図２（ａ）に示すように、はんだバンプ８を導体ランド４と位置合わせし、はんだを溶融させて、フリップチップＩＣ７をアルミナ積層基板１上に実装する。
この後、図１（ａ）に示すように、フリップチップＩＣ７とアルミナ積層基板１の間に、補強用樹脂９を注入する。この補強用樹脂９としては、ガラスフィラーを７０ｗｔ％含有するエポキシ系樹脂を用いることができる。
【００１４】
なお、図１（ａ）は、フリップチップＩＣ７をアルミナ積層基板１に実装した後の断面構成を示す図で、図１（ｂ）は、その平面構成を示す図である。
上記した実装構造においては、検査ランド６を、その直下のビア２と内層配線３を介して導体ランド４に電気的に接続し、ビア２および内層配線３により補強用樹脂９のフィレット部Ａをバイパスした配線構造となっている。従って、補強用樹脂９のフィレット部Ａは、検査ランド６への配線と接しなく、全て密着強度の高いアルミナと接することになるため、冷熱サイクル、湿気などのストレスに対し、補強用樹脂９の剥離を防止することができる。
【００１５】
また、図３に示すように、アルミナ基板１ａ上に絶縁ガラス１ｂを形成した印刷多層基板としてもよい。この場合、絶縁ガラス１ｂと補強用樹脂９とは密着強度が高いため、上記した実施形態と同様の効果を得ることができる。
【００１６】
また、絶縁性基板は、積層基板に限らず単層基板であってもよい。この場合、導体ランド４から基板を貫通するビアを形成し、基板の裏面に他の電子部品と接続する配線を形成し、その配線と検査ランド６とをビアを介して電気的に接続する構造とすることができる。
（第２実施形態）
この実施形態においては、アルミナ積層基板上にベアチップの半導体素子を実装した構造としている。
【００１７】
図４に示すように、アルミナ積層基板１には、第１実施形態と同様、ビア２と内層配線３による内部配線が形成されており、アルミナ積層基板１の表面にビア２と接続されたワイヤランド１０、検査ランド６が形成されている。
そして、ベアチップの半導体素子１１を接着剤（例えば、エポキシ樹脂と銀フィラーからなるもの）１２でアルミナ積層基板１上に固定し、金、アルミニウムなどのワイヤ１３を用いて、半導体素子１１の電極とワイヤランド１０をボンディングする。この後、エポキシ系樹脂などの封止樹脂１４にて半導体素子１１を樹脂封止する。なお、ワイヤランド１０は、銅、アルミニウム、金、銀などで形成された導体ランドとなっている。
【００１８】
この実施形態においても、ビア２および内層配線３により検査ランド６とワイヤランド１０を電気的に接続するようにしているから、封止樹脂１４の端部Ｂをバイパスした配線構造となり、封止樹脂１４の端部Ｂは、全て密着強度の高いアルミナと接するため、冷熱サイクル、湿気などのストレスに対し、封止樹脂１４の剥離を防止することができる。
【００１９】
なお、ワイヤランド１０上にワイヤ１３をボンディングする場合、ビア２の直上は面粗度が大きいため、図５（ａ）に示すように、ビア２の直上位置ではワイヤ１３のボンディングが行いにくい。このため、図５（ｂ）に示すように、ビア２をワイヤランド１０の中心からずれた位置に形成し、ワイヤ１３をビア２の直上とならない位置にてボンディングするのが好ましい。
【００２０】
この実施形態においては、絶縁性基板としては、アルミナ積層基板の他、低温焼成積層基板、単層基板、印刷多層基板を用いることができる。なお、上記第１、第２実施形態において、検査ランド６は、導体ランド４、１０と１対１の関係で形成する必要はなく、検査に用いる端子端子に対応した数だけ形成するようにすればよい。
【図面の簡単な説明】
【図１】本発明の第１実施形態を示すフリップチップＩＣの実装構造を示す図である。
【図２】本発明の第１実施形態において、フリップチップＩＣを実装する前の状態を示す図である。
【図３】本発明の第１実施形態において、絶縁性基板として印刷多層基板を用いた場合の構造を示す図である。
【図４】本発明の第２実施形態を示すベアチップ半導体素子の実装構造を示す図である。
【図５】図４に示す実施形態において、ワイヤランドに対するビアの形成位置を説明するための図である。
【図６】従来のフリップチップＩＣの実装構造を示す図である。
【符号の説明】
１…アルミナ積層基板、２…ビア、３…内層配線、４…導体ランド、
６…検査ランド、７…フリップチップＩＣ、８…はんだバンプ、
９…補強用樹脂、１０…ワイヤランド、１１…ベアチップの半導体素子、
１３…ワイヤ、１４…封止樹脂。

Claims (3)

  1. 表面に複数の導体ランド（４）が形成され、内部に前記複数の導体ランド（４）のそれぞれと電気接続される内部配線（２、３）が形成された絶縁性基板（１）としてのアルミナ基板と、
    前記アルミナ基板（１）上に実装され前記複数の導体ランド（４）とフリップチップ接合される半導体素子（７）とを備え、
    前記半導体素子（７）と前記アルミナ基板（１）の間に補強用樹脂（９）が注入されてなる半導体素子の実装構造において、
    前記半導体素子（７）を検査するための複数の検査ランド（６）が前記アルミナ基板（１）の表面に形成されており、
    前記補強用樹脂（９）のフィレット部（Ａ）をバイパスして前記複数の検査ランド（６）と前記複数の導体ランド（４）とをそれぞれ電気的に接続するように、前記アルミナ基板（１）に内部配線（２、３）を形成し、前記補強用樹脂（９）のフィレット部（Ａ）が前記複数の検査ランド（６）への配線と接しなく、すべて前記アルミナ基板（１）と接していることを特徴とする半導体素子の実装構造。
  2. 表面に複数の導体ランド（１０）が形成され、内部に前記複数の導体ランド（１０）のそれぞれと電気接続される内部配線（２、３）が形成された絶縁性基板（１）と、
    前記絶縁性基板（１）上に実装され前記複数の導体ランド（１０）と電気接続される半導体素子（１１）とを備え、
    前記半導体素子（１１）が封止樹脂（１４）にて封止されてなる半導体素子の実装構造において、
    前記半導体素子（１１）を検査するための複数の検査ランド（６）が前記絶縁性基板（１）の表面に形成されており、
    前記封止樹脂（１４）の端部（Ｂ）をバイパスして前記複数の検査ランド（６）と前記複数の導体ランド（１０）とをそれぞれ電気的に接続するように、前記絶縁性基板（１）に内部配線（２、３）を形成し、前記封止樹脂（１４）の端部（Ｂ）が前記複数の検査ランド（６）への配線と接しなく、すべて前記絶縁性基板（１）と接していることを特徴とする半導体素子の実装構造。
  3. 前記絶縁性基板（１）は積層基板であって、前記複数の検査ランド（６）は、前記絶縁性基板（１）に形成されたビア（２）と内層配線（３）を介して前記複数の導体ランド（４、１０）にそれぞれ電気的に接続されていることを特徴とする請求項１又は２に記載の半導体素子の実装構造。
JP02808797A 1997-02-12 1997-02-12 半導体素子の実装構造 Expired - Fee Related JP3704864B2 (ja)

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