WO1999060831A1 - Printed circuit board and method of production thereof - Google Patents
Printed circuit board and method of production thereof Download PDFInfo
- Publication number
- WO1999060831A1 WO1999060831A1 PCT/JP1999/002512 JP9902512W WO9960831A1 WO 1999060831 A1 WO1999060831 A1 WO 1999060831A1 JP 9902512 W JP9902512 W JP 9902512W WO 9960831 A1 WO9960831 A1 WO 9960831A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- wiring board
- printed wiring
- conductor
- land
- wiring pattern
- Prior art date
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
- H05K1/0256—Electrical insulation details, e.g. around high voltage areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
- H05K1/0265—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09236—Parallel layout
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09254—Branched layout
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09272—Layout details of angles or corners
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09454—Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09627—Special connections between adjacent vias, not for grounding vias
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0594—Insulating resist or coating with special shaped edges
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49194—Assembling elongated conductors, e.g., splicing, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/31504—Composite [nonstructural laminate]
Definitions
- the present invention relates to a printed wiring board on which a wiring pattern is formed, and more particularly to a printed wiring board that can be suitably used for a multilayer build-up wiring board and a method for manufacturing the printed wiring board.
- an insulating layer 250 having an opening 250 a serving as a via hole is formed on both surfaces of the core substrate 230, and the surface of the interlayer resin insulating layer 250 is uniformly electrolessly plated with a copper film 2.
- Form 52 (Fig. 32 (A)).
- a resist film (not shown) for forming a resist on the electroless plated copper film 255
- the resist film is exposed and developed to form a plating resist 255.
- the core substrate 230 is immersed in an electrolytic plating solution, and a current is applied through the electroless plating copper film 252, so that the electrolytic plating copper film 254 is formed on the non-formed portion of the resist 254. 6 is deposited (Fig.
- FIG. 33 (B) shows a section taken along line 8-8 in FIG. 32 (E).
- multi-layer printed wiring boards adopt a design in which branched wiring is drawn from one main wiring to prevent disconnection. Therefore, as shown in Fig. 33 (A) and Fig. 33 (B) A T-shaped intersection X occurs at
- the wiring pattern was broken at the intersection X described above. That is, as described above with reference to FIG. 32 (C), the wiring pattern 258 is formed by the force X formed at the non-formed portion of the resist 254 at the intersection X of FIG. 33 ( ⁇ ). As shown in the figure, at the corner C where the wall surfaces 258 ⁇ 3 and 258/3 of the wiring pattern 255 at the intersection intersect at 90 ° or less (right angle in this case), the plating solution does not flow around. And the wiring pattern becomes thinner. For this reason, disconnection sometimes occurred. Further, as shown in FIG.
- a bubble B may remain between the wiring pattern 255 b and the interlayer resin insulating layer 350.
- the bubbles B expand when the printed wiring board is thermally contracted, which causes a failure of the printed wiring board.
- a multilayer build-up wiring board is formed by alternately stacking interlayer resin insulating layers and wiring layers on a core substrate.
- a multilayer build-up wiring board is mainly manufactured by an additive method, and the above-mentioned wiring layer is formed in an opening of a resist formed on an interlayer resin insulating layer by electrolytic or electroless plating.
- the upper and lower wiring layers are electrically connected by via holes penetrating the interlayer resin insulation layer.
- This wiring layer is composed of a via hole land used as a via hole receiving tray, a wiring pattern, a battery portion to which a high potential such as a power supply is applied and plays a role as an electrode of a capacitor, and the like.
- the minimum value of the size of the via hole land, the width of the wiring pattern, and the distance between these insulations are determined by the resolution of the resist, the degree of adhesion, etc., and are larger than the minimum value.
- the via hole land and the wiring pattern are manufactured.
- the multilayer build-up wiring board for the package plays a role as a connector for electrically connecting electronic components such as an IC chip mounted on the upper surface and a printed wiring board such as a mother board located on the lower surface.
- a narrower wiring pattern line width, insulation interval, and land diameter are required.
- these values are smaller than the above-mentioned minimum values, the desired wiring cannot be formed due to slight variations in process conditions, and the probability of disconnection of the wiring, short-circuiting between the wirings, etc. increases. The yield decreases.
- the thickness of the interlayer resin insulating layer varies depending on the density at which the wiring patterns are arranged.
- the thickness may be small where the wiring density is high, and may be thick where the density is low (where there is no signal line around).
- the thickness may be thicker in a portion where the wiring density is high, and thinner in a portion where the wiring density is low.
- the plating thickness varies.
- the electric field is concentrated at the time of electrolytic plating and the thickness becomes thicker at the place where the wiring density is low, and conversely, the electric field is dispersed at the place where the wiring density is high and the thickness of the signal line becomes thinner.
- multilayer build-up wiring boards are mainly formed by semi-additive methods in order to obtain higher performance.
- a resist pattern is formed, and electricity is passed through the electroless plating film to prevent formation of a resist.
- a conductor layer is formed by forming an electrolytic plating film on the part.
- the resist is removed, and then the electroless plating film under the resist is removed by light etching.
- the connection between the conductor layer in the multilayer core substrate and the build-up wiring layer is performed by connecting inner layer pads wired from through holes to the surface of the multilayer core substrate. And a via hole is connected to the inner layer pad. That is, an inner layer pad for connecting a via hole to an upper layer is added to the land of the through hole, or an inner layer pad for connecting the via hole is connected to the land of the through hole via a wiring.
- the package substrate On the other hand, on the package substrate, more bumps are formed on the back surface than on the front surface. This is because wiring from a plurality of bumps on the back side is connected to bumps on the front side while being integrated. For example, the number of power supply lines required to have low resistance to signal lines was 20 at the bumps on the back side (mother board side), but one at the front side (IC chip side). Will be integrated.
- the ability to integrate the wiring at the same pace between the build-up wiring layer formed on the front side of the core substrate and the build-up wiring layer formed on the back side of the core board has the advantage that the upper build-up wiring layer and the lower build-up wiring layer This is desirable in order to minimize the number of layers.
- the number of through holes that can be formed in the multilayer core substrate is limited.
- the wiring was integrated to some extent in the build-up wiring layer on the back side, and then connected to the build-up wiring layer on the front side through through holes in the multilayer core substrate.
- the build-up wiring layer on the front side has a lower wiring density, and thus does not originally require the same number of layers as the build-up wiring layer on the back side.
- the number of build-up wiring layers on the front and back were made different, warping would occur due to asymmetry, so the number of layers on the front and back were the same.
- the number of layers of the build-up wiring layer on the back side must be increased, and the number of layers is equal to the number of layers on the back side where the number of layers is increased.
- the build-up wiring layer on the front side had to be formed.
- the present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a printed wiring board and a method of manufacturing the printed wiring board which do not cause disconnection of a wiring pattern. is there.
- An object of the present invention is to provide a high-density printed wiring board that can be manufactured with a high yield.
- An object of the present invention is to provide a printed wiring board having excellent uniformity of the thickness of a wiring pattern and an interlayer resin insulating layer.
- An object of the present invention is to increase the density of through holes formed in a core substrate. Accordingly, an object of the present invention is to provide a printed wiring board and a method for manufacturing a printed wiring board, which can reduce the number of build-up layers. Disclosure of the invention
- Claim 1 is a printed wiring board having a wiring pattern on an insulating substrate or a substrate provided with an interlayer resin insulating layer, in order to achieve the above object,
- a technical feature is that a fillet is added to the intersection of the wiring patterns.
- Claim 2 is a printed wiring board having a wiring pattern on an insulating substrate or a substrate provided with an interlayer resin insulating layer,
- a technical feature is that a fillet is added to a corner portion of 90 ° or less at an intersection of the wiring patterns.
- the fillet is added at the intersection of the wiring pattern of the printed wiring board and at a corner of 90 ° or less, the wiring pattern is narrowed at the intersection. There is no disconnection. Also, no cracks occur due to heat shrinkage.
- a fillet is added to an intersection of the wiring pattern of the printed wiring board, and no stress is concentrated at the intersection, so that no disconnection occurs in the wiring pattern. Since no air bubbles remain between the intersection of the wiring pattern and the interlayer resin insulating layer, the reliability of the printed wiring board is improved.
- Claim 4 is a step of forming a resist having an opening for forming a wiring pattern on an insulating substrate or a substrate provided with an interlayer resin insulating layer;
- Forming a wiring pattern by depositing a metal layer in the opening of the resist.
- a corner portion of 90 ° or less which is an intersection of the wiring pattern, is chamfered.
- a wiring pattern is formed so that the chamfered portion becomes a fillet.
- the fillet since the fillet is added, the wiring pattern becomes thin at the intersection, and there is no breakage.
- Claim 5 is a step of forming a resist having an opening for forming a wiring pattern on an insulating substrate or a substrate on which an interlayer resin insulating layer is provided, wherein: Forming a resist by chamfering a corner of 90 ° or less;
- Forming a wiring pattern by depositing a metal layer in the opening of the resist;
- a portion which is an intersection of the wiring pattern and has a corner portion of 90 ° or less is formed.
- the resist is formed by chamfering.
- a wiring pattern is formed so that the chamfered portion becomes a fillet.
- an interlayer resin insulating layer and a wiring pattern are further formed.
- the fillet is added, the wiring pattern at the intersection does not become thin and the wire breaks.
- a fillet is added, so that stress is not concentrated at the intersection, so there is no disconnection in the wiring pattern, and bubbles remain between the intersection of the wiring pattern and the interlayer resin insulating layer. The reliability of the printed wiring board is increased because there is no wiring.
- Claim 6 is a printed wiring board on which a conductor portion and a wiring pattern are provided to achieve the above object,
- the wiring pattern is provided with a narrow portion in accordance with the distance between the adjacent conductors.
- the insulation distance between the wiring pattern and the conductor portion can be maintained, and high density can be achieved.
- the width of the wiring pattern is not narrowed at a portion where the insulation distance from the conductor portion can be maintained, the possibility of disconnection is reduced, and the yield is increased.
- Claim 7 is a printed wiring board provided with a conductor portion and a wiring pattern, wherein the wiring pattern has a technical feature that the width of a portion sandwiched between the conductor portions is reduced.
- the insulation distance between the wiring pattern and the conductor portion is maintained, and the density can be increased.
- the portion where the insulation distance from the conductor portion can be maintained that is, the portion not sandwiched between the conductor portions is not reduced in width of the wiring pattern, so that the possibility of disconnection is reduced and the yield is increased.
- the width is narrowed toward the center of the wiring pattern, so that the insulation distance from both conductors is maintained. Can be.
- the width of each of the wiring patterns is reduced to a side opposite to the conductor portion.
- the width of each of the wiring patterns is reduced to a side opposite to the conductor portion, so that insulation from both conductor portions is achieved. You can keep the distance.
- the technical feature is that at least a part of the central wiring pattern excluding both sides is narrowed toward the center side, and the wiring patterns on both sides are narrowed toward the side opposite to the conductor.
- the width of at least a part of the central wiring pattern excluding both sides is reduced toward the center side, and the wiring on both sides is reduced.
- Each pattern is narrower on the opposite side of the conductor Therefore, the insulation distance from both conductors and the insulation distance between the wiring patterns can be maintained.
- the pitch of the wiring pattern of the multilayer build-up wiring board can be narrowed, high density can be realized without increasing the number of build-up layers.
- the pitch between via hole lands or mounting pads can be reduced, so that high density can be realized without increasing the number of build-up layers.
- claim 14 is a printed wiring board comprising an interlayer resin insulation layer and a conductor layer alternately laminated
- a technical feature is that a dummy conductor is provided around a wiring pattern constituting the conductor layer.
- claim 15 is a printed wiring board formed by alternately laminating interlayer resin insulating layers and conductor layers,
- a technical feature is that a dummy conductor is provided around a plurality of wiring patterns constituting the conductor layer.
- the dummy conductor is provided around the wiring pattern, when the conductor layer is formed by electroplating, the electric field does not concentrate and the wiring pattern is defined. It can be formed in the thickness of. For this reason, it is possible to form an isolated wiring pattern and a densely arranged wiring pattern with a uniform thickness, and furthermore, it is possible to make the thickness of the interlayer resin insulating layer above the wiring pattern uniform, The electrical characteristics of the printed wiring board can be improved. It should be noted that the wiring pattern and the dummy conductor in the present invention do not have to be formed on a so-called core substrate.
- the width of the dummy conductor is set to be 1 to 3 times the minimum width of the wiring pattern, no electric field concentration occurs, and the wiring pattern and the dummy conductor Can be formed to a predetermined thickness.
- the distance between the dummy conductor and the wiring pattern is set to be 1 to 3 times the minimum width of the wiring pattern, no electric field concentration occurs, and the wiring pattern and the dummy pattern are not formed.
- the conductor can be formed to a predetermined thickness.
- Claim 18 is a printed wiring board formed by alternately laminating interlayer resin insulation layers and conductor layers,
- a technical feature is that a dummy conductor is provided around the isolated land constituting the conductor layer.
- the dummy conductor is provided around the isolated land, when the conductor layer is formed by electroplating, no electric field concentration occurs, and the isolated land has a predetermined thickness. Can be formed. For this reason, it is possible to form the isolated land and the land in the dense portion with a uniform thickness, and it is possible to enhance the electrical characteristics of the printed wiring board.
- the width of the dummy conductor is set to 1/6 to 3 times the diameter of the land, the concentration of the electric field does not occur, and the land and the dummy conductor are formed to a predetermined thickness. Can be.
- the minimum distance between the dummy conductor and the isolated land is set to 1/6 to 3 times the land diameter, no electric field concentration occurs, and the land and the dummy conductor have a predetermined thickness. Can be formed.
- Claim 22 is a printed wiring board formed by alternately laminating an interlayer resin insulating layer and a conductor layer,
- a technical feature is that a dummy conductor is provided on the conductor layer and a fillet is formed at an intersection of the dummy conductor and the dummy conductor.
- Claim 23 is a printed wiring board formed by alternately laminating interlayer resin insulation layers and conductor layers,
- a technical feature is that a dummy conductor is provided in the conductor layer, and a fillet is formed at a right angle or an acute angle at an intersection of the dummy conductor and the dummy conductor.
- the interlayer resin insulating layer and the conductor layer are alternately laminated, and build-up wiring layers in which each conductor layer is connected by a via hole are formed on both surfaces of the core substrate.
- a technical feature is that a circular land is formed in a through hole formed in the core substrate, and a via hole is connected to the land.
- a via hole is provided on the land of the through hole, and no pad for via hole connection is added to the land, so that the number of through holes provided on the core substrate may be increased. it can.
- the radius of the through hole is 17 or less and 125 m or more. If it exceeds 175 m, the number of through-holes provided on the core substrate will decrease, and if it is less than 125 m, it will be difficult to form by drilling.
- the radius of the land is larger than the radius of the through-hole by 75 zm to 175 m. This means that the minimum technically possible values are via hole diameter 25 / zm, via hole opening error to land ⁇ 12.5 (total 25) rn, land error to through hole 25 m, Because the sum of these is 75.
- the minimum value that can be economically mass-produced is a via hole diameter of 35 wm, an error of the via hole opening with respect to the land ⁇ 20 (total of 40) m, and a land error of 100 mm with the through hole. Yes, because the sum of these is 175 / m. That is, the land is larger than the radius of the through hole by 75 m to 1 75 m.
- the radius of the land is set to a value equal to or greater than the sum of the diameter of the through hole, the error range of the land with respect to the through hole, the opening diameter, and the error range of the opening with respect to the land.
- the land diameter is set to 700 xm or less, the arrangement density of the through holes can be increased as compared with the conventional configuration in which a land for via hole arrangement is added.
- the radius of the land is set to 200 to 350 m.
- the minimum technically possible values are a through hole radius of 125 Atm, a via hole diameter of 25 / im, a via hole opening error to land of ⁇ 12.5 (total 25) m, and land error of through hole 25. There is a total of 200 m.
- the minimum values that can be mass-produced economically are: through hole radius 175 m, via hole diameter 35 m, via hole opening error ⁇ 20 (total 40), land error with through hole 100 m.
- the total (radius) is 350 m.
- a plating resist is formed on a substrate and a metal layer is deposited in the opening to form a wiring pattern by a full additive method.
- plating is performed after a metal layer is provided on the substrate.
- a semi-additive method can be employed in which a resist is formed, a metal layer is further deposited in the opening, the plating resist is removed, and the metal layer under the plating resist is removed to form a wiring pattern.
- an electroless plating adhesive as the interlayer resin insulating layer.
- This adhesive for electroless plating is obtained by dispersing heat-resistant resin particles soluble in a cured acid or an oxidizing agent in an uncured heat-resistant resin hardly soluble in an acid or an oxidizing agent. Optimal.
- the heat-resistant resin particles are dissolved and removed, and a roughened surface composed of an octopus pot-shaped anchor can be formed on the surface.
- the heat-resistant resin particles that have been particularly cured include: 1) a heat-resistant resin powder having an average particle diameter of 10 m or less, and 2) a heat-resistant resin powder having an average particle diameter of 2 m or less.
- Examples of the heat-resistant resin hardly soluble in an acid or an oxidizing agent include a “resin composite comprising a thermosetting resin and a thermoplastic resin” or a “photosensitive resin and a thermoplastic resin”. It is desirable to be composed of a “resin composite made of fat”. This is because the former has high heat resistance, and the latter can form an opening for a via hole by photolithography.
- thermosetting resin an epoxy resin, a phenol resin, a polyimide resin, or the like can be used.
- methacrylic acid, acrylic acid or the like is subjected to an acrylate reaction with a thermosetting group.
- epoxy resin acrylate is most suitable.
- a nopolak type epoxy resin such as a phenol novolak type or a cresol novolak type, or an alicyclic epoxy resin modified with dicyclopentene can be used.
- Thermoplastic resins include polyethersulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenylene ether (PPE), and polyether imide (PI ) Can be used.
- PES polyethersulfone
- PPS polysulfone
- PES polyphenylene sulfone
- PPES polyphenylene sulfide
- PPE polyphenylene ether
- PI polyether imide
- the mixing weight ratio of the heat-resistant resin particles is 5 to 50% by weight, preferably 10 to 40% by weight, based on the solid content of the heat-resistant resin matrix.
- the heat-resistant resin particles are preferably amino resin (melamine resin, urea resin, guanamine resin), epoxy resin, and the like.
- the adhesive may be composed of two layers having different compositions.
- solder resist layer can be added to the surface of the multilayer build-up wiring board.
- resins can be used as the solder resist layer to be added to the surface of the multilayer build-up wiring board.
- bisphenol A-type epoxy resin acrylate of bisphenol A-type epoxy resin, nopolak-type epoxy resin A resin obtained by curing an acrylate of a novolak type epoxy resin with an amine curing agent or an imidazole curing agent can be used.
- solder resist layer is composed of a resin having a rigid skeleton, peeling may occur. Therefore, the provision of the reinforcing layer can also prevent the solder resist layer from peeling off.
- the acrylate of the novolak-type epoxy resin an epoxy resin obtained by reacting glycidyl ether of phenol novolac or cresol novolac with acrylic acid, methacrylic acid, or the like can be used.
- the imidazole curing agent is desirably liquid at 25 ° C. This is because the liquid can be uniformly mixed.
- liquid imidazole curing agent examples include tribenzyl-2-methylimidazole (product name: 1 B2MZ), tocianoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN), and 4-methyl-2-ethylimidazolic acid. (Product name: 2E4MZ) can be used.
- the addition amount of the imidazole curing agent is preferably 1 to 10% by weight based on the total solid content of the solder resist composition. The reason for this is that if the added amount is within this range, the uniform mixing is slow.
- glycol ether-based solvent it is desirable to use a glycol ether-based solvent as the solvent in the composition before curing the solder resist.
- solder-resist layer using such a composition does not generate free acid and does not oxidize the copper pad surface. It is also less harmful to the human body.
- glycol ether-based solvent one having the following structural formula, particularly preferably at least one selected from diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG) is used. These solvents can completely dissolve the reaction initiators benzophenone and Michler's ketone by heating at about 30 to 50 ° C.
- DMDG diethylene glycol dimethyl ether
- DMTG triethylene glycol dimethyl ether
- solder resist composition In addition to the solder resist composition described above, various defoaming agents and repelling agents, heat-resistant resin, a thermosetting resin for improving base resistance and providing flexibility, and for improving resolution. , A photosensitive monomer or the like can be added.
- the leveling agent is preferably made of an acrylic ester polymer.
- the initiator Irgacure I907 from Ciba-Geigy I, and as the photosensitizer, DETX-S from Nippon Kayaku are preferable.
- a dye or pigment may be added to the solder resist composition. This is because the wiring pattern can be hidden. It is desirable to use a phthalocyanine line as this dye.
- thermosetting resin As an additional component, a bisphenol-type epoxy resin can be used.
- This bisphenol-type epoxy resin includes bisphenol A-type epoxy resin and bisphenol F-type epoxy resin. The former is required when base resistance is important, and the latter is required when lower viscosity is required. The latter is better.
- a polyvalent acryl-based monomer can be used as the photosensitive monomer as an additional component. This is because polyacrylic monomers can improve the resolution.
- DPE-6A manufactured by Nippon Kayaku and R-604 manufactured by Kyoeisha Chemical can be used as the polyvalent acrylic monomer.
- solder resist compositions have a ratio of 0.5 to 25 at 25: lOPa-Si, more preferably 1 to 10Pas. This is because the viscosity is easy to apply in a roll.
- FIG. 1 is a process chart of a method for manufacturing a multilayer printed wiring board according to a first embodiment of the present invention.
- FIG. 2 is a process chart of a method for manufacturing a multilayer printed wiring board according to the first embodiment.
- FIG. 3 is a process chart of the method for manufacturing a multilayer printed wiring board according to the first embodiment.
- FIG. 4 is a process chart of the method for manufacturing a multilayer printed wiring board according to the first embodiment.
- FIG. 5 is a process chart of the method for manufacturing a multilayer printed wiring board according to the first embodiment.
- FIG. 6 is a process chart of the method for manufacturing a multilayer printed wiring board according to the first embodiment.
- FIG. 7 is a process chart of a method for manufacturing a multilayer printed wiring board according to the first embodiment.
- FIG. 8 is a process chart of a method for manufacturing a multilayer printed wiring board according to the first embodiment.
- FIG. 9 is a view on arrow C of the core substrate in the step shown in FIG. 4 (M).
- FIG. 10 is a view on arrow E of the core substrate in the step shown in FIG. 4 (O).
- FIG. 11 is a plan view of a core substrate on which a wiring pattern according to a modification of the first embodiment is formed.
- FIG. 12 is an explanatory diagram showing a wiring pattern of the first embodiment.
- FIG. 13 is a view showing a cross section of a multilayer build-up wiring board according to a second embodiment of the present invention.
- FIG. 14 (A) is a cross-sectional view taken along the line A--A of the multilayer build-up wiring board shown in FIG. 13, and FIG. 14 (B) is a plan view showing an example of a wiring pattern. is there.
- FIG. 15 is a plan view showing an example of a wiring pattern.
- FIG. 16 is a plan view showing an example of the wiring pattern of the second embodiment.
- FIG. 17 is a sectional view of a multilayer build-up wiring board according to a third embodiment of the present invention.
- FIG. 18 is a cross-sectional view taken along the line XX of FIG.
- FIG. 19 is an enlarged view of a portion A in FIG. 18, and (B) of FIG. 19 is an enlarged view of a portion B in FIG.
- FIG. 20 is an enlarged view of a portion C in FIG. 18, and (C ′) of FIG. 20 is an enlarged view of an isolated land.
- FIG. 21 is an enlarged view of a portion D in FIG.
- FIG. 22 is an enlarged view of a signal line and a dummy conductor.
- FIG. 23 is a process chart for manufacturing a printed wiring board according to the fourth embodiment of the present invention.
- FIG. 24 is a process chart of manufacturing a printed wiring board according to the fourth embodiment.
- FIG. 25 is a manufacturing process diagram of the multilayer printed wiring board according to the fourth embodiment.
- FIG. 26 is a manufacturing process diagram of the printed wiring board according to the fourth embodiment.
- FIG. 27 is a manufacturing process diagram of the printed wiring board according to the fourth embodiment.
- FIG. 28 is a drawing showing the manufacturing process of the printed wiring board according to the fourth embodiment.
- FIG. 29 is a drawing showing the manufacturing process of the printed wiring board according to the fourth embodiment.
- FIG. 30 is a sectional view of the method for manufacturing a printed wiring board according to the fourth embodiment of the present invention.
- FIG. 31 is a BB cross-sectional view of the core substrate shown in FIG.
- FIG. 32 is a process chart of a method for manufacturing a multilayer printed wiring board according to the prior art.
- FIG. 33 (A) is a diagram showing a wiring pattern of a conventional multilayer printed wiring board, and FIG. 33 (B) is a BB cross-sectional view of FIG. 32 (E).
- compositions of A. Electroless plating adhesive, B. Interlayer resin insulating agent, and C. Resin filler used in the method of manufacturing the multilayer printed wiring board according to the first embodiment will be described.
- PES polyether sulfone
- epoxy resin particles manufactured by Sanyo Chemical Industries, Polymer Pole
- the filler used in the present invention is preferably composed of at least one kind of bisphenol-type epoxy resin selected from bisphenol F-type epoxy resin and bisphenol A-type epoxy resin, an imidazole curing agent, and inorganic particles. .
- the particle diameter of the inorganic particles is desirably 0.1 to 5. Om.
- the amount of the inorganic particles to be mixed is preferably 1.0 to 2.0 times the weight of the epoxy resin in weight ratio.
- silica silica, alumina, mullite, SiC and the like are preferable.
- Bisphenol ⁇ type epoxy monomer (manufactured by Yuka Shell, Epiko one preparative 8 28) 100 parts by weight, eight 1 2 ⁇ 3 spherical particles 150 parts by weight of the average particle diameter 1.5 ⁇ 11 in the surface, N- main Chirupirori pyrrolidone (NMP) 30 parts by weight, leveling agent (manufactured by San Nopco, Le S 4) Stir and mix 1.5 parts by weight, and adjust the viscosity of the mixture to 45,000-49, OOOcps at 23 ⁇ 1 ° C.
- NMP N- main Chirupirori pyrrolidone
- Imidazole curing agent (Shikoku Chemicals, 2E4MZ-C) 6.5 parts by weight.
- a copper-clad laminate in which 12 copper foils 32 are laminated on both sides of a substrate 30 made of a 1 mm thick glass epoxy resin or BT (bismaleimide triazine) resin 3
- a substrate 30 made of a 1 mm thick glass epoxy resin or BT (bismaleimide triazine) resin 3
- OA a copper-clad laminate 3OA is drilled, and an electroless plating 33 is deposited in the through hole to form a through hole 36 (FIG. 1 (B)).
- a conductor layer 34 is formed on the core substrate 30 as shown in FIG. 1 (C).
- a roughened layer 38 is provided on the surfaces of the conductor layer 34 and the through hole 36 by an oxidation-reduction treatment using NaOH (lOgZl) and NaBH 4 (6 g / 1).
- the filler is heat-cured and polished by belt sander polishing using # 400 belt polishing paper (manufactured by Sankyo Rikagaku) so that the resin filler does not remain on the surface of the through-hole land 36a and the conductor layer 34. Then, buff polishing for removing scratches caused by the belt sander polishing is performed with SiC abrasive grains. Such a series of polishing is similarly performed on the other surface of the substrate.
- heat treatment is performed at 100 ° C. for 1 hour and at 150 ° C. for 1 hour to cure the resin filler 40.
- the surface layer of the resin filler 40 filled in the through holes 36 and the like and the roughened layer on the upper surface such as the through hole lands 36a are removed, and both surfaces of the substrate 30 are smoothed.
- the roughened layer 42 is formed on the surface of the roughened layer 42, and a Sn layer (not shown) having a thickness of 0.3 wm can be provided on the surface of the roughened layer 42.
- the formation method is as follows.
- the substrate 30 was acid-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to provide a Pd catalyst.
- a catalyst solution comprising palladium chloride and an organic acid to provide a Pd catalyst.
- a roughened layer 42 of Cu—Ni—P alloy is formed on the upper surface and the land of the through hole 36a.
- the surface of the through-hole land 36 a and the surface of the conductive layer 34 may be roughened by an etching solution containing a cupric complex and an organic acid. It is possible and can be roughened by redox treatment.
- the raw material composition for preparing the adhesive for electroless plating of the composition A described above is stirred and mixed to adjust the viscosity to 7 Pa, s to obtain an adhesive solution for electroless plating (for upper layer). .
- a photomask film (not shown) on which a black circle of 85 im ⁇ is printed is brought into close contact with both surfaces of the substrate 30 on which the adhesive layer 50 is formed in the above (8), and the pressure is 500 mJZcm 2 by an ultra-high pressure mercury lamp. Expose. This was spray-developed with DMT G solution, the further, exposing the substrate to a super-high pressure mercury lamp at 3000mJZcm 2, 1 hour at 100 ° C, 1 hour at 120 ° C, heat treatment subsequent 3 hours at 0.99 ° C By performing (post-bake), as shown in Fig.
- the thickness of the film having an 85 mm ⁇ opening (via hole forming opening) 48 with excellent dimensional accuracy equivalent to a photomask film 35 An interlayer resin insulation layer of 50 m (two-layer structure) 50 is formed. Note that the tin plating layer can be partially exposed in the opening 48 serving as a via hole.
- the substrate 30 in which the openings 48 are formed is immersed in chromic acid for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulation layer 50, as shown in FIG. 3 (J). Then, the surface of the interlayer resin insulation layer 50 is made a roughened surface 51, and thereafter, it is immersed in a neutralizing solution (manufactured by Shipley) and then washed with water.
- a neutralizing solution manufactured by Shipley
- the surface of the interlayer resin insulating layer 50 and the opening 48 for the via hole are formed. Attach a catalyst core to the inner wall.
- the substrate is immersed in an electroless copper plating aqueous solution having the following composition, and as shown in Fig. 3 (K), a 0.6 / m-thick electroless copper plating film is formed on the entire rough surface.
- FIG. 4 (M) is a view taken in the direction of arrow C, that is, the core substrate on which the plating resist 54 is formed.
- FIG. 9 shows a plan view of No. 30.
- the line DD in FIG. 9 is a line corresponding to the cut end in FIG. 4 (M).
- the plating resist 54 has a circular opening 54a for forming a land or a via hole and a linear opening 54b for forming a wiring pattern.
- 4b is a bent portion, and a corner L in which the crossing angle of the side wall 54/3 of the portion is 90 ° or less is chamfered.
- the electroless plating film 52 under the plating resist 54 is etched with a mixed solution of sulfuric acid and hydrogen peroxide.
- a wiring pattern 58b, a via hole 60, and a land 61 having a thickness of 18 ⁇ comprising an electroless copper plating film 52 and an electrolytic copper plating film 56 are formed by dissolving and removing the film.
- the above-mentioned core substrate 30 is immersed in chromic acid of 800 g / l at 70 ° C for 3 minutes to form an adhesive layer for electroless melting without wiring patterns 58 b, via holes 60 and lands 61.
- the surface of 50 is etched by 1 zm to remove the palladium catalyst on the surface.
- FIG. 10 is a view taken in the direction of arrow E in FIG. 4 (4), that is, a plan view of the core substrate 30.
- the line FF in FIG. 10 is a line corresponding to the cut end in FIG. 4 ( ⁇ ).
- the wiring patterns 58 a, 58 b, 58 c, 58 d, 58 e, 58 f, 58 g, via holes 60, and lands 61 are formed on the core substrate 30.
- a fillet F is added to a corner portion C of the intersection X of the wiring pattern 58b where the intersection angle of the side wall 58/3 of the wiring pattern is 90 ° or less.
- the side wall 58 of the wiring pattern 58c and the side wall 5 of the wiring pattern 58d are formed.
- a fillet F is added to the corner C where the intersection angle with 8/3 is 90 ° or less.
- the wiring pattern (signal line) 58 e and the wiring pattern (signal line) 58 f, and the intersection of the side wall 58 ⁇ of the wiring pattern Fillet F is added to corner C at an angle of 90 ° or less.
- the adjacent fillets F added to the wiring pattern (signal line) 58e and the wiring pattern (signal line) 58f partially overlap each other. Further, a fillet F is also added to a corner portion L where the wiring pattern 58 g is bent and the crossing angle of the side wall 54/3 of the portion is 90 ° or less (here, a right angle).
- the corners of the resist 54 described above with reference to FIG. 9 are chamfered so that the fillet F is added to the intersections X of the wiring patterns 58, and the spillage of the plating liquid is performed.
- the fillet F is added to the intersection X of the wiring pattern 58, it is possible to prevent the occurrence of disconnection due to the concentration of stress that occurs when the printed wiring board repeats thermal contraction.
- the line width of the wiring pattern is formed to be 50 wm or less, preferably 15 to 50 m, and the width of the fillet F is formed to be 75 to 100 m.
- the width of the fillet F is set to 70 or more, the stress collection that occurs when the printed wiring The occurrence of disconnection due to the inside can be prevented. Therefore, if the line width is set to 70 or more, no additional filet is required.
- the substrate 30 on which the wiring patterns 58 are formed is copper sulfate 8 gZ, nickel sulfate 0.6 gZl, citric acid 15 gZ, sodium hypophosphite 29 g / 1, boric acid 31 gZ1, surfactant 0. 5 g of 1 g / 1, and immersed in an electroless plating solution having a pH of 9 to form a 3 / m-thick copper-nickel-phosphorous on the surface of the wiring pattern 58 and the via hole 60 as shown in FIG. 5 (P).
- a roughened layer 62 made of is formed. Instead of the roughening layer 62, the surfaces of the conductor circuit 58 and the via hole 60 can be roughened by an etchant or an oxidation-reduction treatment.
- steps (2) to (14) By repeating steps (2) to (14), a further upper interlayer resin insulation layer and a conductor circuit are formed. That is, an interlayer resin insulating material is provided on both sides of the substrate 30.
- a photomask film is brought into close contact with both surfaces of the substrate 30 on which the insulating layer 144 and the adhesive layer 146 are formed, exposed and developed to form an interlayer resin insulating layer 150 having openings (openings for forming via holes) 148.
- the surface of the interlayer resin insulation layer 150 is roughened (see FIG. 5 (R)).
- an electroless copper plating film 152 is formed on the surface of the substrate 30 subjected to the surface roughening treatment (see FIG. 6 (S)).
- a plating resist 154 is provided on the electroless copper plating film 152
- an electrolytic copper plating film 156 is formed on a portion where no resist is formed (see FIG. 6 (T)).
- the plating resist 15 is removed. 4. Dissolve and remove the lower electroless plating film 15 2 to form a conductor circuit (not shown), land 16 1 and via hole 16 0. Further, a roughened layer 162 is formed on the surface of the conductor circuit, land 161, and via hole 160 to complete a multilayer printed wiring board (see FIG. 7 (U)). Note that, in the step of forming the upper conductive circuit, Sn substitution was not performed.
- solder bumps are formed on the multilayer printed wiring board described above.
- a solder resist composition was coated in a thickness of 20 tm to the substrate 30, 2 0 min at 70 ° C, after the drying treatment for 30 minutes at 7 0 ° C, of l OO OM j ZCM 2 Exposure to UV light and DMTG development.
- nickel chloride 2.31X10- mo 1 Z 1, sodium hypophosphite 2. 8 X10 -. 1 mo 1 / Kuen sodium 1.85X10- 1 mo IZ 1, consisting of pH 4 5 free
- the substrate 30 was immersed in an electrolytic nickel plating solution for 20 minutes to form a nickel plating layer 72 having a thickness of 5 m in the opening 71.
- the substrate potassium gold cyanide 4. 1 X10- ⁇ mo 1 / and chloride
- solder paste is printed on the opening 71 of the solder resist layer 70, and the solder bump 76 is formed by forming a riff at 200 ° C. and soldering.
- a printed wiring board having bumps is manufactured.
- a triangular fillet F is added.
- the fillet in the example has a curved fillet F. That is, a fillet F is added to a corner portion C of the intersection X of the wiring pattern 58b where the intersection angle of the side wall 58] 3 of the wiring pattern is 90 ° or less.
- a fillet F is added to a corner C where the wiring pattern (signal line) 58c and the wiring pattern (signal line) 58d intersect and the crossing angle of the side wall 58 is 90 ° or less. Have been.
- the side wall 58 of the wiring pattern A fillet F is added to the corner C where the intersection angle of ⁇ is 90 ° or less. Further, the fillet F is also added to a corner portion L where the wiring pattern 58 g is bent and the crossing angle of the side wall 54/3 of the portion is 90 ° or less.
- the fillet of the modified example has the advantage that stress is unlikely to be concentrated, while the fillet shown in FIG. 10 has the advantage that the process for adding the fillet (mask pattern forming process) is easy.
- the fillet F is added to the intersection X of the wiring pattern of the printed wiring board and a corner C of 90 ° or less. No disconnection occurs due to stress concentration in the part. Further, the stress generated at the intersection of the wiring patterns does not cause cracks in the interlayer resin insulation layers (50, 150). Furthermore, since no air bubbles remain between the intersection X of the wiring pattern 58 and the interlayer resin insulating layer 150, the reliability of the printed wiring board is improved.
- FIG. 13 shows a cross section of a multilayer build-up wiring board according to a second embodiment of the present invention.
- Build-up wiring layers 90 A and 9 OB are formed on the front surface and the back surface of the multilayer core substrate 30.
- the built-up layers 90 A and 90 B are composed of a via hole 60, a via hole land 61, an interlayer resin insulation layer 50 on which a wiring pattern 58 is formed, a via hole 16 0, a land 16 1, Wiring pattern (not shown) And an interlayer resin insulation layer 150 formed with An upper via hole 160 is connected to the via hole land 61.
- solder bumps 76 U are formed to connect to bumps (not shown) on the IC chip, and on the back (lower) side, bumps on the motherboard (not shown) Solder bumps 76D for connection to are formed.
- the wiring pattern from the solder bump 76 U connected to the IC chip is routed toward the outer periphery of the board, and to the solder bump 76 D connected to the mother board It is connected.
- the built-up layer 9OA on the front side and the built-up layer 90B on the back side are connected via a through hole 36 formed in the core substrate 30.
- Fig. 14 (A) shows the A-A cross section of the multilayer build-up wiring board in Fig. 13.
- the X-X line in FIG. 14 (A) corresponds to the cut end in FIG.
- the via hole land 61 and the via hole 60 are formed to have a diameter of 140 to 200 m.
- the wiring pattern 58 has a narrow portion (hereinafter referred to as a narrow portion) 58b having a width of 30 mm according to the distance between the adjacent conductor portions (via holes, via hole lands), and a width of 40 to 50 mm.
- a normal line width portion of 50 zm (hereinafter referred to as a normal width portion) 58 a is formed.
- a portion of the two wiring patterns 58 sandwiched between the via hole lands 61 and 61 is a narrow portion 58b between the via hole lands 61 and 61.
- the area where the insulation distance (here, 40 ⁇ m) between the two wiring patterns 58 and the via hole land can be maintained is usually formed as 40 to 50 ⁇ m as the width part 58 a.
- each of the two via-hole lands 61 is narrowed on the opposite side to the via-hole land 61 so as to maintain an insulation distance from both via-hole lands 61.
- the wiring pattern 58 provided between the via hole 60 and the via hole land 61 has the insulation space (40 °) between the via hole 60 and the via hole land 61 even in the closest part. m) are all formed as normal width portions 58a.
- the wiring pattern 58 is formed by reducing the width of a portion (narrow portion) 58 a sandwiched between the conductor portion (via hole land 61).
- the insulation distance between the wiring pattern 58 and the conductor is maintained and the density is increased. This Therefore, high density can be realized without increasing the number of build-up layers.
- a portion where the insulation distance from the conductor portion can be maintained, that is, a portion (normal width portion) 58 a not sandwiched between the via hole lands 61 is not narrowed, so that it is disconnected in a later-described manufacturing process. Is reduced, and the yield can be prevented from lowering.
- FIGS. 14 (B), 15 (C), 15 (D), and 16. the shape of the wiring pattern 58 of the second embodiment will be described with reference to FIGS. 14 (B), 15 (C), 15 (D), and 16. .
- Fig. 14 (B) one wiring pattern sandwiched between conductors (via hole lands or mounting pads (hereinafter referred to as pads) 6 1) 58 A narrow portion 58b is provided. That is, the insulation distance from both conductors (via hole land or pad 61) is maintained by reducing the width toward the center of wiring pattern 58.
- FIG. 15 (C) when three wiring patterns are sandwiched between the conductors (via hole land or pad) 61, the width of the center wiring pattern 58 is reduced toward the center, The wiring patterns 58 on both sides are formed to be narrow on the opposite side to the conductor portion (via hole land or pad) 61, respectively. In other words, the width of the center wiring pattern is reduced toward the center, and the width of the wiring patterns on both sides is reduced toward the opposite side of the conductor, so that the insulation distance from both conductors and the insulation distance between the wiring patterns are reduced. It is kept.
- FIG. 15 (D) as in FIG. 15 (C), three wiring patterns 58 are provided with a narrow portion 58a and a conductor portion (via hole land or pad 61) is formed.
- the wiring pattern side is notched. That is, the insulation distance between the wiring pattern and the via hole land or pad 61 is maintained by cutting out the wiring pattern side of the via land or pad 61.
- the example shown in FIG. 15 (D) is used only when it is not possible to maintain the insulation distance of 40 m by simply reducing the width of the wiring pattern as shown in FIG. 15 (C). That is, the diameter of the via hole land or pad 61 is larger than the diameter by 50 when the diameter of the lower end face of the upper via hole 160 shown in FIG. 13 is 140 m. Formed at 190.
- the upper via hole 160 has a positional error of about 25 m with respect to the via hole land or pad 61, so even if the via hole 160 is deviated most, the via hole land or pad 61 is still in position. To be able to form on pad 6 1 12
- the manufacturing method of the multilayer build-up wiring board according to the second embodiment described above with reference to FIG. 13 is the same as that of the first embodiment described above with reference to FIGS. I do.
- FIGS. 4 (N) and 4 (0) when forming the wiring pattern 58, FIGS. 14 (A) to 15 (D),
- the wiring pattern 58 is formed by a portion (narrow width) sandwiched between conductors such as via hole land 61. Part) Only the width of 5 8a is narrowed. That is, the portion (normal width portion) 58a not sandwiched between the via hole lands 61 is not reduced in width, so that the possibility of disconnection in the above-described process is reduced, and the yield is increased.
- the example in which the wiring pattern is formed by electroless plating is given.
- the shape of the wiring pattern of the second embodiment described above is also changed. Can be applied.
- an example in which a part of the wiring pattern sandwiched between the via-hole lands or the pads 61 is made thinner has been described.
- a printed wiring board and a method of manufacturing the same according to a third embodiment of the present invention will be described with reference to the drawings.
- Fig. 17 shows a multilayer printed wiring board.
- the figure shows a state in which the IC chip 90 is placed on 10 and attached to the door board 94. ing.
- a through hole 36 is formed in a core substrate 30, and conductor circuits 34 are formed on both surfaces of the core substrate 30.
- a lower interlayer resin insulation layer 50 is provided on the core substrate 30, and the lower interlayer resin insulation layer 50 has via holes 60, wiring patterns 58 S and lands 58 R. , And a conductor layer composed of the dummy conductor 58D is formed.
- an upper interlayer resin insulation layer 150 is disposed, and in the interlayer resin insulation layer 150, a via hole 160, a signal line 158S, and a dummy conductor are provided.
- a conductor layer made of 158D is formed.
- FIG. 18 shows a cross-sectional view taken along the line XX of FIG. 17, that is, a plan view of the conductor layer formed on the surface of the lower interlayer resin insulating layer 50.
- the E-E cross section in FIG. 18 corresponds to FIG. As shown in FIG.
- a wiring pattern 58S, a land 58m, an isolated land 58RS, a dummy conductor 58D, and a dummy conductor 5 8 DS is formed.
- a dummy conductor 58D is provided around an isolated wiring pattern 58S.
- the part surrounded by B in FIG. 18 is enlarged and shown in FIG. 19 (B).
- dummy conductors 58D are provided around three wiring patterns 58S.
- the dummy conductor 58D is disposed around the wiring pattern 58S, when the conductor layer is formed by electrolytic plating as described later, the electric field is concentrated. Does not occur, and the light etching CT / J
- the wiring pattern 58S can be formed to a predetermined thickness (15 wm) and width (37 im) without over-etching. Further, since it is possible to form the isolated signal lines and the densely arranged signal lines with a uniform thickness, the thickness of the interlayer resin insulating layer 150 above the signal lines can be made uniform, and The electrical characteristics of the wiring board can be improved.
- the width of the dummy conductor 58D is 1-3 times (37-llzm) the minimum width (37m) of the wiring pattern 58S. With such a width, the electric field is not concentrated on the wiring pattern 58S and the dummy conductor 58D, and the signal line and the dummy conductor can be formed to have a predetermined thickness.
- the minimum distance D1 between the dummy conductor 58D and the wiring pattern 58S is set to be 1 to 3 times (37 to 11 m) the signal line 38. Therefore, concentration of the electric field does not occur, and the wiring pattern and the dummy conductor can be formed to a predetermined thickness.
- Fig. 20 (C) is an enlarged view of the part surrounded by C in Fig. 18.
- the isolated land 58 RS is surrounded by a dummy conductor 58 DS.
- the dummy conductor 58DS is provided so as to surround the isolated land 58RS, so that when the conductor layer is formed by electrolytic plating as described later, the electric field is reduced. Concentration does not occur, and the isolated land 58 RS can be formed to a predetermined thickness (15 im) and a predetermined diameter (133 m) without causing over-etching in light etching described later.
- the isolated land 58 DS and the dense land 58 D with a uniform thickness, and furthermore, the thickness of the interlayer resin insulating layer 150 on the wiring pattern.
- the electrical characteristics of the printed wiring board can be improved because the electrical characteristics can be made uniform.
- the minimum width of the dummy conductor 58 DS around the isolated land 58 RS is 1 Z6 to 3 times (22 to 3999 / m) of the land monster (133 m).
- the land and the dummy conductor can be formed to have a predetermined thickness without causing the concentration of the electric field.
- the minimum distance D2 between the dummy conductor 58 DS and the isolated land and 58 RS is set to 1 Z6 to 3 times the land diameter (22 to 399 iim). Therefore, the land and the dummy conductor can be formed to a predetermined thickness.
- the isolated land 58 RS is surrounded by the dummy conductor 58 DS, the isolated land 58 RS is less affected by external noise and the like.
- FIG. 20 (C ′) shows an isolated land different from the isolated land shown in FIG. 20 (C).
- the dummy conductor 58 DS is connected to the via hole 60 and to the ground line on the core substrate 30 side (see FIG. 17).
- the dummy conductor 58DS is connected to the ground, it is possible to prevent the isolated land 58RS from being affected by external noise and the like.
- FIG. 21 is an enlarged view of the portion surrounded by D in FIG.
- the fillet F2 is formed at the right angle portion and the fillet F1 is formed at the acute angle portion at the intersection of the dummy conductor 58D and the dummy conductor 58D. is there. Therefore, the dummy conductors can be properly connected to each other.
- the right angle and the acute angle are eliminated, and no crack is generated due to the stress concentration caused by the corner. That is, if there is a corner in a part of the conductor layer, thermal stress is concentrated in a heat cycle, and a crack may be generated in the interlayer resin insulating layer starting from the corner, which is a force of the third embodiment. In a printed wiring board, the occurrence of such cracks can be prevented.
- FIG. 22 (E) shows a case where the wiring pattern 58S and the isolated land 58RS are close to each other. In such a case, both the wiring pattern 58S and the isolated land 58RS can be surrounded by the dummy conductor 58D.
- FIG. 22 (F) shows a case where a plane layer 58H for a power supply layer exists near the wiring pattern 58S. In such a case, it is not particularly necessary to arrange a dummy conductor between the wiring pattern 58S and the plane layer 58H.
- the method for manufacturing a printed wiring board according to the third embodiment described above is the same as that in the first embodiment, and thus description thereof is omitted.
- an electrolytic copper plating film 56 is formed on the electroless copper plating film 52 in the same manner as in the first embodiment described above with reference to FIG.
- a conductor layer and a via hole 60 are formed.
- the conductor layer as described above with reference to FIG. 18, the wiring pattern 58 S, the land 58 length, the isolated land 58 RS, the dummy conductor 58 D, and the dummy conductor 58 DS Is formed.
- the dummy conductors 58D and 58DS are arranged around the isolated wiring pattern 58S and the isolated land 58RS.
- no electric field concentration occurs, and the wiring pattern 58S, the land 58R, and the isolated land 58RS can be formed with a uniform thickness.
- the etching liquid circulation becomes uniform, and the wiring pattern 58S can be formed with a uniform thickness ( ⁇ ⁇ ⁇ ) and width (37zm).
- FIG. 30 shows a cross section of a printed wiring board according to the fourth embodiment of the present invention.
- Build-up wiring layers 90 A and 90 B are formed on the front and back surfaces of the multilayer core substrate 30.
- the built-up layers 90 A and 90 B are formed of an interlayer resin insulation layer 50 on which the via hole 60 and the conductor circuit 58 are formed, and an interlayer resin insulation layer on which the via hole 160 and the conductor circuit 158 are formed. It consists of layer 150.
- solder bump 76 U for connecting to a bump (not shown) of the IC chip is formed, and on the back side, a solder bump for connecting to a bump (not shown) of the motherboard is formed. Solder bumps 76D are formed. In the printed wiring board, the conductor circuit from the solder bump 76 U connected to the IC chip is connected to the solder bump 76 D connected to the motherboard side. Front side built-up layer 9 0 A and the built-up layer 90 B on the back side are connected via a through hole 36 formed on the core substrate 30.
- a land 36a is formed in the opening of the through hole 36, an upper via hole 60 is connected to the land 36a, and a conductor circuit 58 connected to the via hole 60 is connected to the land 36a.
- the upper via hole 160 is connected, and solder bumps 76 U and 76 D are formed on the conductor circuit 158 connected to the via hole 160.
- FIG. 31 shows a BB cross section of the core substrate 30 of the printed wiring board in FIG.
- the land 36a formed in the opening of the through hole 36 is formed in a circular shape, and the via hole 60 is directly connected to the land 36a as described above with reference to FIG. Have been.
- This connection eliminates dead space by allowing the area immediately above the land 36a to function as a conventional inner layer pad, and furthermore, an inner layer pad for connecting the land 36a to the via hole 60. Since no 226 b is added, the shape of the land 36 a of the through hole 36 can be circular. As a result, the number of through holes can be increased by increasing the arrangement density of the through holes 36 provided in the multilayer core substrate 30.
- the wiring from the plurality of bumps on the back side is connected to the bumps on the front side while being integrated, but by forming through holes at the required density, the front and back sides are formed.
- the formed build-up wiring layers 90 A and 9 OB wiring can be integrated at the same pace.
- the number of build-up wiring layers 90 A and 90 B formed on the front side and the back side can be reduced.
- the radius of the land 36a, the diameter TW of the through hole 16, the error range of the land 36a for the through hole 16 with respect to the land 36a, and the opening (via hole) By setting the diameter BW of 60 and the error range 2 ⁇ of the aperture 60 to be equal to or more than the combined value, a via hole 60 is formed on the land 36a. It is. On the other hand, by setting the diameter RW of the land 36a to 700 or less, the arrangement density of through-holes is increased as compared with a configuration in which a land for arranging via holes is added to the land of the conventional technology.
- the radius of the through hole 16 for the through hole is not more than 175 m and not less than 125 m. If it exceeds 175 / xm, the number of through-holes provided on the core substrate will decrease, and if it is less than 125 ⁇ m, it will be difficult to form by drilling.
- the radius of the land 36a is larger than the radius of the through hole 16 for the through hole by 75 ⁇ 111 to 1775. This is the minimum technically possible value for via hole 60 diameter 25 m, via hole opening error for land 36 a ⁇ 12.5 (total 25) im, through hole 16 The error of land 36a is 25 m, and the sum of these is 75 m.
- the minimum value that can be mass-produced economically is 35 m in diameter of via hole 60, ⁇ 20 (total 40) m of opening 60 for via hole, and 100 ⁇ of error of land 36a with respect to through hole 16. Is 1 75 m. That is, by forming a land 75 / xm to 175zm larger than the radius of the through hole, it is possible to technically and economically arrange a via hole on the land.
- composition of the adhesive for electroless plating, B. interlayer resin insulation, and C. the composition of the resin filler used in the method of manufacturing the printed wiring board of the fourth embodiment are the same as those of the first embodiment. Is omitted.
- a copper-clad laminate 3 OA in which 18 m of copper foil 32 is laminated on both sides of a substrate 30 is used as a starting material.
- the copper-clad laminate 3OA is drilled to form a through hole 16 having a diameter (TW) of 300 m (FIG. 23 (B)).
- the diameter of the through hole 16 for through hole is desirably 350 / xm or less and 250 m or more. Over 3 50 / m to core substrate This is because the number of through-holes is reduced, and if it is less than 250 m, it is difficult to form by drilling.
- the entire substrate is subjected to an electroless plating process, and an electroless plated copper film 18 is deposited on the inner wall of the through hole 16 to form a through hole 36 (FIG. 23 (C)).
- the land 36a of the through hole, the conductor circuit 34, and the alignment mark 33 are formed by etching in a pattern (FIG. 23 (B)).
- the land 36a is formed to have a diameter (RW) 600.
- a resin filler is obtained by mixing and kneading the above-described raw material composition for preparing the resin filler of C.
- the substrate 30 that has been subjected to the process (4) is polished by a belt sander so that no resin filler remains on the land 36 a of the through hole 36 and the surface of the conductive circuit 34.
- a heat treatment was performed to cure the resin filler 40.
- the roughened layer on the upper surface was removed, and both surfaces of the substrate 30 were smoothed as shown in FIG. 24 (G).
- a roughened layer (uneven layer) 42 was formed on the through-hole lands 36a and the upper surface of the conductor circuit 34 exposed in the process (5).
- the raw material composition for preparing the adhesive for electroless plating of the composition A was mixed by stirring, and the viscosity was adjusted to 7 Pa * s to obtain an adhesive solution for electroless plating (for upper layer).
- Fig. 25 (I) On both sides of the substrate 30 (Fig. 24 (H)) in (6) above, Fig. 25 (I) As shown in (4), an interlayer resin insulating material (for lower layer) 44 having a viscosity of 1.5 Pa-s obtained in the above (7) is applied and dried. Next, the photosensitive adhesive solution (for upper layer) 46 having a viscosity of 7 Pa * s obtained in the above (7) is applied and dried, and the adhesive layer 50 having a thickness of 35 / Xm is formed. Form.
- a photomask film (not shown) is brought into close contact with both surfaces of the substrate 30 on which the adhesive layer 50 has been formed in (8), and is exposed. This is spray-developed, the substrate is exposed, and heated (post-baked),
- An insulating layer (two-layer structure) 50 is formed.
- the alignment of the photomask film when forming the openings 48 is performed with reference to the alignment marks 33 shown in FIG. Since the through hole 16 for the through hole described above is formed mechanically by a drill, it is difficult to improve the positional accuracy. Therefore, the land 36a formed in the through hole is formed with a positional accuracy of 90 ⁇ ( ⁇ 45 ⁇ m) with respect to the through hole.
- the land 36a formed in the through hole is formed with a positional accuracy of 90 ⁇ ( ⁇ 45 ⁇ m) with respect to the through hole.
- the positional accuracy of the opening 48 with respect to the land 36a should be set at least twice. Is set to ⁇ 15.
- the positioning marks 33 shown in FIG. 31 are provided at the same time as the lands 36 a as long as the above-mentioned required accuracy is obtained for the core substrate 30 for multi-segmenting.
- Positioning of the photomask film is adjusted based on 3 to improve the positioning accuracy. For example, when a land is formed, the position of the four corners of one multi-panel board (for example, 36 boards) is aligned with the alignment reference (positioning mark) at the four corners. When forming 8, the required accuracy is obtained by aligning with the alignment reference (positioning mark) arranged at the four corners of several substrates to be divided (for example, for 8 substrates). To achieve.
- the radius of the land 36a is 1 4 more than the radius of the through hole 16 for the through hole.
- the opening 48 can be formed on the land 36a by forming it larger than 0 im. This means that the minimum technically possible values are the diameter 25 of the via hole 60, the error of the opening for the via hole with respect to the land ⁇ 12.5 (total 25) um, the error of the land 36 a with the through hole 16 of 25 ⁇ xm, This is because the sum of them is 75 m.
- the land 36a to be approximately 175 large, a multilayer printed wiring board can be formed with a high yield.
- the minimum value that can be mass-produced economically is the diameter of the via hole 60 of 35; m, the error of the via hole opening 60 ⁇ 20 (total 40) rn, and the error of the land 36a with respect to the through hole 16 of 100; Because the sum of them is 1 75.
- the printed wiring board of the fourth embodiment by forming a land 140 xm to 175 m larger than the radius of the through hole, it is technically and economically possible to arrange via holes on the land. Become.
- the opening 48 is formed by etching, but the opening can be formed similarly by using laser light.
- the substrate 30 with the openings 48 formed is immersed in chromic acid, and the surface of the interlayer resin insulation layer 50 is made a roughened surface 51 as shown in FIG. 25 (K), and then immersed in a neutral solution. And then wash with water.
- catalyst nuclei are attached to the surface of the interlayer resin insulating layer 50 and the inner wall surface of the via hole opening 48.
- Electrolytic copper plating is performed to form a 15-thick electrolytic plated copper film 56 (FIG. 27 (N);).
- the substrate 30 on which the conductor circuit 58 is formed is immersed in an electroless plating solution, and as shown in FIG. 28 (P), a 3 m-thick copper-nickel A roughened layer 62 made of phosphorus is formed.
- the surfaces of the conductor circuit 58 and the via hole 60 can be roughened by an etchant or an oxidation-reduction treatment.
- a commercially available solder resist composition is applied to both sides of the wiring board obtained in (16) in a thickness of 20 ill. Next, after performing a drying treatment, an exposure and development treatment was performed. Further, a heat treatment is performed to form a solder resist layer (thickness: 20 tm) 70 in which the pad portion 71 is opened (opening diameter 200 wm) (see FIG. 29 (R)).
- a solder-resist layer is applied with a resin composition for reinforcement around the opening group of the solder resist to form a reinforcement layer 78 having a thickness of 40 m.
- the substrate 30 on which the solder resist layer 70 was formed was immersed in an electroless nickel plating solution to form a nickel plating layer 72 having a thickness of 5 m in the opening 71. Further, the substrate 30 is immersed in an electroless plating solution to form a plating layer 74 having a thickness of 0.03 m on the nickel plating layer 72 (FIG. 29 (S)). (20) Then, solder paste is printed on the opening 71 of the solder resist layer 70 and reflowed with 200 to form solder bumps 76U and 76D, thereby manufacturing a printed wiring board having solder bumps ( (Fig. 30).
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
Claims
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/700,592 US6407345B1 (en) | 1998-05-19 | 1999-05-13 | Printed circuit board and method of production thereof |
EP99919584A EP1083779B1 (en) | 1998-05-19 | 1999-05-13 | Printed circuit board and method of production thereof |
DE69934981T DE69934981T2 (de) | 1998-05-19 | 1999-05-13 | Gedruckte leiterplatte und verfahren zur herstellung |
US10/108,628 US7332816B2 (en) | 1998-05-19 | 2002-03-29 | Method of fabricating crossing wiring pattern on a printed circuit board |
US11/078,342 US7525190B2 (en) | 1998-05-19 | 2005-03-14 | Printed wiring board with wiring pattern having narrow width portion |
US12/389,456 US8018046B2 (en) | 1998-05-19 | 2009-02-20 | Printed wiring board with notched conductive traces |
US13/206,084 US8629550B2 (en) | 1998-05-19 | 2011-08-09 | Printed wiring board with crossing wiring pattern |
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10/155329 | 1998-05-19 | ||
JP15532998A JPH11330698A (ja) | 1998-05-19 | 1998-05-19 | 多層プリント配線板及び多層プリント配線板の製造方法 |
JP10/140695 | 1998-05-22 | ||
JP10140695A JPH11340591A (ja) | 1998-05-22 | 1998-05-22 | プリント配線板及びプリント配線板の製造方法 |
JP10140694A JPH11340590A (ja) | 1998-05-22 | 1998-05-22 | プリント配線板 |
JP10/140694 | 1998-05-22 | ||
JP9472599A JP4197070B2 (ja) | 1999-04-01 | 1999-04-01 | 多層ビルドアップ配線板 |
JP11/94725 | 1999-04-01 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09700592 A-371-Of-International | 1999-05-13 | ||
US10/108,628 Continuation US7332816B2 (en) | 1998-05-19 | 2002-03-29 | Method of fabricating crossing wiring pattern on a printed circuit board |
Publications (1)
Publication Number | Publication Date |
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WO1999060831A1 true WO1999060831A1 (en) | 1999-11-25 |
Family
ID=27468248
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1999/002512 WO1999060831A1 (en) | 1998-05-19 | 1999-05-13 | Printed circuit board and method of production thereof |
Country Status (7)
Country | Link |
---|---|
US (5) | US6407345B1 (ja) |
EP (2) | EP1083779B1 (ja) |
KR (2) | KR100791281B1 (ja) |
CN (1) | CN1245061C (ja) |
DE (1) | DE69934981T2 (ja) |
TW (2) | TWI287414B (ja) |
WO (1) | WO1999060831A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2018128037A1 (ja) * | 2017-01-05 | 2018-07-12 | 住友電工プリントサーキット株式会社 | プリント配線板の製造方法 |
Families Citing this family (59)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6407345B1 (en) * | 1998-05-19 | 2002-06-18 | Ibiden Co., Ltd. | Printed circuit board and method of production thereof |
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JPWO2018128037A1 (ja) * | 2017-01-05 | 2019-11-07 | 住友電工プリントサーキット株式会社 | プリント配線板の製造方法 |
US11641716B2 (en) | 2017-01-05 | 2023-05-02 | Sumitomo Electric Printed Circuits, Inc. | Method for manufacturing printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
KR20010043723A (ko) | 2001-05-25 |
TW200623976A (en) | 2006-07-01 |
US7332816B2 (en) | 2008-02-19 |
EP1083779A4 (en) | 2004-08-25 |
US20110290544A1 (en) | 2011-12-01 |
TWI287414B (en) | 2007-09-21 |
EP1083779B1 (en) | 2007-01-24 |
CN1301480A (zh) | 2001-06-27 |
EP1670300A2 (en) | 2006-06-14 |
US8629550B2 (en) | 2014-01-14 |
KR100791281B1 (ko) | 2008-01-04 |
US20050158553A1 (en) | 2005-07-21 |
TW200400782A (en) | 2004-01-01 |
DE69934981T2 (de) | 2007-11-15 |
US8018046B2 (en) | 2011-09-13 |
US6407345B1 (en) | 2002-06-18 |
EP1670300A3 (en) | 2008-12-03 |
DE69934981D1 (de) | 2007-03-15 |
KR20070073984A (ko) | 2007-07-10 |
US20020189849A1 (en) | 2002-12-19 |
US20090159327A1 (en) | 2009-06-25 |
CN1245061C (zh) | 2006-03-08 |
US7525190B2 (en) | 2009-04-28 |
EP1083779A1 (en) | 2001-03-14 |
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