JP4331769B2 - 配線構造及びその形成方法並びにプリント配線板 - Google Patents
配線構造及びその形成方法並びにプリント配線板 Download PDFInfo
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- JP4331769B2 JP4331769B2 JP2007050490A JP2007050490A JP4331769B2 JP 4331769 B2 JP4331769 B2 JP 4331769B2 JP 2007050490 A JP2007050490 A JP 2007050490A JP 2007050490 A JP2007050490 A JP 2007050490A JP 4331769 B2 JP4331769 B2 JP 4331769B2
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- wiring
- connection hole
- wiring layer
- layer
- recess
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2405—Shape
- H01L2224/24051—Conformal with the semiconductor or solid-state device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82035—Reshaping, e.g. forming vias by heating means
- H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01012—Magnesium [Mg]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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Description
Claims (7)
- 接続孔が形成された絶縁層と、
前記接続孔の底部に少なくとも一部が露出するように配置された被配線体と、
前記接続孔の内部で前記被配線体と接続されており、上面の少なくとも一部に凹部を有する配線層と、
を備えており、
前記配線層の延在方向に直交する方向の垂直断面において、前記凹部の上面が弧状又はV字状をなしており、該凹部の両縁端部が前記接続孔の内壁と接しておらず、且つ、該凹部の両縁端部から前記被配線体に向かって断面積が増大する部分を含んでおり、
前記配線層は、前記被配線体と接続する部位から前記接続孔の開口に向かって断面積が増大する部分を含むものである、
配線構造。 - 接続孔が形成された絶縁層と、
前記接続孔の底部に少なくとも一部が露出するように配置された被配線体と、
前記接続孔の内部で前記被配線体と接続されており、上面の少なくとも一部に凹部を有する配線層と、
を備えており、
前記配線層の延在方向に直交する方向の垂直断面において、前記凹部の両縁端部が尖塔状をなしており、該凹部の両縁端部が前記接続孔の内壁と接しておらず、且つ、該凹部の両縁端部から前記被配線体に向かって断面積が増大する部分を含んでおり、
前記配線層は、前記被配線体と接続する部位から前記接続孔の開口に向かって断面積が増大する部分を含むものである、
配線構造。 - 前記配線層は、前記接続孔の内壁の少なくとも一部と該配線層とが接していない空間領域が画成されるように設けられたものである、
請求項1又は2記載の配線構造。 - 前記配線層の上端部の幅が、前記接続孔の開口幅径よりも小さくされている、
請求項1又は2記載の配線構造。 - 前記配線層は、前記接続孔の底部に露出した前記被配線体の露出面の全体を覆うように設けられたものである、
請求項1又は2記載の配線構造。 - 接続孔が形成された絶縁層、前記接続孔の底部に少なくとも一部が露出するように配置された被配線体、及び、前記接続孔の内部で前記被配線体と接続されており、上面の少なくとも一部に凹部を有し、且つ、前記配線層の延在方向に直交する方向の垂直断面において、前記凹部の上面が弧状若しくはV字状をなしており又は前記凹部の両縁端部が尖塔状をなしており、該凹部の両縁端部が前記接続孔の内壁と接しておらず、該凹部の両縁端部から前記被配線体に向かって断面積が増大する部分を含む、配線構造が設けられており、
前記配線層は、前記被配線体と接続する部位から前記接続孔の開口に向かって断面積が増大する部分を含むものである、
プリント配線板。 - 被配線体上に絶縁層を形成する絶縁層形成工程と、
前記被配線体の少なくとも一部を露出させるように、前記絶縁層に少なくとも一つの接続孔を形成する接続孔形成工程と、
前記接続孔の内部で前記被配線体と、上面の少なくとも一部に凹部を有する配線層とを接続する配線層接続工程と、
を備えており、
前記配線層接続工程においては、前記配線層の延在方向に直交する方向の垂直断面において、前記凹部の上面が弧状若しくはV字状をなすように又は前記凹部の両縁端部が尖塔状をなすように、且つ、該凹部の両縁端部が前記接続孔の内壁と接しないように、且つ、該凹部の両縁端部から前記被配線体に向かって断面積が増大する部分を含むように、前記配線層を形成し、
前記配線層は、前記被配線体と接続する部位から前記接続孔の開口に向かって断面積が増大する部分を含むように形成される、
配線構造の形成方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007050490A JP4331769B2 (ja) | 2007-02-28 | 2007-02-28 | 配線構造及びその形成方法並びにプリント配線板 |
US12/007,830 US20080202803A1 (en) | 2007-02-28 | 2008-01-16 | Wiring structure, forming method of the same and printed wiring board |
EP08001425A EP1965421A3 (en) | 2007-02-28 | 2008-01-25 | Wiring structure, forming method of the same and printed wiring board |
KR1020080018602A KR101504348B1 (ko) | 2007-02-28 | 2008-02-28 | 배선 구조 및 그 형성 방법, 그리고 프린트 배선판 |
CN2008100828346A CN101257004B (zh) | 2007-02-28 | 2008-02-28 | 布线构造及其形成方法和印刷布线板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007050490A JP4331769B2 (ja) | 2007-02-28 | 2007-02-28 | 配線構造及びその形成方法並びにプリント配線板 |
Publications (2)
Publication Number | Publication Date |
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JP2008218522A JP2008218522A (ja) | 2008-09-18 |
JP4331769B2 true JP4331769B2 (ja) | 2009-09-16 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP2007050490A Active JP4331769B2 (ja) | 2007-02-28 | 2007-02-28 | 配線構造及びその形成方法並びにプリント配線板 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20080202803A1 (ja) |
EP (1) | EP1965421A3 (ja) |
JP (1) | JP4331769B2 (ja) |
KR (1) | KR101504348B1 (ja) |
CN (1) | CN101257004B (ja) |
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Publication number | Priority date | Publication date | Assignee | Title |
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KR100699874B1 (ko) * | 2005-11-08 | 2007-03-28 | 삼성전자주식회사 | 삽입형 연결부를 갖는 비. 지. 에이 패키지 그 제조방법 및이를 포함하는 보드 구조 |
US20090146295A1 (en) * | 2007-12-11 | 2009-06-11 | Hidefumi Narita | Ceramic substrate having thermal via |
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US20080202803A1 (en) | 2008-08-28 |
EP1965421A2 (en) | 2008-09-03 |
JP2008218522A (ja) | 2008-09-18 |
CN101257004A (zh) | 2008-09-03 |
CN101257004B (zh) | 2012-06-06 |
EP1965421A3 (en) | 2009-11-11 |
KR101504348B1 (ko) | 2015-03-19 |
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