JP5602584B2 - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
- Publication number
- JP5602584B2 JP5602584B2 JP2010241744A JP2010241744A JP5602584B2 JP 5602584 B2 JP5602584 B2 JP 5602584B2 JP 2010241744 A JP2010241744 A JP 2010241744A JP 2010241744 A JP2010241744 A JP 2010241744A JP 5602584 B2 JP5602584 B2 JP 5602584B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- via hole
- nickel
- insulating resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 165
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 107
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 93
- 229920005989 resin Polymers 0.000 claims description 86
- 239000011347 resin Substances 0.000 claims description 86
- 239000010949 copper Substances 0.000 claims description 55
- 238000005530 etching Methods 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 45
- 238000007747 plating Methods 0.000 claims description 44
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 20
- 229910052802 copper Inorganic materials 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 230000003746 surface roughness Effects 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 230000000704 physical effect Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 375
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 34
- 239000000758 substrate Substances 0.000 description 30
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 29
- 239000000654 additive Substances 0.000 description 13
- 238000004544 sputter deposition Methods 0.000 description 11
- 239000010408 film Substances 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 239000011241 protective layer Substances 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 238000007740 vapor deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910018054 Ni-Cu Inorganic materials 0.000 description 1
- 229910018481 Ni—Cu Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
図3〜図5は実施形態の配線基板の製造方法を示す断面図、図6は実施形態の配線基板を示す断面図である。
Claims (4)
- 銅から形成された第1配線層と、
前記第1配線層の上に形成された絶縁樹脂層と、
前記絶縁樹脂層に形成され、前記第1配線層に到達するビアホールと、
前記ビアホールを除く部分に配置されて前記ビアホールの外周から外側の前記絶縁樹脂層の上に形成されたニッケル・銅合金層と、前記ビアホールの内面から前記ニッケル・銅合金層の上に延在する銅から形成されたシード層と、前記シード層の上に前記ビアホールに充填された状態で形成された金属めっき層とを含む第2配線層とを有し、
前記ニッケル・銅合金層は前記絶縁樹脂層の上に所定のパターンで形成されており、
前記ビアホールの底部の前記第1配線層に凹部が形成されており、
前記ニッケル・銅合金層のニッケル含有率は20〜50%に設定され、前記ニッケル・銅合金層は前記銅から形成された第1配線層よりもウェットエッチングでのエッチングレートが遅い物性を有し、
前記ニッケル・銅合金層の厚みは、前記第1配線層の凹部の深さより薄いことを特徴とする配線基板。 - 前記絶縁樹脂層の表面粗さ(Ra)は、10乃至200nmの範囲に設定されることを特徴とする請求項1に記載の配線基板。
- 銅から形成された第1配線層の上に、絶縁樹脂層を介してニッケル・銅合金層が形成された積層体を形成する工程と、
レーザによって前記ニッケル・銅合金層及び前記絶縁樹脂層を加工することにより、前記第1配線層に到達するビアホールを形成する工程と、
前記ビアホール内をデスミア処理する工程と、
前記ビアホール内の前記第1配線層の表面をエッチングして、前記第1配線層に凹部を形成すると共に、前記ニッケル・銅合金層を同時にエッチングして薄化する工程と、
前記ニッケル・銅合金層の上及び前記ビアホールの内面に銅からなるシード層を形成する工程と、
前記ビアホールを含む部分に開口部が設けられためっきレジストを形成する工程と、
前記シード層をめっき給電経路に利用する電解めっきにより、前記ビアホール及び前記めっきレジストの開口部に金属めっき層を形成する工程と、
前記めっきレジストを除去する工程と、
前記金属めっき層をマスクにして前記シード層及び前記ニッケル・銅合金層をエッチングすることにより、前記ビアホールを介して前記第1配線層に接続される第2配線層を前記絶縁樹脂層の上に形成する工程とを有し、
前記積層体を形成する工程において、前記ニッケル・銅合金層のニッケル含有率は20〜50%に設定され、前記ニッケル・銅合金層は前記銅から形成された第1配線層よりもウェットエッチングでのエッチングレートが遅い物性を有し、前記ニッケル・銅合金層の厚みは前記第1配線層の凹部の深さより薄く設定され、かつ、
前記第1配線層の表面をエッチングする工程で前記ニッケル・銅合金層が残されることを特徴とする配線基板の製造方法。 - 前記第2配線層を形成する工程において、前記シード層と前記ニッケル・銅合金層とを同一のエッチャントで一括してエッチングすることを特徴とする請求項3に記載の配線基板の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010241744A JP5602584B2 (ja) | 2010-10-28 | 2010-10-28 | 配線基板及びその製造方法 |
US13/279,501 US8878077B2 (en) | 2010-10-28 | 2011-10-24 | Wiring substrate and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010241744A JP5602584B2 (ja) | 2010-10-28 | 2010-10-28 | 配線基板及びその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2012094734A JP2012094734A (ja) | 2012-05-17 |
JP2012094734A5 JP2012094734A5 (ja) | 2013-08-15 |
JP5602584B2 true JP5602584B2 (ja) | 2014-10-08 |
Family
ID=45995399
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010241744A Active JP5602584B2 (ja) | 2010-10-28 | 2010-10-28 | 配線基板及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8878077B2 (ja) |
JP (1) | JP5602584B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10849226B2 (en) | 2018-12-04 | 2020-11-24 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board and method of manufacturing the same |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130118794A1 (en) * | 2011-11-15 | 2013-05-16 | Bo-Yu Tseng | Package Substrate Structure |
US20130168132A1 (en) * | 2011-12-29 | 2013-07-04 | Sumsung Electro-Mechanics Co., Ltd. | Printed circuit board and method of manufacturing the same |
CN103794544B (zh) * | 2012-10-26 | 2016-04-13 | 中国科学院上海微系统与信息技术研究所 | 一种电镀铜的方法 |
US10028394B2 (en) * | 2012-12-17 | 2018-07-17 | Intel Corporation | Electrical interconnect formed through buildup process |
KR20140085023A (ko) * | 2012-12-27 | 2014-07-07 | 삼성전기주식회사 | 인쇄 회로 기판 및 그 제조 방법 |
US9545003B2 (en) * | 2012-12-28 | 2017-01-10 | Fci Americas Technology Llc | Connector footprints in printed circuit board (PCB) |
KR101506785B1 (ko) * | 2013-05-29 | 2015-03-27 | 삼성전기주식회사 | 인쇄회로기판 |
JP6266907B2 (ja) * | 2013-07-03 | 2018-01-24 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
CN105140198B (zh) * | 2014-05-29 | 2017-11-28 | 日月光半导体制造股份有限公司 | 半导体衬底、半导体封装结构及其制造方法 |
JP6324876B2 (ja) * | 2014-07-16 | 2018-05-16 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
CN105657988B (zh) * | 2014-11-21 | 2019-04-23 | 宏启胜精密电子(秦皇岛)有限公司 | 柔性电路板及其制作方法 |
JP2016213283A (ja) * | 2015-05-01 | 2016-12-15 | ソニー株式会社 | 製造方法、および貫通電極付配線基板 |
EP3386282A4 (en) * | 2015-11-30 | 2019-07-17 | Toppan Printing Co., Ltd. | MULTILAYER FITTED PCB AND METHOD FOR THE MANUFACTURE THEREOF |
US10440836B2 (en) * | 2016-04-26 | 2019-10-08 | Kinsus Interconnect Technology Corp. | Double layer circuit board |
US20190174632A1 (en) * | 2017-12-05 | 2019-06-06 | Canon Components, Inc. | Flexible printed circuit and electronic device |
KR102680005B1 (ko) * | 2018-11-27 | 2024-07-02 | 삼성전기주식회사 | 인쇄회로기판 |
KR20200087479A (ko) * | 2019-01-11 | 2020-07-21 | 스템코 주식회사 | 다층 기판 및 그 제조 방법 |
EP3979774A4 (en) | 2019-05-31 | 2022-07-27 | Toppan Inc. | MULTILAYER CIRCUIT BOARD AND METHOD FOR MAKING IT |
KR20220015193A (ko) * | 2020-07-30 | 2022-02-08 | 삼성전자주식회사 | 반도체 패키지 |
US12027467B2 (en) * | 2021-01-29 | 2024-07-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4969979A (en) * | 1989-05-08 | 1990-11-13 | International Business Machines Corporation | Direct electroplating of through holes |
JP3395621B2 (ja) * | 1997-02-03 | 2003-04-14 | イビデン株式会社 | プリント配線板及びその製造方法 |
JPH1187931A (ja) | 1997-09-11 | 1999-03-30 | Ngk Spark Plug Co Ltd | プリント配線板の製造方法 |
CN1294788C (zh) * | 1997-12-11 | 2007-01-10 | 伊比登株式会社 | 多层印刷电路板的制造方法 |
JP2000022337A (ja) * | 1998-06-30 | 2000-01-21 | Matsushita Electric Works Ltd | 多層配線板及びその製造方法 |
KR20070086862A (ko) * | 1998-09-03 | 2007-08-27 | 이비덴 가부시키가이샤 | 다층프린트배선판 및 그 제조방법 |
MY128333A (en) * | 1998-09-14 | 2007-01-31 | Ibiden Co Ltd | Printed wiring board and its manufacturing method |
JP4905749B2 (ja) | 2001-03-02 | 2012-03-28 | 日立化成工業株式会社 | 配線板とその製造方法とその配線板を用いた半導体搭載用基板とその製造方法と半導体パッケージ並びにその製造方法 |
US7140103B2 (en) * | 2001-06-29 | 2006-11-28 | Mitsubishi Gas Chemical Company, Inc. | Process for the production of high-density printed wiring board |
JP4160765B2 (ja) * | 2002-03-25 | 2008-10-08 | 京セラ株式会社 | 配線基板の製造方法 |
JP4094965B2 (ja) * | 2003-01-28 | 2008-06-04 | 富士通株式会社 | 配線基板におけるビア形成方法 |
TWI262041B (en) * | 2003-11-14 | 2006-09-11 | Hitachi Chemical Co Ltd | Formation method of metal layer on resin layer, printed wiring board, and production method thereof |
JPWO2008053833A1 (ja) * | 2006-11-03 | 2010-02-25 | イビデン株式会社 | 多層プリント配線板 |
JP4303282B2 (ja) * | 2006-12-22 | 2009-07-29 | Tdk株式会社 | プリント配線板の配線構造及びその形成方法 |
JP4331769B2 (ja) * | 2007-02-28 | 2009-09-16 | Tdk株式会社 | 配線構造及びその形成方法並びにプリント配線板 |
KR100905566B1 (ko) * | 2007-04-30 | 2009-07-02 | 삼성전기주식회사 | 회로 전사용 캐리어 부재, 이를 이용한 코어리스인쇄회로기판, 및 이들의 제조방법 |
JP2009188324A (ja) * | 2008-02-08 | 2009-08-20 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法 |
CN102265712B (zh) * | 2008-12-26 | 2014-10-29 | 吉坤日矿日石金属株式会社 | 电子电路的形成方法 |
US20100270646A1 (en) * | 2009-04-28 | 2010-10-28 | Georgia Tech Research Corporation | Thin-film capacitor structures embedded in semiconductor packages and methods of making |
TWI393516B (zh) * | 2009-06-01 | 2013-04-11 | Unimicron Technology Crop | 印刷電路板的製造方法 |
WO2010150310A1 (ja) * | 2009-06-24 | 2010-12-29 | 富士通株式会社 | 配線基板の製造方法 |
JP5428667B2 (ja) * | 2009-09-07 | 2014-02-26 | 日立化成株式会社 | 半導体チップ搭載用基板の製造方法 |
JP5436995B2 (ja) * | 2009-09-14 | 2014-03-05 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
US20110114372A1 (en) * | 2009-10-30 | 2011-05-19 | Ibiden Co., Ltd. | Printed wiring board |
US8334202B2 (en) * | 2009-11-03 | 2012-12-18 | Infineon Technologies Ag | Device fabricated using an electroplating process |
JP4546581B2 (ja) * | 2010-05-12 | 2010-09-15 | 新光電気工業株式会社 | 配線基板の製造方法 |
US20120247818A1 (en) * | 2011-03-29 | 2012-10-04 | Ibiden Co., Ltd. | Printed wiring board |
JP2012216773A (ja) * | 2011-03-29 | 2012-11-08 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法 |
JP5833398B2 (ja) * | 2011-06-27 | 2015-12-16 | 新光電気工業株式会社 | 配線基板及びその製造方法、半導体装置 |
US20130118794A1 (en) * | 2011-11-15 | 2013-05-16 | Bo-Yu Tseng | Package Substrate Structure |
KR102069158B1 (ko) * | 2012-05-10 | 2020-01-22 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 배선의 형성 방법, 반도체 장치, 및 반도체 장치의 제작 방법 |
-
2010
- 2010-10-28 JP JP2010241744A patent/JP5602584B2/ja active Active
-
2011
- 2011-10-24 US US13/279,501 patent/US8878077B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10849226B2 (en) | 2018-12-04 | 2020-11-24 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
US20120103667A1 (en) | 2012-05-03 |
US8878077B2 (en) | 2014-11-04 |
JP2012094734A (ja) | 2012-05-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5602584B2 (ja) | 配線基板及びその製造方法 | |
US10366949B2 (en) | Wiring substrate and semiconductor device | |
US8298945B2 (en) | Method of manufacturing substrates having asymmetric buildup layers | |
US9247644B2 (en) | Wiring board and method for manufacturing the same | |
US9119319B2 (en) | Wiring board, semiconductor device, and method for manufacturing wiring board | |
US20120155048A1 (en) | Wiring board, semiconductor apparatus and method of manufacturing them | |
US20130069251A1 (en) | Wiring substrate, method of manufacturing the same, and semiconductor device | |
JP5363384B2 (ja) | 配線基板及びその製造方法 | |
JP6840935B2 (ja) | 配線回路基板の製造方法 | |
JP2010157718A (ja) | プリント配線板及びプリント配線板の製造方法 | |
US9232644B2 (en) | Wiring substrate | |
JP2012216773A (ja) | 配線基板及びその製造方法 | |
JP5113544B2 (ja) | 配線基板の製造方法 | |
US9137896B2 (en) | Wiring substrate | |
JP2006019591A (ja) | 配線基板の製造方法および配線基板 | |
US20140087556A1 (en) | Method of manufacturing wiring substrate | |
JP2017005081A (ja) | インターポーザ、半導体装置、およびそれらの製造方法 | |
JP2008288607A (ja) | 電子部品実装構造の製造方法 | |
JP5432800B2 (ja) | 配線基板の製造方法 | |
KR100908986B1 (ko) | 코어리스 패키지 기판 및 제조 방법 | |
JP5363377B2 (ja) | 配線基板及びその製造方法 | |
JP2009076928A (ja) | 配線基板の製造方法 | |
JP2013080823A (ja) | プリント配線板及びその製造方法 | |
JP5419583B2 (ja) | 配線基板の製造方法 | |
JP6676370B2 (ja) | 配線基板及び配線基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130625 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20130625 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140131 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140212 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140324 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140812 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140820 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5602584 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |