TWI509798B - 用於形成具多通道之屏蔽閘極溝槽場效電晶體（ｆｅｔ）的結構及方法 - Google Patents

用於形成具多通道之屏蔽閘極溝槽場效電晶體（ｆｅｔ）的結構及方法 Download PDF

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TWI509798B
TWI509798B TW097149388A TW97149388A TWI509798B TW I509798 B TWI509798 B TW I509798B TW 097149388 A TW097149388 A TW 097149388A TW 97149388 A TW97149388 A TW 97149388A TW I509798 B TWI509798 B TW I509798B
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Description

用於形成具多通道之屏蔽閘極溝槽場效電晶體(FET)的結構及方法
本發明係有關於用於形成具多通道之屏蔽閘極溝槽場效電晶體(FET)的結構及方法。
 發明背景
本發明概括有關半導體技術，且更特別有關用於形成沿著各溝槽側壁具有多通道之屏蔽閘極溝槽FET的結構及方法。
屏蔽閘極溝槽場效電晶體(FET)優於習知FET之處係在於：屏蔽電極降低閘極-汲極電容(Cgd)並改良電晶體的崩潰電壓而不犧牲電晶體接通電阻。第1圖為一習知屏蔽閘極溝槽MOSFET 100的簡化橫剖視圖。N-型磊晶層102延伸於經高度摻雜n-型基材101上方。基材101作為汲極接觸區。經高度摻雜n-型源極區108及經高度摻雜p-型重體部區106係形成於p-型井區104中，p-型井區104則形成於磊晶層102中。溝槽110係延伸經過井區104並終止於常稱為漂移區之被井區104及基材101所劃界之磊晶層102的部分中。
溝槽110包括閘極電極122下方之屏蔽電極114。閘極電極122藉由閘極介電質120與井區104絕緣。屏蔽電極114藉由屏蔽介電質115與漂移區絕緣。閘極及屏蔽電極122、114係藉由間電極介電(IED)層116彼此絕緣。IED層116必須具有充分品質與厚度以支持操作期間可能存在於屏蔽電極114與閘極電極122之間的電位差。介電蓋124鋪設於閘極電極122並用來絕緣閘極電極122與頂側互連層126。頂側互連層126延伸於結構上方並與重體部區106及源極區108產生電性接觸。
雖然在閘極電極122底下包括屏蔽電極114的方式已經改良電晶體的特定效能特徵(諸如崩潰電壓及Cgd)，已難以達成這些及其他電性與結構性特徵(諸如電晶體接通電阻Rdson及未鉗制電感切換UIS特徵)的進一步改良。這是因為大部份用於改良FET的特定電性特徵之已知技術時常不利地衝擊其他電性特徵或製程技術需作顯著改變所致。
因此，需要可改良一溝槽閘極FET的不同電性特徵而不減損其他電性特徵之合乎成本效益的技術。
 發明概要
一場效電晶體(FET)係包括延伸至一半導體區中之一對溝槽。各溝槽係包括一位於溝槽的一下部中之第一屏蔽電極以及一位於屏蔽電極上方但與其絕緣之溝槽的一上部中之閘極電極。一第一傳導類型的第一及第二井區係在該對溝槽之間側向地延伸於半導體區中並抵靠該對溝槽的側壁。第一及第二井區藉由一第二傳導類型的一第一漂移區彼此垂直地分隔。閘極電極及第一屏蔽電極係相對於第一及第二井區被定位以當FET在接通狀態中被偏壓時使一通道形成於第一及第二井區的各者中。
一實施例中，當FET在接通狀態中被偏壓時，沿著其中可供第一及第二井區抵靠之各溝槽側壁的部分形成兩個分離的通道。
另一實施例中，第一井區在各溝槽中側向地直接位於閘極電極旁邊，而第二井區在各溝槽中側向地直接位於第一屏蔽電極旁邊。
另一實施例中，第一井區位於第二井區上方。FET進一步包括在該對溝槽之間側向地延伸於半導體區中之第一傳導類型的一第三井區。第三井區抵靠該對溝槽的側壁，並藉由第二傳導類型的一第二漂移區對於第二井區呈垂直地分隔。
又另一實施例中，第一井區位於第二井區上方。FET進一步包括在該對溝槽之間側向地延伸於半導體區中之第一傳導類型的一第三井區。第三井區抵靠該對溝槽的側壁並藉由第二傳導類型的一第二漂移區對於第二井區呈垂直地分隔。一第二屏蔽電極係在第一屏蔽電極下方配置於溝槽中。第一及第二屏蔽電極彼此絕緣。
根據本發明的另一實施例，一用於形成一FET之方法係包括下列步驟。形成延伸至一第一傳導類型的一半導體區中之一對溝槽。一屏蔽電極形成於各溝槽的一下部中。一閘極電極係形成在位於屏蔽電極上方但與其絕緣之各溝槽的一上部中。一第二傳導類型的第一及第二井區在該對溝槽之間形成於半導體區中以使第一及第二井區彼此垂直地分隔且側向地抵靠該對溝槽的側壁。閘極電極及第一屏蔽電極相對於第一及第二井區形成以當FET在接通狀態中被偏壓時使一通道形成於第一及第二井區各者中。
一實施例中，第一井區在各溝槽中側向地直接位於閘極電極旁邊，而第二井區在各溝槽中側向地直接位於第一屏蔽電極旁邊。
另一實施例中，該方法進一步包括下列步驟。形成一用以襯墊於各溝槽的下側壁及底部之屏蔽介電質。形成一用以襯墊於各溝槽的上側壁之閘極介電質。形成側翼式包圍各溝槽的上側壁之第二傳導類型的源極區。形成延伸於第一井區中之第一傳導類型的一重體部區。
又另一實施例中，第一井區延伸於第二井區上方，而第一區在第二井區之前形成。
再另一實施例中，第一井區延伸於第二井區上方，且該方法進一步包括將第一傳導類型的一第三井區在該對溝槽之間形成於半導體區中之步驟。第三井區抵靠該對溝槽的側壁且與第二井區垂直地分隔。
將從圖式及本發明實施例的下文詳細描述來得知本發明的進一步特徵構造、其本質及優點。
圖式簡單說明
第1圖為一習知屏蔽閘極MOSFET之簡化橫剖視圖；
第2A圖為根據本發明的一示範性實施例之一雙通道屏蔽閘極MOSFET的簡化橫剖視圖；
第2B圖為第2A圖的MOSFET之電路均等物；
第3A-3C圖為根據本發明的示範性實施例之不同多通道屏蔽閘極溝槽MOSFET的簡化橫剖視圖；
第4A-4E圖為根據本發明的一示範性實施例之一用於製作一雙通道屏蔽閘極溝槽FET之製程的簡化橫剖視圖；
第5A-5F圖為根據本發明的一示範性實施例之另一用於製作一雙通道屏蔽閘極溝槽FET之製程的簡化橫剖視圖；
第6圖為顯示沿著一雙通道屏蔽閘極FET的深度之電場輪廓的模擬結果之繪圖；
第7圖為顯示對於一習知屏蔽閘極FET及一雙通道屏蔽閘極FET的各者之汲極電流vs.汲極電壓的模擬結果之繪圖；
第8圖為顯示對於一習知屏蔽閘極FET及一雙通道屏蔽閘極FET之閘極-汲極電荷Qgd vs.屏蔽電極上的電壓的模擬結果之繪圖；
第9圖為顯示對於一習知屏蔽閘極FET vs.一雙通道屏蔽閘極FET之汲極-源極崩潰電壓BVdss的模擬結果之繪圖。
 較佳實施例之詳細說明
根據本發明的實施例來描述沿著各溝槽側壁具有多通道之屏蔽閘極溝槽FET及其製造方法。將可看出，此等FET實質地改良先前技藝FET結構的特定效能特徵而不犧牲電晶體的其他效能特徵。這些改良係包括較高的BVdss、較低的Rdson、較低的閘極電荷、及經改良的UIS與回彈(snap back)特徵。將參照第2A圖來描述本發明的第一示範性實施例。
第2A圖為根據本發明的一示範性實施例之一雙通道屏蔽閘極功率MOSFET的簡化橫剖視圖。一下漂移區210延伸於一半導體基材205a上方。下漂移區210及基材205a皆為n-型。一p-型屏蔽井區215鋪設於下漂移區210。n-型傳導性的一上漂移區220係鋪設於屏蔽井區215。p-型傳導性的一閘極井區225係鋪設於上漂移區220。
下漂移區210、屏蔽井區215、上漂移區220及閘極井區225係形成一半導體堆積體。溝槽230延伸經過此半導體堆積體並終止於下漂移區210內。經高度摻雜n-型源極區245a延伸於閘極井區225中且側翼式包圍上溝槽側壁。經高度摻雜p-型重體部區249在相鄰的源極區245a之間延伸於閘極井區249中。
溝槽230係包括襯墊於溝槽230的下側壁及底部之屏蔽介電層242(譬如，包含氧化物及氮化物層的一或兩者)。屏蔽電極235a(譬如，包含經摻雜或未摻雜多晶矽)係配置於溝槽230的一下部中。屏蔽電極235a藉由屏蔽介電質242對於相鄰的半導體區呈絕緣。一實施例中，屏蔽介電質242具有300至1000範圍中之一厚度。
一間電極介電質238(譬如包含氧化物)係側向地延伸於屏蔽電極235a上方。一閘極介電質244(譬如包含閘極氧化物)係襯墊於上溝槽側壁。一實施例中，閘極介電質244及IED 238具有相同厚度。另一實施例中，IED 238厚於閘極介電質。一凹入閘極電極240a(譬如，包含經摻雜或未摻雜多晶矽)在溝槽230的一上部中配置於IED238上方。一頂側互連層248電性接觸源極區245a及重體部區249。一背側互連層202電性接觸基材205a的底表面。一實施例中，頂側及背側互連層248、249包含一金屬。
可看出，屏蔽閘極FET 200在結構上許多方面係類似於習知的屏蔽閘極FET，唯一差異在於一額外的井區215與屏蔽電極235a相鄰地嵌入漂移區中。因為井區215緊鄰於屏蔽電極235a，井區215在此處稱為“屏蔽井區”，且因為井區225緊鄰於閘極電極240a，井區225在此處稱為“閘極井區”。屏蔽井區215側向地延伸於台面區的完整寬度且抵靠兩相鄰溝槽的側壁，故將漂移區破開成一上漂移區220及一下漂移區210。
操作期間，由於源極區245a及汲極區205a偏壓至妥當電壓，將一適當正電壓施加至閘極電極240a及屏蔽電極235a各者時，通道244及217係分別沿著溝槽側壁形成於閘極井區225及屏蔽井區215中。因此，一電流路徑經由閘極井區227、上漂移區220、屏蔽井區215及下漂移區210形成於源極區245a與汲極區205a之間。藉由將屏蔽井區215直接在屏蔽電極235a旁邊嵌入漂移區中，實質上形成被序列地連接於汲極及源極區之間的兩個電晶體。這更清楚地顯示於第2B圖的均等電路圖中。第2B圖中，上電晶體260的閘極終端240b、下電晶體270的屏蔽終端235b、源極終端245b、及汲極終端205b係分別對應於第2A圖中的閘極電極240a、屏蔽電極235a、源極區245a及汲極區205a。
第3A-3C圖為第2A圖之雙通道屏蔽閘極FET的三個示範性變異之橫剖視圖。第3A圖的FET 300a類似於第2A圖的FET 200，唯一差異在於有兩個屏蔽井區315a1、315a2嵌入漂移區中而非一者。屏蔽井區315a1、315a2兩者直接位於 屏蔽電極335a旁邊，且因此當FET 300被一施加至屏蔽電極335a的正電壓所接通時，在屏蔽井區315a1及315a2各者中係形成一通道。為此，當FET 300a被接通時，沿著各溝槽側壁形成總共三個通道317a1、317a2、327。請注意兩個屏蔽井區315a1、315a2將漂移區破開成三區：上漂移區320a、中漂移區313a、及下漂移區310。
第3B圖中的FET 300b類似於第3A圖中的FET 300a，唯一差異在於有兩個屏蔽電極335b1、335b2配置於溝槽230中而非一者。屏蔽電極335b1及335b2的各者(於包含有元件310、320b1、320b2的漂移區中)具有與其相鄰之一對應的屏蔽井區315b1、315b2。因此，為了分別形成通道317b1及317b2於各屏蔽井區315b1及315b2中，需分別將一適當的正電壓施加至各屏蔽電極335b1及335b2。屏蔽電極335b1及335b2雖顯示為彼此絕緣，其可在一維度中延伸至頁面中並繞佈往上且離開溝槽外而在其中使其電性束縛在一起。或者，屏蔽電極335b1及335b2可被束縛至兩個不同電壓源。
第3C圖中的FET 300c類似於第2C圖中的FET 300b，唯一差異在於總共有四個屏蔽井區315c11、315c12、315c21、315c22嵌入於包含有元件310、313c1、320c1、313c2及320c2的漂移區中，對於兩屏蔽電極335c1、335c2各有兩個。因此當藉由施加至三個電極340、335c2及335c1各者之妥當正電壓將FET 300c接通時，總共形成五個通道317c11、317c12、317c21、317c22、327。如第3A-3C圖中的示範性變異可看出，屏蔽電極及屏蔽井區可能具有許多組合及變 更，因此本發明並不限於此處顯示及描述的特定組合。
接著，將描述兩用於形成類似第2A圖者的FET結構之示範性製程技術。熟習該技藝者可鑒於此揭示容易地修改這些製程技術以達成第3A-3C圖中之FET結構變異或屏蔽井區及屏蔽電極之其他變更及組合。
第4A-4E圖為根據本發明的一示範性實施例之一用於形成一雙通道屏蔽閘極溝槽FET之製程的不同階段之橫剖視圖。第4A圖中，磊晶區410a利用已知技術形成於半導體基材405上方。磊晶區410a及半導體基材405可摻雜有一諸如砷或磷等n-型摻雜物。一實施例中，半導體基材405被摻雜至位於1x1019 -1x1021 cm-3 範圍之濃度，而磊晶區410a被摻雜至位於1x1018 -1x1019 cm-3 範圍之濃度。
第4B圖中，溝槽430利用已知的矽蝕刻技術形成於磊晶區410a中。一替代性實施例中，溝槽430被蝕刻更深以終止於基材405內。第4C圖中，利用習知技術來形成溝槽430中的不同區及層。利用諸如氮化矽的化學氣相沉積(CVD)、CVD氧化物、或矽的熱性氧化等已知技術來形成襯墊於溝槽430下側壁及底部之屏蔽介電質442(譬如包含氧化物及氮化物層的一或兩者)。屏蔽電極435(譬如包含經摻雜或未摻雜多晶矽)譬如利用習知多晶矽沉積及回蝕技術形成於各溝槽430的一下部中，IED 438(譬如包含熱性氧化物及/或經沉積氧化物)係譬如利用習知熱性氧化及/或氧化物沉積技術形成於屏蔽電極435上方。襯墊於上溝槽側壁之閘極介電質444(譬如包含氧 化物)係譬如利用已知的熱性氧化方法形成。凹入閘極電極440譬如利用習知多晶矽沉積及回蝕方法形成於IED 438上方。雖將IED 438顯示為厚於閘極介電質444，在一替代性實施例中，其被同時地形成且因此具有相同厚度。若在溝槽430中將形成額外的屏蔽電極(如第3B及3C圖)，可以所需要次數重覆進行上述用於形成屏蔽電極及IED之製程步驟。
第4D圖中，一第一p-型井區425(閘極井區)係根據已知技術藉由植入及驅入p-型摻雜物而被形成於磊晶層410a中。一實施例中，閘極井區425可被諸如硼等摻雜物摻雜至位於1x1017 -1x1018 cm-3 範圍中之一濃度。然後利用已知技術進行p-型摻雜物的一高能植入以形成直接在屏蔽電極435旁邊更深入磊晶層410a中之一第二p-型井區415(屏蔽井區)。一實施例中，屏蔽井區415可被諸如硼等摻雜物摻雜至位於1x1016 -1x1018 cm-3 範圍中之一濃度。
需小心選擇對於屏蔽井區435的植入參數以確保屏蔽井區415在處理完成時妥當地對準於屏蔽電極435藉以當屏蔽電極435在接通狀態中被偏壓時可使其中形成一通道。在各溝槽中形成多重屏蔽電極之實施例中，可進行具有不同植入能量之多重屏蔽井植入以形成多重屏蔽井區，其各直接地位於一對應的屏蔽電極旁邊。請注意用於形成屏蔽井區415(於包含有元件410b及420的漂移區中)之植入係在對於閘極井區425的植入之後進行藉以避免閘極井區425驅入期間之屏蔽井區415的往外擴散。然而，藉由小心控制之植入及驅入製程，可使兩植入的次序倒反。
第4E圖中，進行一習知的源極植入以形成一側向地延伸經過閘極井區425的一上部且抵靠溝槽430之經高度摻雜的n-型區。到製程的此點為止植入皆不需要罩幕層，至少在晶粒的主動區中如此。一實施例中，一介電層係在三個植入之前形成於閘極電極440上方。
利用已知方法來形成延伸於閘極電極440上方且與溝槽430相鄰側向地重疊於台面區之介電蓋446(譬如包含BPSG)。介電蓋446因此將一開口在相鄰溝槽之間形成於台面區的一中部上方。進行一習知矽蝕刻以經由介電蓋446所形成的開口將一凹部形成於n-型區中。凹部延伸至n-型區的一底表面下方且進入閘極井區425中。凹部因此將n-型區破開成兩區，而形成源極區445。
進行一習知的重體部植入以經由凹部將重體部區449形成於體部區425中。一頂側互連層448隨後利用已知技術形成於結構上方。頂側互連層448延伸至凹部中以電性接觸源極區445及重體部區449。一背側互連層402形成於晶圓的背側上以電性接觸基材405。請注意第4E圖的胞元結構通常係以一關閉胞元或開放胞元組態在一晶粒中重覆多次。
第5A-5F圖描繪根據本發明另一示範性實施例之另一用於形成一雙通道屏蔽閘極溝槽FET之製程。類似於第4A圖的第5A圖中，n-型磊晶層510a利用已知技術形成於基材505上方。第5B圖中，利用將一p-型磊晶層形成於n-型磊晶層510a上方或利用將p-型摻雜物植入n-型磊晶層510a中使磊晶層510a的一上層轉換成p-型，藉以形成p-型屏蔽井區 515。屏蔽井區515可蓋覆有一薄層的摻砷磊晶(未圖示)以防止後續熱循環期間摻雜物在屏蔽井區515中的往上擴散。
第5C圖中，藉由將一n-型磊晶層形成於屏蔽井區510a上方來形成n-型漂移區520。第5D圖中，利用習知技術，將溝槽530形成為延伸經過不同半導體層且終止於最底部的漂移區510b內。或者，溝槽530可延伸更深入以終止於基材505內。第5E圖中，屏蔽介電質542、屏蔽電極535、IED 538、閘極介電質544、及閘極電極540可以類似於參照第4C圖所述的方式形成於溝槽530中，因此將不予贅述。
接著，利用將p-型摻雜物植入n-型漂移區520中因而使漂移區520的一上層轉換成p-型，藉以形成P-型閘極井區525。第5F圖中，介電蓋546、源極區545、重體部區549、頂側互連層548及背側互連層502皆以類似於上文參照第4E圖所述方式形成而因此將不予贅述。
根據本發明的實施例，溝槽中的一或多個屏蔽電極可以數種不同方式被偏壓。譬如，一或多個屏蔽電極可被偏壓至一恆定的正電壓、可被束縛至閘極電極(故使屏蔽及閘極電極一起切換)、或可被束縛至一獨立於閘極電壓之切換電壓。用於供一或多個屏蔽電極的偏壓之構件可在外部提供或內部產生，譬如來自可取得的供應電壓。在屏蔽電極獨立於閘極電極偏壓被偏壓之實施例中，就使FET的不同結構性及電性特徵構造最適化而言獲得部分彈性。
在一其中使閘極電極切換於20V(接通)與0V(關斷)之間的實施例中，屏蔽電極切換於20V(接通)與10V(關斷)之 間。這將橫越IED 238(第2A圖)的最大值電壓限制至10V，故容許形成一相對較薄的IED。對於此實施例的模擬結果係顯示Rdson的45%改良、約30V的BVdss、及實質低的閘極電荷Qg。在其中使閘極電極240a切換於20V(接通)與0V(關斷)之間的另一實施例中，屏蔽電極235a在接通及關斷狀態中皆被偏壓至20V。對於此實施例的模擬結果已經顯示Rdson的25%改良，約30V的BVdss、及實質低的Qg。
因此，將被施加至閘極電極240a及屏蔽電極235a之理想操作性電壓係決定IED 238的厚度及品質。在其中橫越IED 238出現一較小電壓差(第2A圖)之實施例中，可形成一可有利地能夠形成一較薄上漂移區220藉以獲得較低Rdson之較薄IED 238。藉由沿著各溝槽側壁形成一第二通道來獲得Rdson的進一步降低。參照第6至9圖所示的模擬結果更完整地描述本發明不同實施例的這些及其他優點及特徵構造。
第6圖為顯示沿著一雙通道屏蔽閘極FET 600的深度之電場輪廓的模擬結果之繪圖。如圖所示，兩電場峰值分別發生在對應於井區625及615各者及其埋設漂移區620及604所形成的pn接面之區位617及627處。相反地，在諸如第1圖的FET 100等習知單通道屏蔽閘極FET中，只有一個峰值發生在井區104與其埋設漂移區之間的pn接面處。因此，雙通道FET結構600可有利地增加電場曲線底下之面積，其將增大電晶體崩潰電壓。可看出當額外屏蔽井區嵌入漂移區中時，將在電場輪廓中感應引發額外峰值因此進一步增加電晶體崩潰電壓。崩潰電壓的改良係能夠增加漂移區604及 620中的摻雜濃度藉此降低Rdson。亦即，對於與先前技藝FET相同之崩潰電壓，可獲得一較高Rdson。
第7圖為顯示對於一習知屏蔽閘極FET(曲線610標示為“控制組”)及一雙通道屏蔽閘極FET(曲線620標示為“經改良”)的各者之汲極電流vs.汲極電壓的繪圖。可易於看出，藉由雙通路屏蔽閘極FET來實現汲極電流的顯著增加。
習知的屏蔽閘極FET中，經輕度摻雜漂移區中的空乏電荷係對於Qgd具有顯著貢獻。然而，根據本發明的多通道屏蔽閘極FET中，因為多通道漂移區中的正電荷被其相鄰多重井區中的負電荷所補償，故可實現盡量降低漂移區中電荷對於Qgd之衝擊。第8圖為顯示對於一習知屏蔽閘極FET(曲線810)vs.一雙通道屏蔽閘極FET(曲線820)的各者之閘極-汲極電荷Qgd vs.屏蔽電極上的電壓之模擬結果的繪圖。一施加至屏蔽電極235a之偏壓電壓(第2A圖)係變動於從約6至20V並測量Qgd。可看出，藉由雙通道屏蔽閘極FET來實現閘極-汲極電容Cgd 的顯著降低(在低屏蔽偏壓處之近似40%降低)。
第9圖為顯示對於一習知屏蔽閘極FET(曲線910)及一雙通道屏蔽閘極FET(曲線920)的各者之汲極-源極崩潰電壓BVdss 的模擬結果之另一繪圖。可看出，藉由雙通道屏蔽閘極FET來實現BVdss 的顯著增加。這提供調整溝槽中的不同介電層厚度之額外彈性以改良FET的其他特徵。
多重井屏蔽閘極FET的另一特徵構造係為經改良的UIS及回彈特徵。多重井區係導致數個背對背連接式pn二極 體之形成，其具有類似於熟知的多重環齊納結構(zener structure)的功能藉以提供優良的UIS及回彈特徵。
因此可看出，藉由對於製造製程相對極小的變化(譬如添加一屏蔽井植入)，根據本發明的實施例之多通道屏蔽閘極FET係改良電晶體的不同效能特徵而不負面地衝擊其其他特徵。如上述，所達成的改良係包括較低的Rdson、較低的閘極電荷、較高的BVdss、及經改良的UIS及回彈特徵。
雖然上述提供本發明不同實施例的完整描述，可能具有許多替代方式、修改及均等物。譬如，已就n-通路屏蔽閘極MOSFET的脈絡來描述本發明的不同實施例，然而本發明不只限於此等FET。譬如，可僅藉由使不同半導體區的傳導類型倒反來形成此處所顯示及描述之不同屏蔽閘極MOSFET的p-通道對偶部分。另一範例中，可只藉由使基材的傳導類型倒反來形成此處所描述的MOSFET之n-通道IGBT對偶部分，且可藉由使基材除外之不同半導體區的傳導類型倒反來形成p-通道IGBT對偶部分。並且，雖然已概括在示範性實施例中使用植入來形成經摻雜區，熟習該技藝者將瞭解可以此處所描述的植入步驟來取代或添加至諸如擴散等其他用於形成摻雜區之手段。因此，上文描述不應視為限制住由申請專利範圍所界定之本發明的範圍。
100‧‧‧習知屏蔽閘極溝槽MOSFET
101‧‧‧經高度摻雜n-型基材
102,510a‧‧‧N-型磊晶層
104‧‧‧p-型井區
106,249‧‧‧經高度摻雜p-型重體部區
108,245a‧‧‧經高度摻雜n-型源極區
110,230,430,530‧‧‧溝槽
114,235a,335a,335b1,335b2,335c1,335c2,435,535‧‧‧屏蔽電極
115,542‧‧‧屏蔽介電質
116‧‧‧間電極介電(IED)層
120,244,444,544‧‧‧閘極介電質
122,440,540‧‧‧閘極電極
124,446,546‧‧‧介電蓋
126,248,448,548‧‧‧頂側互連層
200‧‧‧屏蔽閘極FET
202,402,502‧‧‧背側互連層
205a‧‧‧汲極區，半導體基材
205b‧‧‧汲極終端
210,310‧‧‧下漂移區
215,515‧‧‧p-型屏蔽井區
217,317a1,317a2,317c11,317c12,317c21,317c22,327‧‧‧通道
220,320a‧‧‧上漂移區
225,227‧‧‧閘極井區
235b‧‧‧屏蔽終端
238,438,538‧‧‧間電極介電質(IED)
240a,440‧‧‧凹入閘極電極
240b‧‧‧閘極終端
242‧‧‧屏蔽介電層
245b‧‧‧源極終端
260‧‧‧上電晶體
270‧‧‧下電晶體
300a,300b,300c‧‧‧FET
313a‧‧‧中漂移區
315a1,315a2,315b1,315b2,315c11,315c12,315c21,315c22,340‧‧‧電極
405‧‧‧半導體基材
410a‧‧‧磊晶區
415‧‧‧第二p-型井區，屏蔽井區
425‧‧‧第一p-型井區，閘極井區
445,545‧‧‧源極區
449,549‧‧‧重體部區
505‧‧‧基材
510b,604,620‧‧‧漂移區
520‧‧‧n-型漂移區
525‧‧‧P-型閘極井區
600,820,920‧‧‧雙通道屏蔽閘極FET
610,810,910‧‧‧習知屏蔽閘極FET
615,625‧‧‧井區
617,627‧‧‧區位
BVdss ‧‧‧汲極-源極崩潰電壓
Qg‧‧‧閘極電荷
Rdson‧‧‧電晶體接通電阻
第1圖為一習知屏蔽閘極MOSFET之簡化橫剖視圖；第2A圖為根據本發明的一示範性實施例之一雙通道屏蔽閘極MOSFET的簡化橫剖視圖； 第2B圖為第2A圖的MOSFET之電路均等物；第3A-3C圖為根據本發明的示範性實施例之不同多通道屏蔽閘極溝槽MOSFET的簡化橫剖視圖；第4A-4E圖為根據本發明的一示範性實施例之一用於製作一雙通道屏蔽閘極溝槽FET之製程的簡化橫剖視圖；第5A-5F圖為根據本發明的一示範性實施例之另一用於製作一雙通道屏蔽閘極溝槽FET之製程的簡化橫剖視圖；第6圖為顯示沿著一雙通道屏蔽閘極FET的深度之電場輪廓的模擬結果之繪圖；第7圖為顯示對於一習知屏蔽閘極FET及一雙通道屏蔽閘極FET的各者之汲極電流vs.汲極電壓的模擬結果之繪圖；第8圖為顯示對於一習知屏蔽閘極FET及一雙通道屏蔽閘極FET之閘極-汲極電荷Qgd vs.屏蔽電極上的電壓的模擬結果之繪圖；第9圖為顯示對於一習知屏蔽閘極FET vs.一雙通道屏蔽閘極FET之汲極-源極崩潰電壓BVdss的模擬結果之繪圖。
200‧‧‧屏蔽閘極FET
202‧‧‧背側互連層
205a‧‧‧汲極區，半導體基材
210‧‧‧下漂移區
215‧‧‧p-型屏蔽井區
217‧‧‧通道
220‧‧‧上漂移區
225,227‧‧‧閘極井區
230‧‧‧溝槽
235a‧‧‧屏蔽電極
238‧‧‧間電極介電質(IED)
240a‧‧‧凹入閘極電極
242‧‧‧屏蔽介電層
244‧‧‧閘極介電質
245a‧‧‧經高度摻雜n-型源極區
248‧‧‧頂側互連層
249‧‧‧經高度摻雜p-型重體部區

Claims (20)

  1. 一種半導體裝置，其包含：一對溝槽，其延伸至屬於一第一傳導類型的一半導體區中；一屏蔽電極，其設置於該對溝槽中之一溝槽中；一閘極電極，其設置於該對溝槽中之該溝槽中並在該屏蔽電極上方，該閘極電極係與該屏蔽電極呈絕緣；一源極區，其屬於該第一傳導類型，並與該對溝槽中之該溝槽相聯結(associated)；一第一井區，其屬於一第二傳導類型，並設置於該對溝槽之間且在該源極區下方的該半導體區中，該第一井區抵靠於該對溝槽中之該溝槽的一側壁，該第二傳導類型係與該第一傳導類型相反；一第二井區，其屬於該第二傳導類型，並設置於該對溝槽之間的該半導體區中，該第二井區抵靠於該對溝槽中之該溝槽的該側壁；以及一第三井區，其屬於該第一傳導類型，並設置於該對溝槽之間且於該第一井區和該第二井區之間，該第三井區抵靠於該對溝槽中之該溝槽的該側壁。
  2. 如申請專利範圍第1項之半導體裝置，其中該第一井區、該第二井區和該第三井區係與該屏蔽電極相聯結。
  3. 如申請專利範圍第1項之半導體裝置，其中該第一井區、該第二井區和該第三井區係對該屏蔽電極呈側向設置。
  4. 如申請專利範圍第1項之半導體裝置，其中該屏蔽電極係相對於該第一井區和該第二井區而形成，使得當施加一電壓於該屏蔽電極時，一通道係形成於該第一井區和該第二井區的每一者中。
  5. 如申請專利範圍第1項之半導體裝置，其中該屏蔽電極係一第一屏蔽電極，該半導體裝置進一步包含：一第二屏蔽電極，其與該第一屏蔽電極電性呈絕緣。
  6. 如申請專利範圍第1項之半導體裝置，其中該屏蔽電極係一第一屏蔽電極，該第一井區、該第二井區和該第三井區係對該第一屏蔽電極呈側向設置，該半導體裝置進一步包含：一第二屏蔽電極，其與該第一屏蔽電極呈電性絕緣。
  7. 如申請專利範圍第1項之半導體裝置，其中該屏蔽電極係一第一屏蔽電極，該半導體裝置進一步包含：一第二屏蔽電極；一介電質，其設置於該第一屏蔽電極和該第二屏蔽電極之間的該溝槽中，該第二屏蔽電極係電性耦接到該第一屏蔽電極。
  8. 一種半導體裝置，其包含：一溝槽，其延伸至屬於一第一傳導類型的一半導體區中；一電極，其設置於該溝槽中； 一源極區，其屬於該第一傳導類型，並抵靠該溝槽之一側壁；一第一井區，其屬於一第二傳導類型，並設置於該源極區下方的該半導體區中，並抵靠對該電極呈側向之該溝槽的該側壁，該第二傳導類型係與該第一傳導類型相反；一第二井區，其屬於該第二傳導類型，並設置於該半導體區中且抵靠該溝槽的該側壁；以及一第三井區，其屬於該第一傳導類型，並設置於該半導體區中且於該第一井區和該第二井區之間，該第三井區抵靠於該溝槽的該側壁。
  9. 如申請專利範圍第8項之半導體裝置，其中該第一井區、該第二井區和該第三井區係與該電極相聯結。
  10. 如申請專利範圍第8項之半導體裝置，其中該電極係一屏蔽電極，該屏蔽電極係相對於該第一井區和該第二井區而形成，使得當施加一電壓於該屏蔽電極時，一通道係形成於該第一井區和該第二井區的每一者中。
  11. 如申請專利範圍第8項之半導體裝置，其中該電極係一屏蔽電極，該半導體裝置進一步包含：一閘極電極，其設置於該溝槽中且在該屏蔽電極上方，該閘極電極係與該屏蔽電極的至少一部分呈絕緣；以及一第四井區，其設置於該第一井區和該第二井區之 間，該第四井區係對該閘極電極呈側向設置。
  12. 如申請專利範圍第8項之半導體裝置，其中該電極係一閘極電極，該半導體裝置進一步包含：一屏蔽電極，其設置於該溝槽中且在該閘極電極下方，該屏蔽電極係與該閘極電極的至少一部分呈絕緣，該第二井區係對該屏蔽電極呈側向設置。
  13. 如申請專利範圍第8項之半導體裝置，其中該電極係一第一屏蔽電極，該半導體裝置進一步包含：一第二屏蔽電極，其與該第一屏蔽電極呈電性絕緣。
  14. 如申請專利範圍第8項之半導體裝置，其中該電極係一第一屏蔽電極，該第一井區、該第二井區和該第三井區係對該第一屏蔽電極呈側向設置，該半導體裝置進一步包含：一第二屏蔽電極，其與該第一屏蔽電極呈電性絕緣。
  15. 如申請專利範圍第8項之半導體裝置，其中該電極係一第一屏蔽電極，該半導體裝置進一步包含：一第二屏蔽電極；一介電質，其設置於該第一屏蔽電極和該第二屏蔽電極之間的該溝槽中，該第二屏蔽電極係電性耦接到該第一屏蔽電極。
  16. 一種半導體裝置，其包含： 一溝槽，其延伸至屬於一第一傳導類型的一半導體區中；一屏蔽電極，其設置於該溝槽中；一閘極電極，其設置於該溝槽中且於該屏蔽電極上方，該閘極電極係與該屏蔽電極呈絕緣；一源極區，其屬於該第一傳導類型，並抵靠該溝槽之一側壁；一第一井區，其屬於一第二傳導類型，並設置於該源極區下方的該半導體區中且抵靠該溝槽的該側壁，該第二傳導類型係與該第一傳導類型相反；一第二井區，其屬於該第二傳導類型，並設置於該半導體區中且抵靠該溝槽的該側壁；以及一第三井區，其屬於該第一傳導類型，並設置於該半導體區中且於該第一井區和該第二井區之間，該第三井區抵靠於該溝槽的該側壁。
  17. 如申請專利範圍第16項之半導體裝置，其中該第一井區、該第二井區和該第三井區係對該屏蔽電極呈側向設置。
  18. 如申請專利範圍第16項之半導體裝置，其中該屏蔽電極係相對於該第一井區和該第二井區而形成，使得當施加一電壓於該屏蔽電極時，一通道係形成於該第一井區和該第二井區的每一者中。
  19. 如申請專利範圍第16項之半導體裝置，進一步包含：一重體部區(heavy body region)，其屬於該第二傳導 類型，並與該源極區接觸。
  20. 如申請專利範圍第16項之半導體裝置，其中該閘極電極和該屏蔽電極係相對於該第一井區和該第二井區而定位，使得當該半導體裝置被偏壓於導通狀態時，一通道係形成於該第一井區和該第二井區的每一者中。
TW097149388A 2007-12-26 2008-12-18 用於形成具多通道之屏蔽閘極溝槽場效電晶體（ｆｅｔ）的結構及方法 TWI509798B (zh)

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US7772668B2 (en) 2010-08-10
US20090166728A1 (en) 2009-07-02
CN101971304B (zh) 2012-10-10
CN101971304A (zh) 2011-02-09
US9224853B2 (en) 2015-12-29
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