CN101542731B - 沟槽栅场效应晶体管及其制造方法 - Google Patents

沟槽栅场效应晶体管及其制造方法 Download PDF

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CN101542731B
CN101542731B CN2006800184437A CN200680018443A CN101542731B CN 101542731 B CN101542731 B CN 101542731B CN 2006800184437 A CN2006800184437 A CN 2006800184437A CN 200680018443 A CN200680018443 A CN 200680018443A CN 101542731 B CN101542731 B CN 101542731B
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CN101542731A (zh
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哈姆扎·耶尔马兹
丹尼尔·卡拉菲特
克里斯托弗·博古斯瓦·科考恩
史蒂文·P·萨普
迪安·E·普罗布斯特
内森·L·克拉夫特
托马斯·E·格雷布斯
罗德尼·S·里德利
加里·M·多尔尼
布鲁斯·D·马钱特
约瑟夫·A·叶季纳科
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Fairchild Semiconductor Corp
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Abstract

一种场效应晶体管，包括在第二传导类型的半导体区之上的第一传导类型的主体区。栅沟槽延伸穿过主体区并且在半导体区中终止。至少一个导电保护电极被置于栅沟槽中。栅极被置于在至少一个导电保护电极之上但是与其隔离开的栅沟槽中。保护电介质层将至少一个导电保护电极与半导体区隔离开。栅电介质层将栅极与主体区隔离开。这样形成保护电介质层，以使其向外张开并且直接在主体区之下延伸。

Description

沟槽栅场效应晶体管及其制造方法
相关专利的交叉参考 
本申请要求于2005年5月26日提交的美国临时专利申请第60/685,727号的权益，将其全部内容结合于此作为参考。 
将共同转让的于2004年12月29日提交的美国专利申请第11/026,276的全部内容结合于此作为参考。 
技术领域
本发明涉及半导体功率器件，更确切地说，涉及改良的沟槽栅功率器件和其制造方法。 
背景技术
图1为传统沟槽栅金属氧化物半导体场效应晶体管(MOSFET)100的横截面图，该传统MOSFET具有已知的物理和执行特性以及，例如单元间距(cell pitch)、击穿电压能力、导通电阻(Rdson)、晶体管耐用度的局限。沟槽栅105延伸穿过P型阱106并且在n型外延层区104中终止。沟槽栅105包括沟槽侧壁和底部内衬的栅电介质114，以及凹进的栅极112。电介质层116和118将栅极112与相互连接的重叠源极隔离开。 
图2为传统双栅沟槽金属氧化物半导体场效应晶体管(MOSFET)200(也被称为保护沟槽栅金属氧化物半导体场效应晶体管)的横截面图，其改进了图1的沟槽-栅沟槽MOSFET的某  些特性。沟槽205包括通过保护电介质层222与漂移区204隔离开的保护电极220。沟槽205还包括在保护电极220之上并且通过多晶硅层间电介质层(inter-poly dielectric layer)224与保护电极220隔离开的栅极212。保护电极220降低栅-源电容(Cgd)并且提高击穿电压。但是，单栅晶体管100和双栅晶体管200的一个缺点是漂移区占到总导通电阻(Rdson)的大约40％，严重限制了导通电阻的改进。对于双栅沟槽结构，更深的沟槽需要甚至更厚的漂移区从而使这个问题更加严重。沟槽栅晶体管100和200的另一个缺点是沟槽底部的高电场由于底部沟槽的弯曲限制了几种性能参数的改进，例如击穿电压和晶体管耐用度。一些应用要求将肖特基二极管与功率MOSFET进行集成。但是，这样的集成通常需要复杂的、具有多个程序和掩模步骤的工艺技术。 
因此，存在着对节省成本的结构和制造沟槽栅FET、单片集成二极管和MOSFET结构，以及消除或最小化与现有技术相关的缺点的终端结构的方法的需要，这样就可以实质上改进沟槽栅FET的物理和执行特性。 
发明内容
场效应晶体管包括在第二传导类型的半导体区之上的第一传导类型的主体区。栅沟槽延伸穿过该主体区并且在半导体区中终止。至少一个导电保护电极被置于栅沟槽中。栅极被置于至少一个导电保护电极之上的并且与其隔离开的栅沟槽中。保护电介质层将该至少一个导电保护电极与该半导体区隔离开。栅极电介质层将栅极与主体区隔离开。形成保护电介质层，以使其向外张开并且在主体区之下直接延伸。 
在一个具体实施方式中，半导体区包括衬底区和该衬底区之上的漂移区。主体区在漂移区之上延伸，并且具有比衬底区低的掺杂浓度。栅沟槽延伸穿过该漂移区并且在该衬底区内终止。 
根据本发明的另外一个具体实施方式，场效应晶体管的形成如下所述。形成延伸到半导体内的第一深度的上沟槽部分。上沟槽部分的侧壁内衬以保护层材料，以使沿着至少上沟槽部分的部分底部壁的半导体区保持暴露。下沟槽部分延伸穿过上沟槽部分的暴露的底部壁形成，同时具有保护上沟槽部分的侧壁的保护层材料。上沟槽部分的宽度比下沟槽部分的宽度大。 
在一个具体实施方式中，保护电介质层沿着下沟槽部分的侧壁和底部壁形成。保护层材料被去除。沿着上沟槽部分的侧壁形成第二隔离层(绝缘层)，第一隔离层的厚度比第二隔离层的厚度大。 
在另外一个具体实施方式中，第一隔离层通过硅局部氧化(LOCOS)形成。 
在另外一个具体实施方式中，导电保护电极形成在下沟槽部分中。多晶硅层间介质体(interpoly dielectric)形成在导电保护电极之上，并且栅极形成在多晶硅层间介质体之上。 
根据本发明的另外一个具体实施方式，场效应晶体管包括在第二传导类型的半导体区内的第一传导类型的主体区。栅沟槽延伸穿过该主体区并且在该半导体区内终止。第二传导类型的源极区在邻近栅沟槽的主体区内，以使该源极区以及主体区和半导体区之间的分界面限定了沿着栅沟槽侧壁延伸的通道区。第二传导类型的通道增强区邻近该栅沟槽。通道增强区部分延伸进入通道区的下部，从而降低通道区的电阻。 
在一个具体实施方式中，栅极置于栅沟槽中，并且通道增强区与沿着该沟槽栅侧壁的栅极重叠。 
在另外一个具体实施方式中，至少一个导电保护电极安置于栅沟槽中。栅极安置于在至少一个的导电保护电极之上但是与其隔离开的栅沟槽中。保护电介质层将至少一个导电保护电极与半导体区隔离开。栅电介质层将栅极与主体区隔离开。 
根据本发明的另外一个具体实施方式，场效应晶体管的形成如以下所述。在半导体区中形成沟槽。在沟槽中形成保护电极。进行第一传导类型的杂质的成角侧壁注入，以形成邻近沟槽的通道增强区。在半导体区中形成第二传导类型的主体区。第一传导类型的源极区在主体区中这样形成，以使源极区以及主体区和半导体区之间的界面限定了沿着栅沟槽侧壁延伸的通道区。通道增强区部分延伸入该通道区的下部，从而降低该通道区的电阻。 
在一个具体实施方式中，栅极在保护电极之上形成但是与该保护电极隔离开。 
在另外一个具体实施方式中，通道增强区自对准保护电极。 
根据本发明的另外一个具体实施方式，场效应晶体管包括延伸进入半导体区的栅沟槽。该栅沟槽具有置于其内的凹进(凹陷)的栅极。半导体区中的源极区与该栅沟槽的每侧相接。用导电材料填充该栅沟槽的上部使得与该源极区沿着每个源极区的至少一个侧壁电性接触，导电材料与凹进的栅极隔离开。 
根据本发明的另外一个具体实施方式，场效应晶体管按以下所述形成。在半导体区内形成沟槽。在该沟槽内形成凹进的栅极。双通道成角注入杂质，以在沟槽的每一侧上形成源极区。电介质层在  凹进的栅极之上形成。用导电材料填充沟槽，以使导电材料与该源极区电性接触。 
在一个具体实施方式中，导电材料包含掺杂质的多晶硅。 
通过以下的详细描述和附图可以更好地理解本发明的特性和优势。 
附图说明
图1是传统单栅沟槽MOSFET的横截面图。 
图2是传统双栅沟槽MOSFET的横截面图。 
图3是根据本发明的一个具体实施方式的具有延伸入衬底的栅沟槽保护电极的双栅沟槽MOSFET的横截面图。 
图4是根据本发明的另外一个具体实施方式的其中使用LOCOS方法形成保护电介质双栅沟槽MOSFET的横截面图，； 
图5是根据本发明的另外一个具体实施方式的具有侧壁增强型通道区的双栅沟槽MOSFET的横截面图； 
图6是根据本发明的另外一个具体实施方式的具有源极插件区(source plug region)的双栅沟槽MOSFET的横截面图。 
图7是根据本发明的另外一个具体实施方式的具有侧壁通道增强区、源极插件区和LOCOS保护电介质的双栅沟槽的横截面图； 
图8是根据本发明的另外一个具体实施方式的与肖特基二极管单片集成的双栅沟槽MOSFET的横截面图； 
图9是根据本发明的另外一个具体实施方式的与双栅沟槽MOSFET集成的紧密边缘终端结构； 
图10A-10E是根据本发明的另外一个具体实施方式的用于形成图4的MOSFET400的处理模块的不同工艺步骤的横截面图； 
图11是根据本发明的另外一个具体实施方式的对应于用于形成图5的MOSFET500的处理模块的横截面图； 
图12A-12D是根据本发明的另外一个具体实施方式的用于形成图6的MOSFET600的处理模块的不同工艺步骤的横截面图；和 
图13A-13L是根据本发明的一个具体实施方式的形成双栅沟槽MOSFET的示例性制造过程的不同步骤的横截面图。 
具体实施方式
通过图13A-13L中的横截面图描述的工艺次序是形成本发明的一个具体实施方式的双栅沟槽MOSFET的示例性程序。这个加工次序会被用作基础程序，其会被进行修改以包括形成以下所披露的不同的单元结构的各种处理模块。请注意，这里所披露的处理模块也可以集成其它基础程序，并不限于图13A-13L所描述的程序。接下来会披露图13A-13L的加工次序。 
图13A中，n型外延层1302在n型重掺杂衬底(未示出)之上形成。注入P型导电掺杂物以在外延层1302中形成主体区1304。硬掩模1306，例如包含氧化物-氮化物-氧化物(ONO)复合层，用于限定并且蚀刻延伸穿过主体区1304并且进入外延层1302的沟槽1308。 
图13B中，使用传统技术，保护电介质层1310(例如包含氧化物)形成了沟槽侧壁和底部的内衬并且延伸到硬掩模1306之上。在图13C中，保护电极1312的通过沉积多晶硅层以填充沟槽1308，然后回蚀多晶硅使多晶硅深凹入沟槽1308中形成。然后，保护电介质1310凹陷，在沟槽侧壁上留下电介质薄层1313。保护电极1312进一步凹陷使它的顶部表面与凹陷保护电介质的顶部表面在一个水平上。 
图13D中，氮化物层沉积，然后被各向异性蚀刻，使得只有沿着沟槽侧壁延伸的氮化物层的部分1314保留。在图13E中，多晶硅层间介质体(IPD)1316通过进行热氧化形成。氧化物层只在保护电极1312之上形成，因为所有的其它硅表面都被氮化物或氧化物所覆盖。在一个可替换的具体实施方式中，工艺次序进行了修改以适于使用双氧化层形成IPD层。首先，在保护电极之上形成热氧化物层，然后使用SACVD沉积氧化物保形层以便获得均一的IPD层。 
在图13F中，进行氧化蚀刻以除去ONO复合层1306的顶部氧化物层以及沿着沟槽侧壁的氮化物层之上形成的任何氧化物。然后，剥去此时所暴露的ONO复合层的氮化物层以及沿着沟槽侧壁的氮化物层1314。再进行另外一氧化蚀刻以沿着沟槽侧壁以及ONO复合层1306的底部氧化层除去电介质层1313，使得沿着沟槽侧壁和图13F中所示的邻近沟槽的台面区的硅被暴露出来。在图13G中，使用已知的技术形成沿着沟槽侧壁延伸、经过多晶硅层间介质体并且在邻近沟槽的台面区之上的栅电介质层1318。在图13H中，沉积填充沟槽的多晶硅层，然后多晶硅层被回蚀以在沟槽中形成凹陷的栅极1320。 
在图13I中，在台面之上的栅极电介质被回蚀到合适于源极注入(source implant)的厚度。进行在作用区中的覆盖源极注入(blanket  source implant)以形成在台面区中的邻近沟槽之间延伸的n型区1322。在图13J中，使用传统方法在沟槽和台面之上形成BPSG层1324A。在图13K中，使用掩模层(未示出)，除去除了在沟槽和n型区1322a之上的1324B部分的BPSG层1324A。这样，邻近BPSG部分1324的硅台面表面被暴露。然后进行硅蚀刻使暴露的硅表面凹陷到低于n型区1322a的深度，这样就形成接触开口1326。硅的凹陷除去了每个n型区1322a的一部分，留下了后面的自对准源极区1322b。在图13L中，进行高粘度注入(heavy body implant)以在主体区1304中形成p型传导的自对准高粘度区1329。进行BPSG回流以获得接触窗口的更好的纵横比以及随后形成对于源极互连层1330的更好的阶梯覆盖。源极互连(source interconnect)1330电性接触高粘度区1329和源极区1322。 
各种单元结构，它们相对应的处理模块以及这些处理模块与图13A-13L所描述的工艺流程相结合的方式会随后进行披露。图3显示了双栅沟槽MOSFET 300的横截面图，其除了栅305和保护电极320延伸进入衬底302中，与图13L中的双栅MOSFET结构相似。这有利地可使漂移区的厚度大体上被降低从而提高Rdsom。另外，衬底的高掺杂浓度将电位降转移到保护氧化物中，这样就消除了与传统沟槽结构相关的曲率极限击穿(curvature-limited breakdown)问题。这也改进了装置的耐用度，因为雪崩点(即最大碰撞电离率)转移到晶体管台面的中心并且远离与引起耐用度丧失相关的寄生双极性元件(parasitic bipolar elements)。图13A-13L中的工艺次序唯一需要进行的修改是图13A中需要在衬底之上形成薄外延层使得沟槽延伸到衬底中。 
图4显示了根据本发明的一个具体实施方式的使用LOCOS工艺形成保护电介质422的双栅沟槽MOSFET400的横截面图。虚线表示沟槽605的轮廓。在形成保护电介质422中，LOCOS工艺导致邻近沟槽605的硅的消耗从而造成保护电介质433向外张开并且  直接在主体区406之下延伸。LOCOS工艺是形成保护电介质422并且还产生均匀薄膜的有利的、节省成本的方法。MOSFET 400的上部与图3中的MOSFET 300的上部相似。当沟槽605和保护电极420被显示延伸到衬底402中时，它们可以类似于图2的MOSFET200中示出的二者选一地在N-区404中终止。在一个具体实施方式中，通过将图10A-10E的横截面图所描述的处理模块与随后的图13A-13L的工艺流程结合来形成MOSFET 400。 
对应于图13A-13L的工序被对应于图10A-10E的工序所代替。除了在图10A中形成正好经过主体区1004延伸的较浅的沟槽1008，对应于图10A的工序与对应于图13A的工序相同。在图10B中，氮化物间隙壁(隔离层，spacer)1010沿着沟槽侧壁形成。在图10C中，进行硅蚀刻(自对准氮化物间隙壁1010)从而将沟槽1008更深入延伸到硅区1002中。这样，栅沟槽具有了更宽的上部1008和更窄的下部1012。在图10D中，进行LOCOS工艺，从而使保护电极1014的自对准层沿着暴露的硅表面，即在下沟槽部1012中形成。LOCOS工艺消耗部分所示(虚线表示下沟槽部1012的轮廓)的硅区1002。在图10E中，通过沉积多晶硅层在沟槽中形成保护电极1016，然后回蚀多晶硅使多晶硅深凹进沟槽中。接下来进行对应于图13E-13L的工序来完成单元结构。图中的不同的层和区的厚度和尺寸可能是不按规定比例的。例如，在图10D中，氮化物间隙壁1010在实际中可以是比它们看起来薄的，以使LOCOS保护电介质1014的部分向外张开并且直接在主体区1004之下延伸。 
图5示出了根据本发明的另外一个具体实施方式的双栅沟槽MOSFET 500的横截面图，其除了在MOSFET 500中结成一体的侧壁通道增强区526，与图3中的MOSFET 300相似。通道增强区526沿着MOSFET 500的每个通道区的底部形成以校正通道区中的掺杂浓度分布曲线的尾部。从而，沟道长度和沟道电阻被有利地降低。因为通道区中的掺杂浓度峰值正好出现在源极区510之下(即远离  通道区的底部)，附加通道增强区526不会反向影响晶体管的阈值电压。假设MOSFET 500为n-沟道，通道增强区526则为n型。正如前面的具体实施方式中，MOSFET 500可以进行修改，使得沟槽505终止在漂移区504中而不是在衬底502中。在一个具体实施方式中，通过将图11的横截面图所描述的处理模块与随后的图13A-13L的工艺流程结合来形成MOSFET 500。 
对应于图11的处理模块需要在图13F之后但是在图13G之前进行。也就是，在进行完对应于图13A-13F的步骤之后，如图11所示沿着沟槽侧壁形成氧化物层(screen oxide)1112。氧化物层1112的厚度要适合于穿过其注入掺杂物。在图11中，以预先确定的角度进行n型掺杂物的通道增强注入1113以形成沿着一个沟槽侧壁的通道增强区，并且以图11所示的相对的角度进行第二通道增强注入以形成沿着相对的沟道侧壁的通道增强区。通道增强区可以是自对准在前面步骤中形成的IPD 1124。然后进行对应于图13G-13L的工序以完成单元结构。在一个具体实施方式中，主体区在通道增强注入1113之前形成，在可替换的具体实施方式中，主体区是在通道增强注入1113之后形成。 
图6示出了根据本发明的另外一个具体实施方式的具有源极插件区630的双栅沟槽MOSFET 600的横截面图。取代形成如图3中所完成的在栅极614之上的电介质圆顶，在栅极614之上形成薄电介质层628并且电介质层628之上的沟槽605的其余部分被源极插件630(例如，包含多晶硅)填充。源极插件630电性连接栅沟槽605侧面的源极区610。MOSFET 600具有提供用于形成顶部金属的平坦表面的优点。另外，源极插件能够在沟槽侧面的非常狭窄的源极区形成，从而降低单元间距(cell pitch)而不会反向影响源极电阻。通过在形成源极插件630之前进行双通道成角注入形成狭窄的源极区610。MOSFET 600可以进行修改，使得沟槽605在漂移区604中终止而不是在衬底602中。源极插件630可以以相似的方  式结合到例如图1中的传统沟槽栅FET中。在一个具体实施方式中，通过将图12A-12D的横截面图所描述的处理模块与随后的图13A-13L的工艺流程结合来形成MOSFET 600。 
对应于图13H-13L的工序被对应于图12A-12D的工序所取代。也就是，在进行对应的13A-13G的步骤之后，除了如图12A所示的沉积的栅极多晶硅深凹进沟槽中，栅极以与图13H中相似的方式形成。在图12A中，进行n型掺杂物的双通道成角注入以形成沿着沟槽1205的暴露的上侧壁的源极区1210。接下来，如图12B所示，电介质层1216a(例如，包含氧化物)利用压差式填充differential fill来沉积，使得在沟槽中的栅极1212之上形成比在邻近的台面之上更厚的氧化物。在图12C中，均匀地蚀刻电介质层1216a，从而电介质薄层1216b留在了栅极1212之上的沟槽中。在图12C中，沟槽1205被填充掺杂的多晶硅1217。然后，可以用传统技术来形成高粘度区(未示出)、源极互连(未示出)、其它区和层以完成单元结构。源极插件1217可以通过将图12A-12D表示的处理模块结合到传统的形成沟槽栅FET 100的工艺次序中，以相似的方式被结合到图1中的沟槽栅FET 100中。 
图7示出了复合双栅沟槽MOSFET 700的横截面图，其中结合了图4-6中的结构的有利部件。如图所示，n型通道增强区726、源极插件730和LOCOS保护电介质722被结合到MOSFET700中。请注意，根据设计的目的和性能要求，这3个部件中的任意两个可以结合，而不是三个都结合。以上所讨论的每一个MOSFET 400、500和600的可替代具体实施方式也可以应用于MOSFET 700。由于本公开，需要在图13A-13L中的工艺流程进行以形成MOSFET700的修改对于所属领域的一般技术人员是显而易见的。 
图8示出了单片集成肖特基二极管以获得集成MOSFET-肖特基二极管结构800的双栅沟槽MOSFET的横截面图。正如所看到  的，虽然图4-7中的任何MOSFET都可以代替使用，该MOSFET结构与图3中的相似。在图8中，源极互连(未示出)包括肖特基势垒金属，其不仅接触源极区810和高粘度区808，而且在肖特基二极管区之上延伸并且与N-区804b电性接触。与轻度掺杂区804b接触的肖特基势垒金属形成肖特基二极管。肖特基二极管区中的沟槽的结构与MOSFET区中的沟槽结构相同。必须将肖特基二极管结构频繁地结合到作用区中以达到理想的MOSFET与肖特基面积的比率。 
图9示出了与双栅沟槽MOSFET集成的紧密边缘终端结构。正如所看到的，作用区终止在终端沟槽905b中，该终端沟槽包括作为沟槽侧壁和底部内衬的保护电介质以及填充沟槽的保护电极920。正如所看到的，虽然图4-7中的任何MOSFET都可以代替使用，作用区中的MOSFET结构与图3中的相以。 
这里所披露的本发明的各种具体实施方式，可以与以上所引用的、共同转让的美国专利申请第11/026,276中所披露的一个或多个具体实施方式(尤其是保护栅沟槽结构和方法)进行结合以获得具有出众特性的功率器件。 
虽然以上提供了本发明各种具体实施方式的详细披露，多种代替、修改和等同替换是可以的。例如，以上的工艺次序和处理模块是在双栅(保护栅)沟槽结构的环境进行披露的，但是这里所公开的各种具体实施方式的有利特性也可以在如图1中所示的传统沟槽栅TEF的环境中实现。另外，应理解这里所提供的所有材料都只是基于说明的目的。而且，这里所披露的具体实施方式中的一种或多种不同的电介质层可以包含低介电常数或高介电常数的介电材料。例如，在第一次多晶硅沉积之前形成的一个或多个电介质层可以包含高介电常数的介电材料，而在最后的多晶硅沉积之后形成的一个或多个电介质层可以包含低介电常数的介电材料。基于这种和其它  原因，因此，以上的披露不能被认为限定了本发明的范围，本发明的范围由所附的权利要求进行限定。 

Claims (11)

1.一种场效应晶体管，包括：
在第二传导类型的半导体区之上的第一传导类型的主体区；
延伸穿过所述主体区并且在所述半导体区内终止的栅沟槽；
至少一个置于所述栅沟槽中的导电保护电极；
置于所述至少一个导电保护电极之上但是与所述导电保护电极隔离开的栅极；
将至少一个导电保护电极与所述半导体区隔离开的保护电介质层；以及
将所述栅极与所述主体区隔离开的栅电介质层，其中所述保护电介质层向外张开并且直接在所述主体区之下延伸。
2.根据权利要求1所述的场效应晶体管，其中所述半导体区包括：
衬底区；和
在所述衬底区之上的漂移区，所述主体区在所述漂移区之上延伸，所述漂移区具有比所述衬底区低的掺杂浓度，其中所述栅沟槽延伸穿过所述漂移区并且在所述衬底区内终止。
3.一种形成场效应晶体管的方法，包括：
形成延伸到半导体区内第一深度的上沟槽部分；
用保护层材料内衬于所述上沟槽部分的侧壁，使得所述半导体区沿着至少部分所述上沟槽部分的底部壁保持暴露； 
形成穿过具有保护所述上沟槽部分的所述侧壁的保护层材料的所述上沟槽部分的暴露的底部壁的下沟槽部分，从而所述上沟槽部分的宽度大于所述下沟槽部分的宽度；以及
形成沿着所述下沟槽部分的侧壁和底部壁的保护电介质层，使得所述保护电介质层向外张开并且直接在主体区之下延伸。
4.根据权利要求3所述的方法，还包括：
除去所述保护层材料；以及
形成沿着所述上沟槽部分的所述侧壁的第二隔离层，所述保护电介质层具有比所述第二隔离层大的厚度。
5.根据权利要求4所述的方法，其中通过硅的局部氧化(LOCOS)形成所述保护电介质层。
6.根据权利要求3所述的方法，还包括：
形成在所述下沟槽部分中的导电保护电极；
形成在所述导电保护电极之上的多晶硅层间介质体；
形成在所述多晶硅层间介质体之上的栅极。
7.一种场效应晶体管，包括：
在第二传导类型的半导体区中的第一传导类型的主体区；
延伸穿过所述主体区并且在所述半导体区内终止的栅沟槽；
在邻近所述栅沟槽的所述主体区中的所述第二传导类型的源极区，所述源极区以及所述主体区与所述半导体区之间的 界面限定了它们之间的通道区，所述通道区沿着所述栅沟槽侧壁延伸；
邻近所述栅沟槽的所述第二传导类型的通道增强区，所述通道增强区部分延伸进入所述通道区的下部从而降低所述通道区的电阻；
置于所述栅沟槽中的至少一个导电保护电极；以及
将所述至少一个导电保护电极与所述半导体区隔离开的保护电介质层，其中所述保护电介质层向外张开并且直接在所述主体区之下延伸。
8.根据权利要求7所述的场效应晶体管，还包括：
置于在所述至少一个导电保护电极之上但是与其隔离开的所述栅沟槽中的栅极；以及
将所述栅极与所述主体区隔离开的栅极电介质层。
9.一种形成场效应晶体管的方法，包括：
形成延伸到半导体区内第一深度的上沟槽部分；
用保护层材料内衬所述上沟槽部分的侧壁，使得所述半导体区沿着至少部分所述上沟槽部分的底部壁保持暴露；
形成穿过具有保护所述上沟槽部分的侧壁的所述保护层材料的所述上沟槽部分的暴露的底部壁的下沟槽部分，从而所述上沟槽部分的宽度大于所述下沟槽部分的宽度；
形成沿着所述下沟槽部分的侧壁和底部壁的保护电介质层，使得所述保护电介质层向外张开并且直接在第二传导类型的主体区之下延伸；
在所述下沟槽部分中形成保护电极； 
进行第一传导类型的杂质的成角的侧壁注入，以形成邻近所述上沟槽部分的通道增强区；
在所述半导体区中形成所述第二传导类型的所述主体区；以及
在所述主体区中形成所述第一传导类型的源极区，所述源极区以及所述主体区与所述半导体区之间的界面限定了它们之间的通道区，所述通道区沿着所述上沟槽部分侧壁延伸，
其中所述通道增强区部分延伸进入所述通道区的下部从而降低所述通道区的电阻。
10.根据权利要求9所述的方法，还包括形成在所述保护电极之上但是与其隔离开的栅极。
11.根据权利要求9所述的方法，进一步包括在所述保护电极上形成多晶硅层间介质体，其中所述通道增强区自对准所述多晶硅层间介质体。 
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