JP6950816B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP6950816B2 JP6950816B2 JP2020510158A JP2020510158A JP6950816B2 JP 6950816 B2 JP6950816 B2 JP 6950816B2 JP 2020510158 A JP2020510158 A JP 2020510158A JP 2020510158 A JP2020510158 A JP 2020510158A JP 6950816 B2 JP6950816 B2 JP 6950816B2
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- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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Description
本発明の第1の実施形態に係る半導体装置は、図1に示すように、主面に溝100が形成された基板10と、基板10にそれぞれ形成されたドリフト領域20、ウェル領域30、第1半導体領域40、第2半導体領域50を備える。
Na×Wp=Nd×Wn ・・・(1)
幅Wnと幅Wpは、n型ドリフト領域21とp型ドリフト領域22が繰り返し配列される方向の幅である。式(1)を満足するように、n型ドリフト領域21とp型ドリフト領域22の不純物濃度がそれぞれ設定される。
図15に示す第1の実施形態の変形例に係る半導体装置は、ドリフト領域20が溝100の底部のみに配置されている。つまり、溝100の第1の側面にドリフト領域20を配置していない点が、図1に示す半導体装置と異なる。
本発明の第2の実施形態に係る半導体装置は、図16に示すように、溝100の底部において、ドリフト領域20が、溝100の深さ方向に沿ってn型ドリフト領域21とp型ドリフト領域22を交互に積層した構造を有する。溝100の長手方向については、n型ドリフト領域21とp型ドリフト領域22を交互に配置した構造の第1の実施形態とは異なり、n型ドリフト領域21とp型ドリフト領域22のそれぞれは全面に連続的に配置されている。その他の構成については、図1に示した第1の実施形態と同様である。
本発明の第3の実施形態に係る半導体装置は、図19に示すように、ソース電極70とドレイン電極80の間に溝100の内部を埋め込んで配置された分離絶縁膜90に、溝100の第1の側面と並行に延在する分割溝900が形成されている。分割溝900によって、分離絶縁膜90のソース電極70とドレイン電極80で挟まれた部分が分割されている。つまり、図19に示した半導体装置は、分割溝900によってソース電極70とドレイン電極80との間で分離絶縁膜90が分離されている点が図1に示した半導体装置と異なる。その他の構成については、図1に示した第1の実施形態と同様である。
本発明の第4の実施形態に係る半導体装置は、図21に示すように、1つの溝100に第1〜第3の実施形態に係る半導体装置と同様の構成の2つの半導体装置が形成されている。
上記のように、本発明は実施形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。
20…ドリフト領域
21…n型ドリフト領域
22…p型ドリフト領域
30…ウェル領域
40…第1半導体領域
50…第2半導体領域
60…ゲート電極
65…ゲート絶縁膜
70…第1の主電極
80…第2の主電極
90…分離絶縁膜
Claims (10)
- 主面に溝が形成された基板と、
前記溝の底部に配置された部分を有する第1導電型のドリフト領域と、
前記ドリフト領域と接続して前記溝の一方の側面に配置された第2導電型のウェル領域と、
前記ドリフト領域と離間して、前記溝の前記側面において前記ウェル領域の表面に配置された第1導電型の第1半導体領域と、
前記溝の内部に前記ドリフト領域を介して前記ウェル領域と対向して配置された第1導電型の第2半導体領域と、
前記ウェル領域及び前記第1半導体領域のそれぞれの上面にまたがって開口部が形成されて前記溝の深さ方向に延伸するゲートトレンチの内部に配置され、前記ウェル領域と対向するゲート電極と
を備えることを特徴とする半導体装置。 - 前記ドリフト領域が、前記溝の前記側面から前記溝の底部に亘って連続的に配置され、
前記ウェル領域が、前記溝の前記側面で前記ドリフト領域の表面に配置されている
ことを特徴とする請求項1に記載の半導体装置。 - 前記基板が、絶縁性基板であることを特徴とする請求項1又は2に記載の半導体装置。
- 前記ドリフト領域の前記溝の底部に配置された部分が、前記側面の延伸する前記溝の長手方向に沿って第1導電型領域と第2導電型領域を交互に配置した構造を有することを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- 前記ドリフト領域の前記溝の底部に配置された部分が、前記溝の深さ方向に沿って第1導電型領域と第2導電型領域を積層した構造を有することを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- 前記第1半導体領域と第2半導体領域の間に流れる主電流が遮断されるオフ状態において、前記第1導電型領域と前記第2導電型領域の境界に形成されるpn接合から伸びる空乏層によって前記第1導電型領域と前記第2導電型領域が空乏化するように、前記第1導電型領域と前記第2導電型領域の不純物濃度が設定されていることを特徴とする請求項4又は5に記載の半導体装置。
- 前記溝の前記側面において前記第1半導体領域の表面に配置され、前記第1半導体領域と電気的に接続された第1の主電極と、
前記第1の主電極と対向して前記溝の内部に配置され、前記第2半導体領域と電気的に接続された第2の主電極と、
前記第1の主電極と前記第2の主電極の間に前記溝の内部を埋め込んで配置された分離絶縁膜と
を更に備え、
前記分離絶縁膜の前記第1の主電極と前記第2の主電極で挟まれた部分が、前記溝の前記側面と並行に延在する分割溝によって分割されていることを特徴とする請求項1乃至6のいずれか1項に記載の半導体装置。 - 基板の主面に溝を形成する工程と、
前記溝の底部に配置された部分を有する第1導電型のドリフト領域を形成する工程と、
前記ドリフト領域と接続させて、前記溝の一方の側面に第2導電型のウェル領域を形成する工程と、
前記ドリフト領域と離間させて、前記溝の前記側面において前記ウェル領域の表面に第1導電型の第1半導体領域を形成する工程と、
前記ドリフト領域を介して前記ウェル領域と対向させて、前記溝の内部に第1導電型の第2半導体領域を形成する工程と、
前記ウェル領域及び前記第1半導体領域のそれぞれの上面にまたがって開口部が形成されて前記溝の深さ方向に延伸するゲートトレンチを形成する工程と、
前記ゲートトレンチの内部に前記ウェル領域と対向するゲート電極を形成する工程と
を含み、
前記基板に不純物をイオン注入することにより前記ドリフト領域を形成することを特徴とする半導体装置の製造方法。 - 前記基板に不純物をイオン注入することにより、前記ウェル領域、前記第1半導体領域及び前記第2半導体領域を形成することを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記ドリフト領域を、前記溝の前記側面から前記溝の底部に亘って連続的に形成し、
前記ドリフト領域の前記溝の前記側面に形成される部分、前記溝の前記側面において前記ドリフト領域の表面に形成される前記ウェル領域、及び、前記ウェル領域の表面に形成される前記第1半導体領域を、前記溝の開口部から前記溝の前記側面に向けて斜めに不純物を打ち込むイオン注入により形成することを特徴とする請求項8又は9に記載の半導体装置の製造方法。
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