CN101971304A - 用于形成具有多个沟道的屏蔽栅沟槽fet的结构和方法 - Google Patents

用于形成具有多个沟道的屏蔽栅沟槽fet的结构和方法 Download PDF

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CN101971304A
CN101971304A CN2008801227424A CN200880122742A CN101971304A CN 101971304 A CN101971304 A CN 101971304A CN 2008801227424 A CN2008801227424 A CN 2008801227424A CN 200880122742 A CN200880122742 A CN 200880122742A CN 101971304 A CN101971304 A CN 101971304A
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潘南西
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Abstract

场效应晶体管(FET)包括一对延伸进入半导体区中的沟槽。每个沟槽包括位于沟槽底部中的第一屏蔽电极和位于沟槽上部的栅电极，该栅电极位于屏蔽电极的上方但与该屏蔽电极绝缘。第一导电类型的第一阱区和第二阱区在沟槽对之间半导体区中横向延伸并邻接该沟槽对的侧壁。该第一阱区和第二阱区通过第二导电类型的第一漂移区彼此垂直地隔开。栅电极和第一屏蔽电极相对于第一阱区和第二阱区设置，以使得当FET在导通状态下偏置时，在第一阱区和第二阱区的每一个中形成沟道。

Description

用于形成具有多个沟道的屏蔽栅沟槽FET的结构和方法
背景技术
本发明总体上涉及半导体技术，更具体地涉及沿着每个沟槽侧壁形成具有多个沟道的屏蔽栅沟槽FET的结构和方法。
屏蔽栅沟槽场效应晶体管(FET)比传统的FET更具优势，这是因为屏蔽电极减小了栅-漏电容(Cgd)并改善了晶体管的击穿电压而不牺牲晶体管导通电阻。图1是传统的屏蔽栅沟槽MOSFET100的简化截面图。N型外延层102在高度掺杂的n型衬底101上方延伸。衬底101作为漏极接触区。在p型阱区104中形成高度掺杂的n型源区108和高度掺杂的p型重本体区(heavy body region)106，而p型阱区104形成在外延层102中。沟槽110通过阱区104延伸并终止于由阱区104和衬底101所限定的外延层102的部分，其中该部分通常被称为漂移区。
沟槽110包括栅电极122下方的屏蔽电极114。栅电极122通过栅极电介质120与阱区104绝缘。屏蔽电极114通过屏蔽电介质115与漏区绝缘。栅电极112和屏蔽电极114通过极间电介质(IED)层116彼此绝缘。IED层116必需具有足够的质量和厚度以支持在在操作过程中存在于屏蔽电极114和栅电极122之间的电势差。介电帽124覆盖栅电极122并用于使栅电极122和顶侧互连层126绝缘。顶侧互连层126在该结构的上方延伸并使重本体区106和源区108电接触。
尽管栅电极122下的屏蔽电极114的绝缘提高了晶体管的某些性能特性(例如击穿电压和Cgd)，但是很难实现进一步改善这些或其他电学和结构特性(例如晶体管导通电阻Rdson和非钳位感应开关UIS特性)。这是由于用于提高FET某些电学特性的大多数已知技术通常会对其他电学特性造成不利影响或要求对处理技术进行重大改变。
因此，需要能够提高沟槽栅FET的各种电学特性而不损害其他电学特性的节约成本的技术。
发明内容
场效应晶体管(FET)包括一对延伸进入半导体区中的沟槽。每个沟槽包括位于沟槽下部第一屏蔽电极、和位于沟槽上部但与屏蔽电极绝缘的栅电极。第一导电类型的第一阱区和第二阱区横向延伸进入该沟槽对之间的半导体区并邻接该沟槽对的侧壁。第一阱区和第二阱区通过第二导电类型的第一漂移区垂直地彼此间隔。栅电极和第一屏蔽电极相对于第一阱区和第二阱区形成，从而当FET在导通状态下处于偏置(bias)时，在第一阱区和第二阱区的每一个中均形成沟道。
在一个实施方式中，当FET在导通状态下处于偏置时，沿着邻接第一阱区和第二阱区的每个沟槽侧壁的部分形成两个分离的沟道。
在另一个实施方式中，第一阱区与每个沟槽中的栅电极横向地直接相邻，并且第二阱区与每个沟槽中的第一屏蔽电极横向地直接相邻。
在另一个实施方式中，第一阱区位于第二阱区的上方。FET进一步包括在沟槽对之间的半导体区中横向延伸的第一导电类型的第三阱区。该第三阱区与邻接沟槽对的侧壁，并通过第二导电类型的第二漂移区与第二阱区垂直地隔开。
在另一个实施方式中，第一阱区位于第二阱区的上方。FET进一步包括在沟槽对之间的半导体区中横向延伸的第一导电类型的第三阱区。该第三阱区邻接该沟槽对的侧壁，并通过第二导电类型的第二漂移区与第二阱区垂直地隔开。第二屏蔽电极位于沟槽中，而沟槽位于第一屏蔽电极的下方。第一屏蔽电极和第二屏蔽电极彼此绝缘。
根据本发明的另一实施方式，形成FET的方法包括以下步骤。形成延伸进入第一导电类型的半导体区的一对沟槽。在每个沟槽的下部形成屏蔽电极。在每个沟槽的上部形成与屏蔽电极绝缘的栅电极。在该沟槽对之间的半导体区中形成第二导电类型的第一阱区和第二阱区，以使得该第一阱区和第二阱区垂直地彼此间隔，并横向地邻接于该沟槽对的侧壁。栅电极和第一屏蔽电极相对于第一阱区和第二阱区形成，从而当FET在导通状态下处于偏置时在每个第一阱区和第二阱区中均形成沟道。
在一个实施方式中，第一阱区与每个沟槽中的栅电极横向地直接相邻，并且第二阱区与每个沟槽中的第一屏蔽电极横向地直接相邻。
在另一实施方式中，该方法进一步包括以下步骤。形成衬于每个沟槽的下部侧壁和底部的屏蔽电介质。形成衬于每个沟槽的上部侧壁的栅极电介质。在每个沟槽的上部侧壁的侧面形成第二导电类型的源区。形成在第一阱区中延伸的第一导电类型的重本体区。
在另一个实施方式中，第一阱区在第二阱区上方延伸，并且第一阱区在第二阱区之前形成。
在另一个实施方式中，第一阱区在第二阱区上方延伸，该方法进一步包括在该沟槽对之间的半导体区中形成第一导电类型的第三阱区的步骤。该第三阱区邻接该沟槽对的侧壁并与第二阱区垂直地隔开。
结合附图以及本发明实施方式的如下具体描述，本发明的其他特征、特点和各种优点会变得更加明显。
附图说明
图1是传统的屏蔽栅MOSFET的简化截面图；
图2A是根据本发明的一种示例性实施方式的双沟道屏蔽栅MOSFET的简化截面图；
图2B是图2A中MOSFET的等效电路；
图3A-图3C是根据本发明的示例性实施方式的各种多沟道屏蔽栅沟槽MOSFET的简化截面图；
图4A-图4E是根据本发明的一种示例性实施方式的用于制造双沟道屏蔽栅沟槽FET的方法的简化截面图；
图5A-5F是根据本发明的一种示例性实施方式的用于制造双沟道屏蔽栅沟槽FET的另一种方法的简化截面图；
图6是示出了沿着双沟道屏蔽栅FET的深度的电场分布的仿真结果图；
图7是示出了每个传统的屏蔽栅FET和双沟道屏蔽栅FET的漏电流对漏电压的仿真结果图；
图8是示出了传统的屏蔽栅FET和双沟道屏蔽栅FET的栅-漏电荷Qgd对屏蔽电极上的电压的仿真结果图；和
图9是示出了传统的屏蔽栅FET对双沟道屏蔽栅FET的漏-源击穿电压BVdss的仿真结果图。
具体实施方式
根据本发明的实施方式，描述了沿着每个沟槽侧壁具有多个沟道的屏蔽栅沟槽FET及其制造方法。人们将会发现，这样的FET明显改善了现有技术中FET结构的某些性能特性而不会牺牲晶体管的其他性能特性。这些改善包括更高的BVdss、更低的Rdson、更低的栅电荷、和改善的UIS和突发击穿(snap back)特性。下面将参照图2A描述第一示例性实施方式。
图2A是根据本发明的一种示例性实施方式的双沟道屏蔽栅功率MOSFET的简化截面图。下漂移区210在半导体衬底205a上方延伸。下漂移区210和衬底205a都是n型的。p型屏蔽阱区215覆盖下漂移区210。n型导电性的上漂移区220覆盖屏蔽阱区215。p型导电性的栅极阱区225覆盖上漂移区220。
下漂移区210、屏蔽阱区215、上漂移区220和栅极阱区225形成半导体堆叠。沟槽230延伸通过该半导体堆叠在下漂移区210中终止。高度掺杂的n型源区245a在栅极阱区225和侧面的上部沟道侧壁中延伸。高度掺杂的p型重本体区249在相邻的源区245a之间的栅极阱区249中延伸。
沟槽230包括衬于沟槽230的下部侧壁和底部的屏蔽介电层242(例如，包含氧化层和氮化层中的一者或二者)。将屏蔽电极235a(例如，包含掺杂或未掺杂的多晶硅)置于在沟槽230的下部。屏蔽电极235a通过屏蔽电介质242与相邻的半导体区绝缘。在一个实施方式中，屏蔽电介质242的厚度范围为
Figure BPA00001168042500061
极间电介质238(例如，包含氧化物)在屏蔽电极235a上方横向延伸。栅极电介质244(例如，包含栅极氧化物)衬于上部沟槽侧壁。在一个实施方式中，栅极电介质244和IED 238具有相同的厚度。在另一实施方式中，IED 238比栅极电介质厚。将凹进式(或隐藏式，recessed)的栅电极240a(例如，包含掺杂或未掺杂的多晶硅)置于沟槽230上部的IED 238上方。顶侧的互连层248与源区245a和重本体区249电连接。背面的互连层202与衬底205a的底面电连接。在一个实施方式中，顶侧和背面的互连层248，202包含金属。
可以看到，屏蔽栅FET 200的结构在许多方面都与传统的屏蔽栅FET相同，除了在相邻于屏蔽电极235a的漂移区中嵌入了额外的阱区215。由于阱区215与屏蔽电极235a临近，因此这里的阱区215被称为“屏蔽阱区”，并且由于阱区225与栅电极240a临近，因此这里的阱区225被称为“栅极阱区”。屏蔽阱区215横向延伸台面区(mesa region)的全部宽度并邻接两个相邻沟槽的侧壁，从而将漂移区分为上漂移区220和下漂移区210。
在操作过程中，随着源区245a和漏区205a相对于合适的电压偏置，在将合适的正电压施加到每个栅电极240a和屏蔽电极235a后，沿着沟槽侧壁在栅极阱区225和屏蔽阱区215中分别形成沟道244和217。因此，在源区245a和漏区205a之间通过栅极阱区227、上漂移区220、屏蔽阱区215和下漂移区210形成电流通路。通过将屏蔽阱区215嵌入到与屏蔽电极235a直接相邻的漂移区中，实际上在漏区和源区之间形成了串联的两个晶体管。在图2B的等效电路图中有更清楚的描述。在图2B中，上方晶体管260的栅极端240b、下方晶体管270的屏蔽端235b、源极端245b、和漏极端205b分别对应于图2A中的栅电极240a、屏蔽电极235a、源区245a和漏区205a。
图3A-图3C是图2A中双沟道屏蔽栅FET的3个示例性变形的截面图。图3A中的FET 300a与图2A中的FET 200类似，除了将两个屏蔽阱区315a1，315a2而不是将一个屏蔽阱区嵌入到漂移区中。屏蔽阱区315a1，315a2均与屏蔽电极335a直接相邻，因此，当向屏蔽电极335a施加正电压使FET 300导通时，在每一个屏蔽阱区315a和315a2中形成沟道。因此，当FET 300a导通时，沿着每个沟槽侧壁总共形成三个沟道317a1，317a2，327。注意到，两个屏蔽阱区315a1、315a2将漂移区分为三个区：上漂移区320a、中漂移区313a、和下低漂移区310。
图3B中的FET 300b与图3A中的FET 300a相似，除了将两个屏蔽电极335b1，335b2而不是将一个屏蔽电极放置在沟槽330b中。每个屏蔽电极335b1和335b2具有相应的屏蔽阱区315b1和与之相邻的315b2。因此，为了在每个屏蔽阱区315b1和315b2中形成沟道，需要分别向每个屏蔽电极335b1和335b2施加合适的正电压。当屏蔽电极335b1和335b2显示为彼此绝缘时，它们能够在一个方向上延伸成为一块并且向上延伸和延伸到它们在其中能够电连接在一起的沟槽之外(While shield electrodes 335b1 and 335b2 areshown being insulated form one another，they can be extended in adimension into the page and routed up and out of the trench where theycan be electrically tied together)。可替代地，屏蔽电极335b1，335b2能够连接于两个不同的电压源。
图3C中的FET 300C与图2C中的FET 300b相似，除了将总共四个屏蔽阱区315c11，315c12，315c21，315c22嵌入到漂移区中，其中两个屏蔽阱区对应于两个屏蔽电极335c1，335c2中的一个。从而当将合适的正电压施加于3个电极340、335c2和335c1中的每一个以使FET 300C导通时，总共形成5个沟道317c11、317c12、317c21、317c22、327。从图3A-图3C的各种示例中可以看出，屏蔽电极和屏蔽阱区的各种组合和交换是可行的，并且本发明不限于这里所示出和描述的特定组合方式。
接下来，将描述与图2A相似的用于形成FET结构的两种示例性方法。对于本领域技术人员来说，通过阅读说明内容以修改这些方法从而得到图3A-图3C的FET结构变化或者屏蔽阱区和屏蔽电极的其他改变和组合是显而易见的。
图4A-图4E是根据本发明的一种示例性实施方式的用于形成双沟道屏蔽栅沟槽FET的方法的各阶段的截面图。在图4A中，利用公知技术在半导体衬底405上方形成外延区410a。外延区410a和半导体衬底405可掺杂有n型掺杂剂，例如砷或磷。在一个实施方式中，半导体衬底405的掺杂浓度范围为1×1019-1×1021cm-3，外延区410a的掺杂浓度范围为1×1018-1×1019cm-3。
在图4B中，利用公知的硅蚀刻技术在外延区410a中形成沟槽430。在一种可替代的实施方式中，对沟槽430进行较深的蚀刻以在衬底405中终止。在图4C中，使用常规技术形成沟槽430中的各种区和层。使用诸如氮化硅的化学气相沉积(CVD)、CVD氧化物、或硅的热氧化等公知技术形成衬于沟槽430的下部侧壁和底部的屏蔽电介质442(例如，包含氧化层和氮化层中的一者或二者)。通过使用诸如常规的多晶硅沉积和凹蚀技术在每个沟槽430的下部中形成屏蔽电极435(例如，包含掺杂或未掺杂的多晶硅)。
例如，利用例如常规的热氧化和/或氧化物沉积技术在屏蔽电极435上方形成IED 438(例如，包含热氧化物和/或沉积的氧化物)。可利用公知的热氧化方法形成衬于上部沟槽侧壁的栅极电介质444(例如，包含氧化物)。可利用该例如常规的多晶硅沉积和蚀凹方法在IED 438上方形成凹进的栅电极440。其中IED 438比栅极电介质444厚，在一种可替代的实施方式中，它们可同时形成并具有相同的厚度。如果在沟槽430中形成额外的屏蔽电极(如图3B和图3C所示)，可将用于形成屏蔽电极和IED的上述工艺步骤重复所需的次数。
在图4D中，根据公知的技术通过注入和驱入p型掺杂剂以在外延层410a中形成第一p型阱区425(栅极阱区)。在一个实施方式中，栅极阱区425可掺杂有掺杂剂，例如浓度范围为1×1016-1×1018cm-3的硼。然后利用已知的技术进行p型掺杂剂的高能量注入，以形成深于与屏蔽电极435直接相邻的外延层410a的第二p型阱区415(屏蔽阱区)。在一个实施方式中，屏蔽阱区415可以掺杂有掺杂剂，例如浓度范围为1×1016-1×1018cm-3的硼。
需要仔细选择屏蔽阱区415的注入参数，以确保在处理完成时，屏蔽阱区415与屏蔽电极435适当地对齐，从而当屏蔽电极435在导通状态下偏置时能够在其中形成沟道。在每个沟槽中形成多个屏蔽电极的实施方式中，可实施具有不同注入能量的多次屏蔽阱注入以形成多个屏蔽阱区，其中每个屏蔽阱区与相应的屏蔽电极直接相临。注意到，用于形成屏蔽阱区415的注入是在栅极阱区425的注入之后进行的，这是为了避免在驱入(drive-in)栅极阱区425的过程中屏蔽阱区415发生向外扩散(或逸出，out-diffusion)。然而，当小心控制注入和驱入过程时，两次注入的顺序可以颠倒。
在图4E中，执行常规的源极注入以形成侧向延伸通过栅极阱区425的上部并邻接沟槽430的高度掺杂的n型区。因此，在处理过程中不需要注入掩膜层，至少是在芯片的有源区中。在一个实施方式中，在三次注入之前在栅电极440上方形成介电层。
利用公知的方法形成在栅电极440上方延伸并横向覆盖台面区相邻沟槽430的介电帽446(例如，包含BPSG)。因此，介电帽446在相邻沟槽之间的台面区的中部上方形成开口。实施常规的硅蚀刻以通过由介电帽446形成的开口形成n型区中的凹进部分。该凹进部分延伸至n型区的底表面下方并延伸至栅极阱区425中。因此，该凹进部分将n型区分成两个区域，从而形成源区445。
实施常规的重本体注入以通过该凹进部在本体区425中形成重本体区449。然后利用已知技术在该结构上方形成顶侧互连层448。顶侧互连层448延伸进入凹进部，与源区445和重本体区449电接触。在晶片的背面形成背面互连层402以与衬底405电接触。注意，在封闭单元(closed cell)或开放单元(open cell)构造中，图4E中的单元结构在芯片中通常多次重复。
图5A-图5F描述了根据本发明另一示例性实施方式的形成双沟道屏蔽栅沟槽FET的可替换方法。在图5A中，类似于图4A，利用公知技术在衬底505上方形成n型外延层510a。在图5B中，通过在n型外延层510a上方形成p型外延层或者通过将p型掺杂剂注入到n型外延层510a中以形成p型屏蔽阱区515，从而使外延层510a的上层转变为p型。屏蔽阱区515可以覆有一薄层掺杂有砷的外延层(未示出)，以在随后的加热周期中防止屏蔽阱区514中的掺杂剂向上扩散(up-diffusion)。
在图5C中，通过在屏蔽阱区510a上方形成n型外延层以形成n型漂移区520。在图5D中，利用常规技术形成延伸通过各种半导体层并在最底部的漂移区510b中终止的沟槽530。可替代地，沟槽530可以向更深处延伸以在衬底505中终止。在图5E中，可以类似于图4C中所描述的方式在沟槽530中形成屏蔽介电层442、屏蔽电极435、IED 438、栅极电介质444、和栅电极440，因此就不再进行描述。
接着，通过将p型掺杂剂注入到n型漂移区520中以形成p型栅极阱区525，从而使漂移区520的上层转变为p型。在图5F中，可以类似于图4E中所描述的方式形成介电帽546、源区545、重本体区549、顶侧互连层548和背面互连层502，因此就不再进行描述。
根据本发明的实施方式，沟槽中的一个或多个屏蔽电极可以多种不同的方式偏置。例如，一个或多个屏蔽电极可偏置为恒定的正电压、可连接到栅电极(从而屏蔽电极和栅电极可以一起开关)、或可连接到独立于栅电压的开关电压。用于偏置一个或多个屏蔽电极的方法可由外部提供或者由内部产生，例如，由可获得的电压提供。在屏蔽电极的偏置与栅电极偏置无关的实施方式中，可在优化FET的各种结构和电学特性方面获得一些灵活性。
在栅电极在20V(导通)和0V(断开)之间进行切换的一个实施方式中，屏蔽电极在20V(导通)和10V(断开)之间进行切换。这将横跨IED 238(图2A)的最大电压限制为10V，从而允许形成相对薄的IED。该实施方式的仿真结果表明Rdson有45％的提高，BVdss为大约30V，并且实质上低的栅电荷Qg。在栅电极240a在20V(导通)和0V(断开)之间进行切换的另一实施方式中，屏蔽电极235a在导通和断开状态都偏置为20V。该实施方式的仿真结果表明Rdson有25％的提高，BVdss为大约30V，和实质上低的Qg。
因此，将期望的操作电压施加于栅电极240a和屏蔽电极235a以确定IED 238的厚度和质量。在横跨IED 238(图2A)的电压差较小的实施方式中，可形成薄的IED 238，这能够有利地形成薄的上漂移区220，从而获得较低的Rdson。通过沿着每个沟槽侧壁形成第二沟道可进一步降低Rdson。参照图6-图9的仿真结果可更全面地描述本发明的各种实施方式的这些和其他优点和特点。
图6是示出了沿着双沟道屏蔽栅FET 600的深度描述电场分布的仿真结果图。如图所示，两个电场的峰值分别出现在对应于由每个阱区625和615以及它们下面的漂移区620和604所形成的pn结的位置617和627处。相反，在诸如图1中的FET 100的传统单沟道屏蔽栅FET中，在阱区104和其下面的漂移区之间的pn结处仅出现一个峰值。因此，双沟道FET结构600有利地增加了电场曲线下方的区域，这使晶体管的击穿电压增加。可以看到，在漂移区中嵌入额外的屏蔽阱区后，电场分布中会出现另外的峰值，从而使晶体管的击穿电压进一步增加。击穿电压的提高能够使漂移区604和620的掺杂浓度增加，从而降低Rdson。也就是说，对于与现有技术的FET相同的击穿电压，能够获得更高的Rdson。
图7是示出了描述对于每个传统屏蔽栅FET(标记为“对照”的曲线610)和双沟道栅FET(标记为“改进”的曲线720)的漏电流对漏电压的仿真结果。可以容易地观察到，通过双沟道屏蔽栅FET实现了漏电流的显著增加。
在传统的屏蔽栅FET中，微量掺杂的漂移区中的耗尽电荷对Qgd有很大的贡献。然而，在根据本发明的多沟道屏蔽栅FET中，由于多个漂移区中的正电荷被其相邻的多个阱区中的负电荷补偿，因此漂移区中电荷对Qgd的影响会显著减小。图8是示出了每个传统的屏蔽栅FET(曲线810)对双沟道屏蔽栅FET(曲线820)的栅-漏电荷Qgd对屏蔽电极的电压的仿真结果图。施加于屏蔽电极235a(图2A)的偏置电压的变化范围是约6-20V，并测量Qgd。很明显，通过双沟道屏蔽栅FET可实现栅-漏极电容Cgd的显著下降(在低屏蔽偏置时下降约40％)。
图9是示出了每个传统的屏蔽栅FET(曲线910)和双沟道屏蔽栅FET(曲线920)的漏-源极穿电压BVdss的另一个仿真结果图。可以看到，通过双沟道屏蔽栅FET可实现BVdss的显著增加。这在调整沟槽中各介电层的厚度以改善FET的其他特性方面提供了另外的灵活性。
多阱屏蔽栅FET的另一个特性是改善的UIS和突发击穿特性。多个阱区导致形成多个背靠背连接的pn二极管，其功能类似于公知的多环齐纳结构，从而提供优异的UIS和突发击穿特性。
因此，正如所看到的，通过对制造工艺进行相对较小的改变(例如，增加屏蔽阱注入)，根据本发明实施方式的多沟道屏蔽栅FET提高了晶体管的各种性能特性，并不对其他特性产生影响。如上文所述，能够实现包括低Rdson、低栅电荷、高BVdss、以及改善的提高的UIS和突发击穿特性。
虽然上文中提供了本发明的各种实施方式的完整说明，但是可以进行许多替换、修改和等同替代。例如，在本发明的各实施方式中已描述的n-沟道屏蔽栅MOSFET，但是本发明不局限于这样的FET。例如，可以仅通过转换各种半导体区的导电类型来形成本文中示出和描述的各种屏蔽栅MOSFET的p沟道对应物(counterpart)。又例如，可以仅通过转换衬底的导电类型来形成本文中描述的MOSFET的n-沟道IGBT对应物，以及仅通过转换除衬底之外的各种半导体区的导电类型来形成p-沟道IGBT对应物。此外，尽管在示例性实施方式一般使用注入的方式以形成掺杂区，本领域技术人员会认识到用于形成掺杂区的其他方式(诸如扩散)可以替换或与本文中描述的注入步骤相结合。因此，上文的描述不应被用于限制本发明的范围，本发明范围由所附的权利要求所限定。

Claims (28)

1.一种场效应晶体管(FET)，包含：
延伸进入半导体区的一对沟槽；
第一屏蔽电极，位于每个沟槽的下部中；
栅电极，位于每个沟槽的上部中，所述栅电极位于所述屏蔽电极上方但通过极间电介质与所述屏蔽电极绝缘；和
第一导电类型的第一阱区和第二阱区，其在所述沟槽对之间的所述半导体区中横向延伸，所述第一阱区和第二阱区邻接所述沟槽对的侧壁，所述第一阱区和第二阱区通过第二导电类型的第一漂移区垂直地彼此间隔，
其中，所述栅电极和所述第一屏蔽电极相对于所述第一阱区和第二阱区设置，以使得当所述FET在导通状态下偏置时，在所述第一阱区和第二阱区的每一个中形成沟道。
2.根据权利要求1所述的FET，其中，当所述FET在导通状态下偏置时，沿着邻接所述第一阱区和第二阱区的每个沟槽侧壁的部分形成两个分离的沟道。
3.根据权利要求1所述的FET，其中，所述第一阱区与每个沟槽中的所述栅电极横向地直接相邻，并且所述第二阱区与每个沟槽中的所述第一屏蔽电极横向地直接相邻。
4.根据权利要求1所述的FET，进一步包含：
屏蔽电介质，衬于每个沟槽的下部侧壁和底部；
栅极电介质，衬于每个沟槽的上部侧壁；
所述第二导电类型的源区，位于每个沟槽的上部侧壁的侧面；和
所述第一导电类型的重本体区，其在所述第一阱区中延伸。
5.根据权利要求1所述的FET，其中，所述第一阱区位于所述第二阱区的上方，所述FET进一步包含在所述沟槽对之间的半导体区中横向延伸的第一导电类型的第三阱区，所述第三阱区邻接所述沟槽对的侧壁，所述第三阱区通过所述第二导电类型的第二漂移区与所述第二阱区垂直地隔开。
6.根据权利要求5所述的FET，其中，所述栅电极和所述第一屏蔽电极相对于所述第一阱区、第二阱区和第三阱区设置，以使得当所述FET在导通状态下偏置时，在所述第一阱区、第二阱区和第三阱区的每一个中形成沟道。
7.根据权利要求5所述的FET，其中，当所述FET在导通状态下偏置时，沿着邻接所述第一阱区、第二阱区和第三阱区的每个沟槽侧壁的部分形成三个分离的沟道。
8.根据权利要求5所述的FET，其中，所述第一阱区与每个沟槽中的所述栅电极横向地直接相邻，并且所述第二阱区和第三阱区与每个沟槽中的所述第一屏蔽电极横向地直接相邻。
9.根据权利要求1所述的FET，其中，所述第一阱区位于第二阱区的上方，所述FET进一步包含：
所述第一导电类型的第三阱区，其在所述沟槽对之间的所述半导体区中横向延伸，所述第三阱区邻接所述沟槽对的侧壁，所述第三阱区通过所述第二导电类型的第二漂移区与所述第二阱区垂直地隔开；和
所述沟槽中的第二屏蔽电极，其位于所述第一屏蔽电极的下方，所述第一屏蔽电极和第二屏蔽电极彼此绝缘。
10.根据权利要求9所述的FET，其中，所述栅电极、所述第一屏蔽电极和所述第二屏蔽电极相对于所述第一阱区、第二阱区和第三阱区设置，以使得当所述FET在导通状态下偏置时，在所述第一阱区、第二阱区和第三阱区的每一个中形成沟道。
11.根据权利要求9所述的FET，其中，当所述FET在导通状态下偏置时，沿着邻接所述第一阱区、第二阱区和第三阱区的每个沟槽侧壁的部分形成三个分离的沟道。
12.根据权利要求9所述的FET，其中，所述第一阱区与每个沟槽中的所述栅电极横向地直接相邻，所述第二阱区与每个沟槽中的所述第一屏蔽电极横向地直接相邻，并且所述第三阱区与每个沟槽中的所述第二屏蔽电极横向地直接相邻。
13.一种场效应晶体管(FET)，包含：
堆叠，所述堆叠从上至下包括第一导电类型的第一阱区、第二导电类型的第一漂移区、第一导电类型的第二阱区、和第二导电类型的第二漂移区，所述堆叠在两个沟槽之间横向延伸并邻接两个沟槽的侧壁，每个沟槽具有从上至下包括通过极间电介质彼此绝缘的栅电极和第一屏蔽电极的堆叠，
其中，所述栅电极和所述第一屏蔽电极相对于所述第一阱区和第二阱区设置，从而当所述FET在导通状态下偏置时，在所述第一阱区和第二阱区的每一个中形成沟道。
14.根据权利要求13所述的FET，其中，当所述FET在导通状态下偏置时，沿着邻接所述第一阱区和第二阱区的每个沟槽侧壁的部分形成两个分离的沟道。
15.根据权利要求13所述的FET，其中，所述第一阱区与每个沟槽中的所述栅电极横向地直接相邻，并且所述第二阱区与每个沟槽中的所述第一屏蔽电极横向地直接相邻。
16.根据权利要求13所述的FET，进一步包含：
屏蔽电介质，衬于每个沟槽的下部侧壁和底部；
栅极电介质，衬于每个沟槽的上部侧壁；
所述第二导电类型的源区，位于每个沟槽的上部侧壁的侧面；和
所述第一导电类型的重本体区，其在所述第一阱区中延伸。
17.根据权利要求13所述的FET，进一步包含所述第一导电类型的第三阱区，所述第三阱区在两个所述沟槽之间横向延伸并邻接两个所述沟槽，所述第三阱区在所述第二漂移区下方延伸。
18.根据权利要求17所述的FET，其中，当所述FET在导通状态下偏置时，沿着邻接所述第一阱区、第二阱区和第三阱区的每个沟槽侧壁的部分形成三个分离的沟道。
19.根据权利要求17所述的FET，其中，所述第一阱区与每个沟槽中的所述栅电极横向地直接相邻，并且所述第二阱区和第三阱区与每个沟槽中的所述第一屏蔽电极横向地直接相邻。
20.根据权利要求13所述的FET，进一步包含：
所述第一导电类型的第三阱区，其在两个所述沟槽之间横向延伸并邻接两个所述沟槽，所述第三阱区在所述第二漂移区的下方延伸；和
第二屏蔽电极，位于所述第一屏蔽电极下方的沟槽中，所述第一屏蔽电极和第二屏蔽电极彼此绝缘。
21.根据权利要求20所述的FET，其中，当所述FET在导通状态下偏置时，沿着邻接所述第一阱区、第二阱区和第三阱区的每个沟槽侧壁的部分形成三个分离的沟道。
22.根据权利要求20所述的FET，其中，所述第一阱区与每个沟槽中的所述栅电极横向地直接相邻，所述第二阱区与每个沟槽中的所述第一屏蔽电极横向地直接相邻，并且所述第三阱区与每个沟槽中的所述第二屏蔽电极横向地直接相邻。
23.一种形成场效应晶体管(FET)的方法，该方法包括：
形成延伸进入第一导电类型的半导体区的一对沟槽；
在每个沟槽的下部中形成屏蔽电极；
在每个沟槽的上部中形成栅电极，所述栅电极位于所述屏蔽电极上方并与所述屏蔽电极绝缘；和
在所述沟槽对之间的所述半导体区中形成第二导电类型的第一阱区和第二阱区，以使得所述第一阱区和第二阱区垂直地彼此间隔，并且横向地邻接所述沟槽对的侧壁，
其中，所述栅电极和所述第一屏蔽电极相对于所述第一阱区和第二阱区设置，从而当所述FET在导通状态下偏置时，在第一阱区和第二阱区的每一个中形成沟道。
24.根据权利要求23所述的方法，其中，所述第一阱区与每个沟槽中的所述栅电极横向地直接相邻，并且所述第二阱区与每个沟槽中的所述第一屏蔽电极横向地直接相邻。
25.根据权利要求23所述的方法，进一步包括：
形成衬于每个沟槽的下部侧壁和底部的屏蔽电介质；
形成衬于每个沟槽的上部侧壁的栅极电介质；
形成位于每个沟槽的上部侧壁侧面的所述第二导电类型的源区；和
形成在所述第一阱区中延伸的所述第一导电类型的重本体区。
26.根据权利要求23所述的方法，其中，所述第一阱区在所述第二阱区上方延伸，并且第一阱区在所述第二阱区之前形成。
27.根据权利要求26所述的方法，其中，所述第一阱区在所述第二阱区上方延伸，所述方法进一步包括：
在所述沟槽对之间的所述半导体区中形成所述第一导电类型的第三阱区，所述第三阱区邻接所述沟槽对的侧壁，并且所述第三阱区与第二阱区垂直地隔开。
28.根据权利要求27所述的方法，其中，所述第一阱区与每个沟槽中的所述栅电极横向地直接相邻，并且所述第二阱区和第三阱区与每个沟槽中的所述第一屏蔽电极横向地直接相邻。
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US20100258866A1 (en) 2010-10-14
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US20090166728A1 (en) 2009-07-02

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