TW201240016A - Manufacturing method of semiconductor substrate - Google Patents

Manufacturing method of semiconductor substrate Download PDF

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Publication number
TW201240016A
TW201240016A TW100110345A TW100110345A TW201240016A TW 201240016 A TW201240016 A TW 201240016A TW 100110345 A TW100110345 A TW 100110345A TW 100110345 A TW100110345 A TW 100110345A TW 201240016 A TW201240016 A TW 201240016A
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TW
Taiwan
Prior art keywords
layer
semiconductor substrate
filling
layers
epitaxial
Prior art date
Application number
TW100110345A
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Chinese (zh)
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TWI478279B (en
Inventor
yong-zhong Li
Zong-Ming Pan
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Taiwan Semiconductor Co Ltd
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Publication date
Application filed by Taiwan Semiconductor Co Ltd filed Critical Taiwan Semiconductor Co Ltd
Priority to TW100110345A priority Critical patent/TW201240016A/en
Publication of TW201240016A publication Critical patent/TW201240016A/en
Application granted granted Critical
Publication of TWI478279B publication Critical patent/TWI478279B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66143—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Composite Materials (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

A manufacturing method of semiconductor substrate is disclosed. A plurality of layers of epitaxial layers is stacked up and down on a substrate. A plurality of trenches is formed respectively on each layer of epitaxial layer by the trench forming process. High concentration doped layer is formed for sidewall of each trench by the tilt angle implantation (imp) process, and then inner side of high concentration doped layer is filled with the packed layer for filling the packed layer of oxide or polysilicon before the planarization process treatment. High concentration doped layer is stacked up and down in trenches between each epitaxial layer for forming super junction. Each packed layer is stacked up and down for incorporating as one body. A top layer epitaxial layer is stacked on top of the stacked epitaxial layer for manufacturing a semiconductor substrate. Semiconductor substrate formed in this manufacturing method can be the base material of metal-oxide semiconductor field-effect transistor with the super junction trench or the Schottky diode with the metal junction.

Description

201240016 六、發明說明： 【發明所屬之技術領域】 曰本發明係關於一種半導體基材之製備方法，尤指一種以複數層蟲 明上、下堆疊兩濃度摻雜層之溝槽邊牆，所形成之半導體基材之製備 【先前技術】 按’習知之金氧半場效電晶體或蕭特基二極體等半導體，為廣被 利用之半導體元件’諸如中華專利公報第132瞻號「半導體元件 及互補式金氧半場效電晶體」發明專利案、第肋柳號「溝渠式功率 半導體裝置及其製法」發明專繼、中國專· ZL_i443號「溝槽 =基整流器」發明專利案、第几0281〇57〇2號「雙掩模溝槽肖特基整 ^器及其製造方法」發明專利案與美國發明專利第⑷⑽號「 SCHOTTKY DIODE WITH DIELECTRIC TRENCHJ^a^#lJt , 典型之溝渠型的金氧半場效電晶體婦特基二極體等料體結構，該 習知之溝渠型的金氧半場效電晶體結構或f特基二極體，由於該溝渠 於順向偏壓時均存有順向阻抗偏高、逆向偏壓值偏低與高逆 缺點’並沒有明顯改善之成效，致使該金氧半 日…蕭特基一極體因溫昇、逆向偏壓值或逆向漏電流之限 【發明内容】 遙曰知2氧料效電晶體或蕭特基二極體等半導體中之溝渠 積弊問題無點，致《適綠高辨或高電壓之操作^電政 其步Π括本發敗轉目的，餘提供—辭導縣狀製備方法， 201240016 (C^f邊牆軸高濃度摻騎，在步驟B之各溝射以傾斜角度注入 離子丄於該溝槽邊牆以傾斜角度注人高漠度換雜離子半導體材料， 形成南漢度摻雜層於溝槽邊牆； (D) 真充層填充於步驟c中之高濃度接雜層内側填充氧化物或多晶 之填充層； (E) 平坦化纽，將步驟D之填充層表面進行平坦化處理； (^复數層蟲晶層堆疊處理，在步驟A2下縣晶層上方，社、下堆 疊方式，堆疊複數層之蟲晶層，並於每一層蟲晶層逐一實施相同於 步驟B之溝卿成、步驟C之溝槽邊牆形成高濃度摻雜層、步驟D 氧化物^與轉E平坦域理等步驟，使每_滅晶層内均形成 溝槽、南濃度摻雜層與填充層填充於高濃度摻雜層内側，並讓下層 遙晶層與各蟲晶層之溝槽、高濃度摻雜層與填充層均呈上、下堆^ 連結為-體，該高濃度摻雜層並堆疊結合形成超級接面。 儿 (G)製備，成-複數層蟲晶堆疊之半導體基材，藉由步驟f之各層蟲晶 層堆疊組合形成一複數層磊晶堆疊之半導體基材。 本發明之半導體歸之製備方法之功效，係在㈣賴複數層之 蟲晶層上、下堆疊組合，以及，各“層中之溝槽之高濃度摻靜上、 下堆疊組合’形成-體之超級接面結構，使該金屬氧化铸體場效應 電晶體或蕭縣二極體科導體，在顧本發方法製備之半導體基材^ 可具備有較低之順向電阻值、高逆向偏壓與低逆向漏電流特性，而具’ 有财高壓與低鋪之功效’細使該金屬氧化半導_效應電晶體或 蕭特基二極體可應用於高功率與高電壓操作場合。 〆 【實施方式】 ' ° 請參閱第-圖〜第十AD所示，第—圖為本發明之半導體 製備方法流程圖’其步驟包括步驟1〇〜7〇，其中： UU)下層伽層堆疊’如第一圃所不，係在一祕上，堆疊一下層 磊晶層205，該基材200在本發明中係以N+半導體材料: 磊晶層205為N-磊晶； ’、.、’、列’ s玄 (20)溝槽形成，如第三圖所示’在步驟1〇之為晶層2〇5内形成複數莫 201240016 槽 210 ; (30)溝槽邊牆形成高濃度摻雜層，如第三圖所示，在步驟2()之各溝槽 210中以傾斜角度注入離子，於該溝槽21〇邊牆以傾斜角度注入^ 濃度摻雜離子半導體材料，形成高濃度摻雜層21S於溝槽2ι〇邊牆 上，該高濃度摻雜層215為P型摻雜半導體構成； (40)填充層填充’如第四圖所*，於步驟3〇中之高濃度摻雜層215内 側填充填充層220，該填充層220為氧化物或多晶矽； (50)平坦化處理’如第四圖所示，將步驟4〇之填充層22〇表面進行平 坦化處理； (60)複數層Jaa層堆疊處理，如第五圖〜第十a圖在步驟1〇之下層蟲 晶層210上方，以上、下堆疊方式，堆疊複數層之磊晶層3〇〇，該 磊晶層300為N-磊晶，並於每一層磊晶層3⑻逐一實施相同於步 驟20之溝槽形成、步驟3〇之溝槽邊牆形成高濃度摻雜層、步驟 40氧化物填充與步驟50之平坦化處理等步驟，使每一個磊晶層3〇〇 内均形成溝槽305、高濃度摻雜層31〇，以及填充層315填充於高 濃度摻雜層310内侧，該高濃度摻雜層31〇為p型摻雜半導體構 成，該填充層315為氧化物或多晶矽，並讓下層磊晶層21〇與各磊 晶層300之溝槽210及305、高濃度摻雜層215及310，與填充層 220及315均呈上、下堆疊連結為一體，該高濃度摻雜層21〇及31〇 並堆疊結合形成超級接面’上述之磊晶層3〇〇之層數並不限於上述 之二層為限，且該下層磊晶層21〇與各磊晶層300之溝槽21〇及 305、高濃度摻雜層215及310間之寬度、高度或形狀並不限制一 定相同。 (70)製備形成一複數層磊晶堆疊之半導體基材，藉由步驟6〇之各層磊 晶層300堆疊組合形成一如第十A圖所示之複數層磊晶堆疊之半 導體基材400。 請參閱第十B圖所示，為依本發明之第一圖之步驟1〇〜7〇所示之 製備方法所製備之半導體基材400之第二實施例，其中，顯示該下層 磊晶層210與各磊晶層300之溝槽210及305間之寬度，由下而上逐 201240016 步遞增加寬，而使該下層磊晶層210與各磊晶層300之溝槽210及305、 高濃度摻雜層215及310、填充層220及315共同上、下堆疊連結形成 如螺絲狀之形狀，但其上、下堆疊形狀亦不限於第十圖A及第十圖B 所示者為限。 請再配合第十c圖所示’為依本發明之第一圖之步驟10〜7〇所示 之製備方法所製備之半導體基材400之第三實施例，其中，顯示該下 層磊晶層210與各磊晶層300之溝槽210及305形狀皆為上寬下窄之 梯形形狀，同樣可讓該下層磊晶層210與各磊晶層300之溝槽21〇及 3〇5而濃度推雜層215及310、填充層220及315共同上、下堆疊連 結。 請再配合第十一圖、第十二圖所示，為上述本發明之半導體基材 之製備方法所製備之半導體基材4〇〇之應用例，其中，係列舉應用於 —金屬氧化半導體場效應電晶體500(如第十二圖所示)作為製造時之半 導體基礎材料之狀態，如第十一圖所示，在如圖十A所示之半導體基 材400中之最上層蟲晶層3〇〇之上方結合一頂層遙晶層，該頂層 磊晶層400A為N-磊晶，該頂層磊晶層4〇〇A中形成一埋入層41〇與^ 曰420及埋入層41〇下方與半導體基材4⑻之最上層之磊晶層3⑻之 溝槽305邊牆形成之高濃度摻雜層310與填充層315頂面結合，該基 層20並、、σ於5亥埋入層上方，該埋入層41〇為p型半導體材料， 該基層420為ρ型半導體材料，該基層42〇頂面並形成一接面似。 如第十一圖所示，將複數源極與閘極電極分別透過—氧 化層接面450結合於該頂層蟲晶層侧Α頂面，以及，基層42〇頂面與 該NPN接面似之間，使該半導體基材侧之基材形成沒極電^ 藉以=成具超級接面溝槽之金屬氧化半導體場效應電晶體獅。 ^再配合第十三_示’為上述第十-圖及第十二®巾應用本發 ^之’備方法製備之半導體基材4⑻之金屬氧化物半導體場效應電晶 =500’與習知金屬氧化半導體場效應電晶體間之逆向偏壓狀態之實驗 、線圖’其中，橫向轴為祕電壓DV，其單位為伏特，縱向轴為源_ 及極門之逆向漏電流，其單位為安培，曲線&代表本發明之金屬氧化 201240016 _的實驗曲線’曲線82表示習知金屬氧化半導 %效應電Ba體之實驗曲線，由該曲線S1與曲線s2相為比對下，可 出本發明製傷方法所製備之半導體基材4⑻應用於金屬氧化半 %效應電，體5〇〇上，確具備有高逆向偏壓與低逆向漏電流之特 ，且該金屬氧化半導體場效應電晶體5〇〇如欲得到更好的逆向偏壓 =!·生可以由該半導體基材4〇〇透過上述步驟6〇之複數層纟晶層堆疊 處理步驟中之蟲晶層堆疊層數增加而達成。 ^再參閱第十四_示，為上述針―®及第忙圖中應用本發 明之製備方法製備之半導體基材伽之金屬氧化物半導體場效應電晶 體5〇〇與1知金屬氧化半導體場效應電晶體間在順向偏壓狀態之實驗 曲線圖，其中’橫向軸為_電壓GV，其單位為伏特，縱向軸為沒極 電流DA，其單位為安培，曲線％代表本發明之金屬氧化半導體場效 應電晶，500的實驗曲線，曲線％表示習知金屬氧化半導體場效應電 晶體之實驗曲線’由該曲線S3與曲線以相為比對下，可明顯看出可 明顯看出本發明製備方法所製備之半導體基材棚應用於金屬氧化 導體场效應f晶體5GG上’具備有侧向電贿之特性。 ，上述料三®及第十四圖之實驗結果，同理可於本發明本發明之 製備方法製備之轉縣材_應驗具溝猶構之金屬接面之蕭特 基-極體時’亦可得朗樣的軸雜值低、逆向驗高與逆向漏 流低之實驗結果。 綜上所述’本發明之半導體基材之製備方法所列舉之各圖式及說 明，係為便於說明本發明之技術内容，關舉之實關之—隅，並非 用以限制本發明之料，舉凡是針對本發明之步驟、程序或元件的等 效變更與置換’當屬本發明之範嘴，其範圍將由以下的申請專利範 來界定之。 【圖式簡單說明】 第一圖為本發明之半導體基材之製備方法之流程圖； *第二圖為-剖視圖，顯示本發明方法中之下層蟲晶層堆疊於基材之狀 態； 201240016 第二圖為—剖視圖’顯示本發明方法中之下層蟲晶層之溝 彡成高濃麟雜狀狀態； g ^ 與平坦化 第四圖為一剖視圖，顯示本發明方法令之下層磊晶層 處理之狀態； 具兄 層磊晶層 第五圖為一剖視圖，顯示本發明方法中之下層磊晶層之 堆疊之狀態； — •第六圖為一剖視圖，顯示本發明方法中之下層磊晶層之第一層磊晶層 之溝槽形錢溝槽舰臟冑濃度雜層之狀態； aa曰 第七圖為一剖視圖，顯示本發明方法中之下層遙晶層之第 之填充與平垣化處理之狀態； 日曰 μ第八圖為一剖棚，顯示本發明方法中之下層遙晶層之第二層蟲晶層 堆疊之狀態； 第九圖為-剖視圖，顯示本發明方法中之下層蟲晶層之第 之溝槽形成與溝槽邊牆形成高濃度摻雜層之狀態； 曰 第十Α圖為一剖視圖’顯示本發明方法中之下層磊晶層之第二層磊晶 層之填充與平坦化處理後形成製備半導體基材之狀態； 第十B圖為本發明方法中之製備半導體基材之第二實施例圖； 第十C圖為本發明方法中之製備半導體基材之第三實施例圖·， 第十-圖為-规®，顯示本發明方法製備之半導體基材顧於金屬氧 化半導體場效應電晶體之製造過程之應用例； 第十二圖為應用本發明方法製備之半導體基材，所製成之金屬氧化半導 體場效應電晶體剖面圖； β第十二圖為顧本發明方法製備之半導體基材所製成之金屬氧化半導 體場效應電晶體，於逆向偏壓狀態下之實驗曲線圖； 第十四圖為應用本發明方法製備之半導體基材，所製成之金屬氧化半 導體場效應電晶體，於順向偏壓狀態下之實驗曲線圖。 【主要元件符號說明】 10 下層磊晶層堆疊 20 溝槽形成 201240016 30 溝槽邊牆形成高濃度摻雜層 40 填充層填充 50 平坦化處理 60 複數層磊晶層堆疊處理 70 製備形成一複數層磊晶堆疊之半導體基材 200 基材 205 遙晶層 210 溝槽 215 高濃度摻雜層 220 填充層 300 磊晶層 305 溝槽 310 高濃度摻雜層 315 填充層 400A頂層磊晶層 410 埋入層 420 基層 421 NPN接面 430 源極 440 閘極 450 氧化層接面 400 半導體基材 500 金屬氧化物半導體場效應電晶體201240016 VI. Description of the Invention: [Technical Field] The present invention relates to a method for preparing a semiconductor substrate, and more particularly to a trench sidewall with two layers of doped layers stacked on top and bottom of a plurality of layers of insects. Preparation of a semiconductor substrate to be formed [Prior Art] A semiconductor element such as a conventional gold oxide half field effect transistor or a Schottky diode is widely used. For example, the Chinese Patent Publication No. 132 And the complementary type of gold-oxygen half-field effect transistor" invention patent case, the rib willow "ditch type power semiconductor device and its manufacturing method" invention, China ZL_i443 "groove = base rectifier" invention patent case, the first few 0281〇57〇2 "Double mask trench Schottky device and its manufacturing method" invention patent case and US invention patent (4) (10) "SCHOTTKY DIODE WITH DIELECTRIC TRENCHJ^a^#lJt, typical ditch type a gold-oxygen half-field effect transistor, such as a female body diode structure, such a trench type of gold oxide half field effect transistor structure or f-te diode, because the trench is biased in the forward direction There are high forward impedance, low reverse bias value and high reverse defect', and there is no obvious improvement effect, resulting in the half-day of the golden oxygen... Schottky's one body due to temperature rise, reverse bias or reverse leakage Limit of current [Invention content] There is no problem in the problem of the ditches in semiconductors such as 2 oxygen-effect transistors or Schottky diodes, which leads to the operation of "high green or high voltage" Including the purpose of the defeat, the remainder provides - the method of preparation of the county, 201240016 (C ^ f side wall axis high concentration of riding, in each step of step B injection of ions at an oblique angle to the side wall of the trench The tilt angle is injecting high-intensity into the hetero-ion semiconductor material to form a south-doped doped layer on the trench sidewall; (D) the true-charge layer is filled in the high-concentration impurity layer in step c to fill the oxide or polycrystal (E) flattening the new layer, planarizing the surface of the filling layer of step D; (^ multiple layers of insect layer stacking treatment, above the county layer under step A2, community, lower stacking mode, stacking plural Layer of worm layer, and in each layer of worm layer one by one is the same as step B Qing Cheng, the groove side wall of step C forms a high concentration doped layer, the step D oxide ^ and the E flat domain theory, so that each of the _ crystal layer is formed with a trench, a south concentration doping layer and filling The layer is filled inside the high-concentration doped layer, and the lower telecrystal layer and the groove of each insect layer, the high-concentration doped layer and the filling layer are connected to the upper and lower layers, and the high concentration is doped. The layers are stacked and stacked to form a super junction. The (G) is prepared as a semiconductor substrate of a plurality of layers of insect crystals, and a plurality of layers of epitaxially stacked semiconductor substrates are formed by stacking the layers of the layers of the layers of the layer f. The effect of the semiconductor preparation method of the present invention is based on (4) stacking and stacking the upper and lower layers of the insect layer of the complex layer, and each of the "high concentration of the trench in the layer is superposed on the upper and lower stacking combination" forming body The super junction structure enables the metal oxide cast field effect transistor or the Xiaoxian diode body conductor to have a lower forward resistance value and a high reverse bias voltage in the semiconductor substrate prepared by the method of the present invention. Low reverse leakage current characteristics, and has the effect of 'rich high pressure and low shop The fine metal oxide semiconductor _-effect transistor, Schottky diodes, or can be applied to high power and high voltage operation applications. 〆 [Embodiment] ' ° Please refer to the first to the tenth AD, the first figure is a flow chart of the semiconductor preparation method of the present invention, the steps of which include steps 1 〇 to 7 〇, where: UU) lower gamma stacking 'As the first point, on the other hand, a layer of epitaxial layer 205 is stacked. The substrate 200 is made of N+ semiconductor material in the present invention: the epitaxial layer 205 is N-epitaxial; ',. ', column' s Xuan (20) trench formation, as shown in the third figure 'in step 1 为 is the formation of the layer 2 〇 5 in the formation of a complex Mo 201240016 trough 210; (30) trench side wall to form a high concentration of doping The impurity layer, as shown in the third figure, implants ions at an oblique angle in each of the trenches 210 of step 2(), and implants the concentration-doped ion semiconductor material at an oblique angle to the sidewall of the trench 21 to form a high concentration. The doped layer 21S is on the side wall of the trench 2 ι, the high concentration doped layer 215 is composed of a P-type doped semiconductor; (40) the filling layer is filled with a high concentration in the step 3 as shown in the fourth figure. The inside of the doping layer 215 is filled with a filling layer 220, which is an oxide or a polysilicon; (50) a planarization process as shown in the fourth figure, step 4 The surface of the filling layer 22 of the crucible is flattened; (60) the stacking process of the plurality of layers of Jaa layer, as shown in the fifth to the eleventh a layer, above the layer of the layer of the layer of the insect layer 210, above and below the stacking manner, stacking The epitaxial layer of the plurality of layers is 3 〇〇, the epitaxial layer 300 is N-epitaxial, and the trench formation of the same step 20 is performed one by one in each of the epitaxial layers 3 (8), and the trench sidewalls of step 3 are formed high. a concentration doping layer, an oxide filling in step 40, and a planarization process in step 50, such that a trench 305, a high concentration doping layer 31, and a filling layer 315 are formed in each of the epitaxial layers 3 Inside the high concentration doping layer 310, the high concentration doping layer 31 is composed of a p-type doped semiconductor, the filling layer 315 is an oxide or polysilicon, and the lower epitaxial layer 21 is separated from the epitaxial layer 300. The grooves 210 and 305 and the high-concentration doping layers 215 and 310 are integrated with the filling layers 220 and 315 in an upper and lower stack. The high-concentration doping layers 21 and 31 are stacked and stacked to form a super junction. The number of layers of the epitaxial layer 3 is not limited to the above two layers, and the lower epitaxial layer 2 The width, height or shape of the trenches 21A and 305 and the high-concentration doping layers 215 and 310 of the respective epitaxial layers 300 are not limited to be the same. (70) A semiconductor substrate on which a plurality of epitaxial stacks are formed is prepared, and a plurality of epitaxially stacked semiconductor substrates 400 as shown in Fig. 10A are formed by stacking and stacking the respective layers of the epitaxial layers 300 of the step 6. Referring to FIG. 4B, a second embodiment of a semiconductor substrate 400 prepared according to the preparation method shown in steps 1A to 7B of the first drawing of the present invention, wherein the lower layer epitaxial layer is displayed. The width between 210 and trenches 210 and 305 of each epitaxial layer 300 is increased from bottom to top by 201240016, and the lower epitaxial layer 210 and trenches 210 and 305 of each epitaxial layer 300 are high. The concentration doping layers 215 and 310 and the filling layers 220 and 315 are stacked on top of each other to form a screw-like shape, but the upper and lower stacked shapes are not limited to those shown in FIG. 11 and FIG. . Please further cooperate with the third embodiment of the semiconductor substrate 400 prepared according to the preparation method shown in the steps 10 to 7 of the first drawing of the present invention, in which the lower layer epitaxial layer is displayed. The shapes of the trenches 210 and 305 of each of the 210 and the epitaxial layers 300 are trapezoidal shapes of the upper width and the lower width, and the lower layer epitaxial layer 210 and the trenches 21 and 3〇5 of the epitaxial layers 300 are also allowed to be concentrated. The dummy layers 215 and 310 and the filling layers 220 and 315 are stacked on top of each other. Further, in combination with the eleventh and twelfth drawings, an application example of the semiconductor substrate 4 prepared by the above method for preparing a semiconductor substrate of the present invention, wherein the series is applied to a metal oxide semiconductor field The effect transistor 500 (shown in FIG. 12) is in the state of the semiconductor base material at the time of manufacture, as shown in FIG. 11, the uppermost layer of the crystal layer in the semiconductor substrate 400 as shown in FIG. A top layer of the epitaxial layer 400A is N-epitaxial, and a buried layer 41〇 and 曰420 and a buried layer 41 are formed in the top epitaxial layer 4A. A high-concentration doped layer 310 formed on the sidewall of the trench 305 of the epitaxial layer 3 (8) of the uppermost layer of the semiconductor substrate 4 (8) is bonded to the top surface of the filling layer 315, and the base layer 20 and σ are embedded in the layer Above, the buried layer 41 is a p-type semiconductor material, and the base layer 420 is a p-type semiconductor material, and the base layer 42 has a top surface and forms a junction. As shown in FIG. 11 , the plurality of source and gate electrodes are respectively coupled to the top layer of the top layer of the top layer of the top layer through the oxide layer junction 450, and the top surface of the base layer 42 is similar to the surface of the NPN. In the meantime, the substrate on the side of the semiconductor substrate is formed into a metal oxide semiconductor field effect transistor lion which has a super junction trench. ^With the thirteenth_shown as the above-mentioned tenth-figure and twelfth-thick towel, the semiconductor substrate 4 (8) prepared by the method of the present invention, the metal oxide semiconductor field effect transistor = 500' and the conventional Experiment and line diagram of the reverse bias state between metal oxide semiconductor field effect transistors. The lateral axis is the secret voltage DV, the unit is volt, and the longitudinal axis is the source _ and the reverse leakage current of the gate. The unit is ampere. , curve & represents the experimental curve 'curve 82 of the metal oxide 201240016 _ of the present invention', and the experimental curve of the conventional metal oxide semiconducting % effect electric Ba body, which is compared with the curve s2 by the curve S1 The semiconductor substrate 4 (8) prepared by the invention of the injury method is applied to the metal oxide half-effect electric current, and the body 5 确 has a characteristic of high reverse bias and low reverse leakage current, and the metal oxide semiconductor field effect transistor 5, if a better reverse bias voltage is to be obtained, the semiconductor substrate 4 can be obtained by increasing the number of layers of the insect layer in the plurality of layers of the twin layer stacking step of the above step 6 . ^ Referring to the fourteenth aspect, for the above-mentioned needle-- and the busy diagram, the semiconductor substrate prepared by the preparation method of the present invention is used to form a metal oxide semiconductor field effect transistor 5〇〇 and a metal oxide semiconductor field. An experimental graph of the forward bias state between the effecting transistors, where 'the transverse axis is the _voltage GV, the unit is volts, the longitudinal axis is the immersion current DA, the unit is ampere, and the curve % represents the metal oxidation of the present invention. Semiconductor field effect transistor, experimental curve of 500, curve % represents the experimental curve of a conventional metal oxide semiconductor field effect transistor. From the curve S3 and the curve are compared with each other, it can be clearly seen that the present invention The semiconductor substrate shed prepared by the preparation method is applied to the metal oxide conductor field effect f crystal 5GG' with the characteristics of lateral electric bribe. The experimental results of the above materials III and 14 are similarly applicable to the preparation of the invention according to the present invention. The experimental results of low axial miscellaneous values, low reverse height and low reverse flow can be obtained. The drawings and descriptions of the method for preparing a semiconductor substrate of the present invention are for convenience of explaining the technical contents of the present invention, and the related matters are not limited to the materials of the present invention. The equivalents and permutations of the steps, procedures, or elements of the present invention are intended to be the scope of the present invention, the scope of which is defined by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a flow chart of a method for preparing a semiconductor substrate of the present invention; * The second figure is a cross-sectional view showing a state in which a lower layer of a worm layer is stacked on a substrate in the method of the present invention; 201240016 The second figure is a cross-sectional view showing the state of the lower layer of the worm layer in the method of the present invention into a high-concentration lining state; g ^ and the flattening of the fourth figure is a cross-sectional view showing the method of the present invention for the lower layer of the epitaxial layer treatment The fifth embodiment of the epitaxial layer is a cross-sectional view showing the state of the stack of the underlying epitaxial layers in the method of the present invention; - the sixth figure is a cross-sectional view showing the lower epitaxial layer in the method of the present invention The state of the first layer of the epitaxial layer of the trench-shaped grooved turbidity concentration impurity layer; aa 曰 seventh figure is a cross-sectional view showing the filling and flattening of the lower layer of the remote layer in the method of the present invention The eighth figure is a section showing the state of the second layer of the wormhole layer of the lower layer of the crystal layer in the method of the present invention; the ninth section is a cross-sectional view showing the layer of worms in the method of the present invention The first groove of the crystal layer Forming a state in which a high concentration doping layer is formed with the sidewall of the trench; FIG. 10 is a cross-sectional view showing the filling and planarization of the second epitaxial layer of the lower epitaxial layer in the method of the present invention. The state of the semiconductor substrate; FIG. 10B is a view showing a second embodiment of preparing a semiconductor substrate in the method of the present invention; and the tenth C is a third embodiment of preparing a semiconductor substrate in the method of the present invention, The ten-graph is a specification, which shows an application example of a semiconductor substrate prepared by the method of the present invention in consideration of a manufacturing process of a metal oxide semiconductor field effect transistor; and a twelfth aspect is a semiconductor substrate prepared by the method of the present invention. a metal oxide semiconductor field effect transistor sectional view; a twelfth figure is an experimental graph of a metal oxide semiconductor field effect transistor formed by a semiconductor substrate prepared by the method of the present invention in a reverse bias state; Figure 14 is an experimental graph of a metal oxide semiconductor field effect transistor fabricated by applying the method of the present invention in a forward biased state. [Main component symbol description] 10 Lower epitaxial layer stack 20 Trench formation 201240016 30 Trench sidewall forming high concentration doping layer 40 Filling layer filling 50 Flattening process 60 Complex layer epitaxial layer stacking process 70 Preparation to form a complex layer Epitaxially stacked semiconductor substrate 200 substrate 205 telecrystalline layer 210 trench 215 high concentration doped layer 220 filled layer 300 epitaxial layer 305 trench 310 high concentration doped layer 315 filled layer 400A top epitaxial layer 410 buried Layer 420 Base 421 NPN Junction 430 Source 440 Gate 450 Oxide Junction 400 Semiconductor Substrate 500 Metal Oxide Semiconductor Field Effect Transistor

Claims (1)

201240016 七、申請專利範圍： 1.-種半導體基材之製備方法，其步驟係包括： a. 下·晶層堆疊，係在—基材上，堆疊—下層蟲晶層； b. 溝槽形成，在步驟3之為晶層内形成複數溝槽； e.龍箱«高濃度摻闕，在步驟b之各溝射以傾斜角度注入離 麟賴雜_斜角粒人高濃度雜軒半賴材料，形成 尚濃度摻雜層於溝槽邊牆上； d. 填充層填充，於麵e巾之高濃度摻雜勒側填充 e. 平坦化處理，將步驟d之填充層表面進行平坦化處理；、 f. 複數層蟲晶層堆疊處理，在步驟3之下層蟲晶層上方以上、下堆最方 式，堆疊複數層之蟲晶層，並於每一層蟲晶層逐—實施相同於步ς匕 之溝槽形成、步驟c之溝槽邊牆形成高濃度摻雜層、步驟d填充 與步驟f之平坦化處理等步驟，使每一個遙晶層内均形成溝槽、言農 摻雜層，以及填紐於高濃度_層關，並讓下妓晶:與^ 磊晶層之溝槽、高濃度摻雜層，與填充層均呈上'下堆疊連結為二、 該局濃度摻雜層並堆疊結合形成超級接面；以及 g·製備形成一複數層磊晶堆疊之半導體基材，藉由步驟f之各層磊a 疊組合形成一複數層蠢晶堆疊之半導體基材。 aa層堆 2. 如申請專利範圍第丨項所述之半導體基材之製備方法，复 基材為辦導體材料。 、中該步驟a之 3. 如申請專利範圍第丨項所述之半導體基材之製備方法，其 下層磊晶層為N-磊晶。 a之 4. 如申請專利範圍第丨項所述之半導體基材之製備方法，其 ^ 、 〇发步驟C之 南啟度摻雜層為p型摻雜半導體構成。 5. 如申請專利範圍第丨項所述之半導體基材之製備方法，其 填充層為氧化物。 d之 6. 如申請專利範圍第丨項所述之半導體基材之製備方法，其 填充層為多晶石夕。 7. 如申請專利範圍第丨項所述之半導體基材之製備方法，其中，該步驟^之 201240016 各蟲晶層為N-蟲晶。 8. 如申請專利範圍第1項所述之半導體基材之製備方法，其中，該步驟f之 各磊晶層之高濃度摻雜層為P型摻雜半導體構成。 9. 如申請專利範圍第1項所述之半導體基材之製備方法，其中，該步驟f之 各蠢晶層之填充層為氧化物。 10. 如申請專利範圍第1項所述之半導體基材之製備方法，其中，該步驟f 之各蠢晶層之填充層為多晶珍。201240016 VII. Patent application scope: 1. A method for preparing a semiconductor substrate, the steps of which include: a. lower layer layer stacking on the substrate, stacking-lower layer of insect layer; b. trench formation In step 3, a plurality of trenches are formed in the crystal layer; e. Dragon box «high-concentration erbium-doped, and each of the trenches in step b is injected at an oblique angle to infiltrate the lining The material is formed to form a doping layer on the sidewall of the trench; d. filling the filling layer, filling the surface of the surface with a high concentration of doping. e. Flattening, planarizing the surface of the filling layer of step d ;, f. complex layer of insect layer stacking treatment, in step 3 above the layer of insect layer above and below the stack of the most way, stacking layers of the layer of insects, and in each layer of the layer of insects - the implementation of the same step The groove formation of the crucible, the formation of the high-concentration doped layer of the trench sidewall of the step c, the filling of the step d and the planarization treatment of the step f, etc., so that the trenches and the doped layer are formed in each of the telecrystal layers. , and fill in the high concentration _ layer off, and let the lower twin: and ^ the epitaxial layer of the trench, The concentration doping layer and the filling layer are both upper and lower stacked, and the local concentration doping layer is stacked and combined to form a super junction; and g·preparing a semiconductor substrate forming a plurality of epitaxial stacks, The layers of step f are stacked to form a plurality of layers of staggered crystal stacked semiconductor substrates. Aa layer stack 2. The method for preparing a semiconductor substrate as described in the scope of claim 2, wherein the substrate is a conductor material. 3. The method of preparing the semiconductor substrate according to the invention of claim 5, wherein the lower epitaxial layer is N-epitaxial. A. The method for preparing a semiconductor substrate according to the above-mentioned patent application, wherein the south-degree doping layer of the step C is a p-type doped semiconductor. 5. The method of preparing a semiconductor substrate according to claim 2, wherein the filling layer is an oxide. 6. The method of preparing a semiconductor substrate according to the invention of claim 2, wherein the filling layer is polycrystalline. 7. The method for preparing a semiconductor substrate according to the invention of claim 2, wherein the step 4, 201240016, is a N-worm crystal. 8. The method for producing a semiconductor substrate according to claim 1, wherein the high concentration doping layer of each of the epitaxial layers of the step f is a P-type doped semiconductor. 9. The method of producing a semiconductor substrate according to claim 1, wherein the filling layer of each of the stray layer of the step f is an oxide. 10. The method for preparing a semiconductor substrate according to claim 1, wherein the filling layer of each of the stray layer of the step f is polycrystalline.
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CN107316899A (en) * 2017-07-14 2017-11-03 何春晖 Half superjunction devices and its manufacture method
TWI800105B (en) * 2020-11-23 2023-04-21 加拿大商萬國半導體國際有限合夥公司 Gas dopant doped deep trench super junction high voltage mosfet

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US7638841B2 (en) * 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
CN101185169B (en) * 2005-04-06 2010-08-18 飞兆半导体公司 Trenched-gate field effect transistors and methods of forming the same
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US7772668B2 (en) * 2007-12-26 2010-08-10 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels

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CN104934465A (en) * 2015-05-12 2015-09-23 电子科技大学 Super junction composition preparation method
CN107316899A (en) * 2017-07-14 2017-11-03 何春晖 Half superjunction devices and its manufacture method
TWI800105B (en) * 2020-11-23 2023-04-21 加拿大商萬國半導體國際有限合夥公司 Gas dopant doped deep trench super junction high voltage mosfet

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