TWI469274B - 在介電塊上具端子之微電子封裝 - Google Patents

在介電塊上具端子之微電子封裝 Download PDF

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Publication number
TWI469274B
TWI469274B TW100141695A TW100141695A TWI469274B TW I469274 B TWI469274 B TW I469274B TW 100141695 A TW100141695 A TW 100141695A TW 100141695 A TW100141695 A TW 100141695A TW I469274 B TWI469274 B TW I469274B
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Taiwan
Prior art keywords
package
package substrate
traces
microelectronic
sheet
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TW100141695A
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English (en)
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TW201230256A (en
Inventor
Belgacem Haba
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Tessera Inc
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Publication of TW201230256A publication Critical patent/TW201230256A/zh
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Publication of TWI469274B publication Critical patent/TWI469274B/zh

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    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Description

在介電塊上具端子之微電子封裝
本發明係關於微電子封裝。
本申請案主張2010年11月15日申請之韓國專利申請案第10-2010-0113271號的優先權，該申請案之揭示內容以引用之方式併入本文中。
微電子元件(諸如，半導體晶片)普遍地具備保護微電子元件且促進其至較大電路之其他元件之連接的元件。舉例而言，半導體晶片典型地被提供為小平坦元件，其具有對置面對之前表面及後表面以及曝露於前表面處之接點。接點電連接至一體式地形成於晶片內之眾多電子電路元件。此晶片最普遍地提供於具有被稱作封裝基板之小型電路面板的封裝中。晶片典型地安裝至封裝基板而使前表面或後表面上覆於封裝基板之表面，且封裝基板典型地具有曝露於基板之表面處的端子。端子電連接至晶片之接點。封裝典型地亦包括某種形式之覆蓋物，覆蓋物在與封裝基板對置的晶片之側面上上覆於晶片。覆蓋物用來保護晶片，且在一些狀況下保護晶片與封裝基板之導電元件之間的連接件。可藉由將封裝基板之端子連接至導電元件(諸如，較大電路面板上之接觸焊墊)而將此已封裝晶片安裝至電路面板(諸如，電路板)。
在某些封裝中，晶片經安裝而使其前表面或後表面上覆於封裝基板之上部表面，而端子提供於對置面對之下部表面上。介電材料塊上覆於晶片，且最典型地上覆於晶片與封裝基板之導電元件之間的電連接件。可藉由圍繞晶片而模製可流動介電組合物以使得介電組合物覆蓋晶片及封裝基板之頂部表面之全部或部分來形成介電塊。此封裝被普遍地稱作「包覆模製(overmolded)」封裝，且介電材料塊被稱作「包覆模具(overmold)」。包覆模製封裝製造起來經濟且因此被廣泛地使用。
在一些應用中，需要將晶片封裝堆疊於彼此頂部，使得可在較大電路面板之表面上的同一空間中提供複數個晶片。某些包覆模製封裝在藉由晶片覆蓋之區域外部且典型地在藉由包覆模具覆蓋之區域外部併入曝露於封裝基板之頂部表面處的堆疊接點。此等封裝可堆疊於彼此頂部而使互連元件(諸如，焊球或其他導電連接件)延伸於堆疊中較低封裝之堆疊接點與次較高封裝之端子之間。在此配置中，堆疊中之所有封裝皆在堆疊之底部處電連接至封裝上端子。然而，在此配置中，在藉由包覆模具覆蓋之區域外部，必須將所有互連元件容納於封裝基板之有限區帶中。此外，因為堆疊中較高封裝之封裝基板位於次較低封裝中之介電包覆模具上方，所以在垂直方向上於較高封裝之端子與較低封裝之堆疊接點之間存在明顯間隙。互連元件必須橋接此間隙。此情形典型地要求互連元件以相對大間隔而隔開。因此，可使用給定大小之封裝基板而容納之互連元件的數目受到限制。
儘管此項技術中有顯著努力來致力於開發可堆疊封裝及具有頂部表面安裝焊墊之其他封裝，但將需要進一步改良。
本發明之一態樣提供一種微電子封裝。根據本發明之此態樣之一封裝理想地包括一第一微電子元件以及一封裝基板，該封裝基板具有延伸於水平方向上之上部表面及下部表面，以及延伸於該上部表面與該下部表面之間的邊緣。理想地，該封裝基板具有導電元件，該等導電元件包括曝露於該封裝基板之該下部表面處的底部端子。該微電子元件較佳地安置於該封裝基板之該上部表面之上且連接至該封裝基板上之該等導電元件中至少一些。根據本發明之此態樣之該封裝較佳地包括覆蓋該微電子元件及該封裝基板之該上部表面之至少一部分的一介電塊。該介電塊界定背對該封裝基板的遠離於該封裝基板之一頂部表面。較佳地，該頂部表面之至少一部分延伸於該微電子元件之上。該介電塊理想地亦界定一第一邊緣表面，該第一邊緣表面自鄰近於該介電塊之該頂部表面的一頂部邊界向下延伸至鄰近於該封裝基板之一底部邊界，該底部邊界安置於該封裝基板之該等邊緣內部。較佳地，該介電塊進一步界定一向上面對之第一凸緣表面，該第一凸緣表面鄰近於該封裝基板在一水平方向上延伸離開該第一邊緣表面之該底部邊界，該第一凸緣表面經安置成與該封裝基板相隔一垂直距離，該垂直距離小於在該封裝基板與該頂部表面之間的一垂直距離。
最佳地，該封裝包括曝露於該介電塊之該頂部表面處的複數個頂部端子，及自該等頂部端子沿著該頂部表面而延伸且沿著該第一邊緣表面而延伸之複數個第一跡線，該等第一跡線具有沿著該凸緣表面而延伸的鄰近於該封裝基板之底部部分，該等底部部分電連接至該封裝基板之該等導電元件。
如下文進一步所論述，根據本發明之此態樣之某些封裝可提供連接至該封裝基板上之眾多導電元件的眾多頂部端子。舉例而言，可以一堆疊式配置使用此等封裝，在該堆疊式配置中，一封裝之該等頂部端子連接至另一封裝之該等底部端子。
根據本發明之一另外態樣之一封裝理想地包括一微電子元件，及具有延伸於水平方向上之上部表面及下部表面的一封裝基板，該微電子元件安置於該封裝基板之該上部表面之上。理想上，該微電子元件電連接至該封裝基板上之至少一些導電元件。根據本發明之此態樣之該封裝理想地包括覆蓋該封裝基板及該微電子元件之該上部表面之至少一部分的一包覆模具，該包覆模具界定背對該封裝基板的遠離於該封裝基板之一頂部表面，該包覆模具頂部表面之至少一部分延伸於該微電子元件之上。該封裝理想地進一步包括：頂部端子，其曝露於該包覆模具之該頂部表面處；及複數個跡線，其自該等頂部端子沿著該包覆模具之該頂部表面而延伸，該等頂部端子及該等跡線嵌入於該包覆模具中。最佳地，該等跡線為固體金屬跡線。
本發明之另外態樣提供系統，該等系統結合其他電子器件而併入根據本發明之上述態樣之封裝。舉例而言，該系統可安置於單一外殼中，該單一外殼可為一攜帶型外殼。
本發明之又另外態樣提供製造微電子封裝之方法。一種此類方法包括如下步驟：將一載體(諸如，承載複數個跡線之一薄片)定位於具有導電元件之一封裝基板與上覆於該封裝基板且電連接至該等導電元件之一微電子元件的一集合體之上，進行該定位步驟，使得該等跡線中至少一些之部分延伸於該微電子元件之上。該方法理想地亦包括如下步驟：在該載體與該封裝基板之間及圍繞該微電子元件引入一可流動組合物，且固化該組合物以形成覆蓋該微電子元件且具有藉由該載體至少部分地界定之一形狀之一包覆模具。較佳地，該方法亦包括移除該載體，以便使該等跡線延伸於背對該封裝基板的該包覆模具之一或多個表面之上。
根據本發明之此態樣之一另外方法理想地包括如下步驟：將一載體(諸如，承載複數個跡線之一薄片)定位於具有導電元件之一封裝基板與上覆於該封裝基板且電連接至該等導電元件之一微電子元件的一集合體之上。在此方法中，理想地執行該定位步驟，使得該載體之一第一部分及在該載體之該第一部分上的該等跡線之第一部分延伸於該微電子元件之上，且該載體之一第二部分及在該載體之該第二部分上的該等跡線之第二部分自該第一部分朝向該封裝基板而延伸。舉例而言，該載體可為在其上具有跡線之一薄片，且該薄片可彎曲或以其他方式變形，使得該載體之該第二部分自該載體之該第一部分朝向該封裝基板而突出。
此方法理想地亦包括如下步驟：在該薄片與該封裝基板之間及圍繞該微電子元件引入一可流動組合物，且固化該組合物以形成覆蓋該微電子元件且具有藉由該載體至少部分地界定之一形狀之一包覆模具。最佳地，該方法包括將該等跡線之該等第二部分與該封裝基板之該等導電元件進行電連接。可在形成該包覆模具之前或之後執行該連接步驟。在任一狀況下，該等跡線之該等第二部分與該封裝基板的近接促進形成小連接件，此情形又有助於在有限大小之一封裝中提供眾多跡線。
一種製造一微電子封裝之另外方法包括如下步驟：將一保形介電層沈積至具有導電元件之一封裝基板與上覆於該封裝基板之一上部表面且電連接至該等導電元件之一微電子元件的一集合體上，該等導電元件包括曝露於該封裝基板之一下部表面處的底部端子。理想地，執行該沈積步驟，使得該保形層之一第一部分界定遠離於該封裝基板且延伸於該微電子元件之上的一頂部表面，且該保形層之一或多個額外部分界定一或多個邊緣表面，該一或多個邊緣表面朝向該封裝基板而向下延伸於藉由該微電子元件覆蓋之一區域外部。該方法理想地包括在該保形層上提供跡線及頂部端子，使得該等跡線沿著該頂部表面而延伸且沿著至少一邊緣表面朝向該封裝基板而延伸，且該等跡線之底部部分經定位成鄰近於該封裝基板。理想地，該方法進一步包括將該等跡線之該等底部部分連接至該封裝基板上之該等導電元件中至少一些。
根據本發明之一實施例的用於製造程序中之組件將呈金屬薄片30之形式的載體併入為(例如)具有第一表面32及對置第二表面34之銅薄片(圖1及圖2)。第一表面32承載複數個導電跡線36。跡線經形成為導電材料之狹長條帶，導電材料較佳地為固體金屬，諸如，在薄片30之第一表面32上的銅、金、鎳及其組合。跡線係與具有相似組合物之端子38一體式地形成。端子安置於薄片之第一部分40(藉由摺線示意性地指示)中。跡線自端子延伸至第二部分42中。在此實施例中，第二部分42包括在第一部分40之對置側面上的區帶。儘管圖1及圖2中僅描繪幾個端子38及幾個跡線36，但實務上，可存在幾百個或幾百個以上端子及跡線。
端子38係以「區域陣列(area array)」而安置於第一部分40內。如本發明所使用，術語「區域陣列」意謂如下端子陣列：其中端子實質上分散遍及二維區帶，而非以幾個列(諸如，僅在區帶之周邊的列，或僅在區帶之中心的列)而集中。儘管圖1所示之特定區域陣列為直線均一陣列，但此情形不係必需的。
可藉由眾多已知金屬加工方法來製造端子及跡線，如(例如)藉由蝕刻最初具有大於薄片30之厚度的薄片，以便自除了藉由端子及跡線佔據之區域以外的區域移除金屬，或藉由將端子及跡線電鍍至薄片上。圖1及圖2僅描繪具有適於製造單一封裝之大小的單一薄片。然而，實務上，薄片理想地被提供為併入眾多部分之連續或半連續元件，每一此類部分構成圖1及圖2所示之薄片，此等部分係彼此連續的。
根據圖1及圖2之薄片係結合集合體46(圖3)予以利用，集合體46併入微電子元件48，諸如，具有前表面50、後表面52及曝露於該前表面處之接點54的半導體晶片。集合體46亦包括呈小電路面板之形式的封裝基板，電路面板併入大體上平面介電結構56，介電結構56具有頂部表面58及對置面對之底部表面60。如本文所使用之字詞「頂部」及「底部」指代所論述之元件之參考座標，而不指代正常重力參考座標。封裝基板56亦包括導電元件，在此例子中，導電元件併入延伸於底部表面60上之跡線62及亦曝露於介電結構之底部表面處且連接至跡線62的端子64。
集合體亦包括將晶片48之接點54與封裝基板上之跡線62連接的導線結合件66。封裝基板具有孔隙68，孔隙68經配置成使得跡線62通過孔隙68而曝露於封裝基板之上部表面處。在圖3所描繪之特定實施例中，眾多集合體之封裝基板被提供為連續或半連續元件，諸如，條帶、帶子或薄片。因此，儘管出於說明清晰性起見而在圖3中之個別封裝基板56之間存在可見邊界，但實務上，在該程序之此階段可不存在可辨別邊界。封裝基板46中之孔隙68理想地係藉由跡線62完全地封閉。同樣地，其中導線結合件66穿透至跡線的孔隙理想地係藉由跡線完全地覆蓋，使得封裝基板為連續的不滲透薄片。
在該方法之一步驟中，將包括眾多載體或薄片30之元件定位於包括眾多集合體46(具有其封裝基板及晶片)之元件之上。每一載體或薄片30經定位成使得承載跡線36及端子38之第一表面32面朝封裝基板。在圖3之實施例中，定位步驟包括使每一載體薄片30自圖1及圖2所描繪之平坦條件變形至變形條件(其中每一薄片之第二部分42自第一部分40彎曲成不在平面中)，其中第二部分42突出於第一表面32之方向上，如在圖2中之42'處示意性地所指示。此情形可藉由基本上任何習知形成技術而進行，如(例如)藉由在衝壓機中使用匹配型金屬沖模。所形成之載體薄片定位於晶片與封裝基板之集合體之上，使得承載端子38的載體薄片30(圖1)之第一部分40延伸於微電子元件或晶片48之上，且第二部分42自第一部分40朝向封裝基板46而延伸。
在此條件下，每一載體薄片30之第二部分42界定自該薄片之第一部分40延伸之傾斜區帶70，且亦界定自傾斜區帶70突出之凸緣區帶74。第二部分42中之跡線沿著傾斜區帶70而延伸且亦沿著凸緣區帶74而延伸。因此，在薄片之第二部分42中的跡線36之彼等部分包括沿著傾斜區帶70而延伸之傾斜部分76，及延伸於凸緣部分74上之底部部分78。
在載體薄片30定位於封裝基板46之上的情況下，跡線之底部部分78及薄片之凸緣區帶74經安置成接近於封裝基板46。薄片上之跡線之底部部分78係藉由任何合適連接件(如(例如)藉由焊接結合件80)而連接至封裝基板上之跡線62。可以極佳準確度來控制載體薄片30上之跡線的位置及封裝基板56上之導電特徵的位置。此情形促進結合程序且促進使用允許跡線之緊密間距的小直徑結合件。
在已將載體薄片上之跡線結合至封裝基板上之跡線之後，將已組裝部件置放至模具中，使得模具之第一側面82支撐載體薄片30，而模具之第二側面84支撐封裝基板46。儘管模具部件被描繪為緊密地上覆於載體薄片及封裝基板，但在模具部件與載體薄片30或封裝基板46之間無需密封嚙合。相反地，模具部件用來實體地支撐載體薄片及封裝基板且防止在下文所論述之模製步驟期間此等元件之失真。
在下一步驟(圖4)中，將可流動組合物(如(例如)環氧樹脂)引入至在每一載體薄片30與關聯封裝基板46之間及圍繞該封裝基板上之晶片或微電子元件48的空間中。固化此可流動組合物以形成包覆模具86(圖4)。隨著引入可流動組合物，其接觸載體薄片且因此呈至少部分地藉由載體薄片界定之形狀。又，可流動組合物流動而與跡線及端子進行親密接觸且部分地環繞跡線及端子。然而，因為載體薄片30與跡線之表面進行親密接觸，且特別是與端子38進行親密接觸，所以面朝該載體薄片的該等端子之面被完全地保護以防與可流動組合物接觸。又，封裝基板46保護該封裝基板上之端子64以防受到可流動組合物污染。因為載體薄片30及封裝基板46被提供為連續或半連續薄片，所以無需使模具部件將可流動組合物限制於任一特定載體薄片或封裝基板之邊際處。可流動組合物可被引入至在一個載體薄片與封裝基板之間的空間中且可流動至在其他載體薄片與封裝基板之間的空間中。
在該程序之下一階段中，移除模具元件82及84，從而使載體薄片30曝露於模製集合體之一個側面上且使封裝基板上之端子64曝露於對置側面上(圖5)。在該程序之下一階段中，移除載體薄片30，如(例如)藉由將該等載體薄片曝露至有效於移除該載體薄片但使端子38及跡線36實質上完好之蝕刻劑。在蝕刻之後，集合體具有圖6所說明之組態。接著，沿著分離線88切開集合體以得到個別微電子封裝90。
每一封裝90(圖7至圖9)包括一封裝基板56，封裝基板56具有延伸於水平方向上之上部表面58及下部表面60，以及延伸於該上部表面與該下部表面之間的邊緣92。封裝90亦具有導電元件，導電元件包括曝露於下部表面60處之跡線62及端子64。在已完成封裝中，將端子64稱作「底部端子」。如本文參考導電元件(諸如，端子或跡線)所使用，術語「曝露於」表面處意謂可自彼表面接取導電元件。在所說明之特定實施例中，底部端子64安置於下部表面60上，使得該等底部端子自該下部表面稍微突出。然而，即使底部端子嵌入於封裝基板56中或安置於該基板之頂部表面58上，底部端子亦可曝露於下部表面處，其限制條件為在基板中存在允許接取之開口。
封裝90亦包括呈晶片之形式的第一微電子元件48，此微電子元件安置於封裝基板之上部表面58之上且電連接至導電元件(封裝基板上之特定跡線62及底部端子64)。
封裝進一步包括呈在上文所論述之模製程序期間所形成之包覆模具86之形式的介電塊，此介電塊覆蓋微電子元件48及封裝基板之上部表面之至少一部分。介電塊或包覆模具86界定遠離於封裝基板56之頂部表面94。頂部表面94之至少一部分延伸於微電子元件48之上。塊或包覆模具86亦界定第一邊緣表面96，第一邊緣表面96自鄰近於頂部表面94之頂部邊界98向下延伸至鄰近於封裝基板56且安置於封裝基板之邊緣92內的底部邊界100。亦即，底部邊界100安置於藉由封裝基板之邊緣92界限的水平區域內。介電塊之第一邊緣表面96在第一水平方向H1 (圖7、圖9及圖10A)上傾斜離開微電子元件48，使得該第一邊緣表面之底部邊界100在水平方向H1 上比頂部邊界98更遠離於該微電子元件。第一邊緣表面96經塑形成使得沿著該第一邊緣表面而延伸成與封裝基板56相隔恆定垂直距離之任何直線安置於在第一水平方向H1 上之恆定部位處。舉例而言，延伸成與封裝基板相隔恆定垂直距離之虛線102(圖7)將亦位於恆定水平部位處。在所示之特定實施例中，第一邊緣表面係實質上平面的。
如在圖10A中最好地所見，介電塊或包覆模具進一步界定離開封裝基板56的向上面對之第一凸緣表面104。第一凸緣表面在第一水平方向H1 上延伸離開第一邊緣表面96之底部邊界100。第一凸緣表面104經安置成鄰近於封裝基板56。在第一凸緣表面104與封裝基板之頂部表面58之間的距離D1 顯著地小於在介電塊之頂部表面94與封裝基板之頂部表面58之間的距離DT 。
如圖7、圖9及圖10A所示，端子38曝露於介電塊之頂部表面94處。在已完成封裝中，將端子38稱作「頂部端子」。複數個跡線36a自頂部端子38中之一些沿著頂部表面94而延伸，且橫越頂部邊界98及沿著第一邊緣表面96而進一步延伸。沿著第一邊緣表面96而延伸的跡線之彼等部分彼此實質上平行。跡線包括底部部分78，底部部分78沿著第一凸緣表面104而延伸。如本發明所使用，跡線「沿著」表面而延伸之語句意謂跡線緊鄰於表面且實質上平行於表面而延伸。在圖7、圖9及圖10A所描繪之特定實施例中，跡線嵌入於頂部表面94、第一邊緣表面96及凸緣表面104中，其中跡線之表面與介電塊或包覆模具86之表面實質上齊平。舉例而言，如在圖8中所見，跡線36a之表面與第一邊緣表面96齊平。此特定齊平安置起因於如下事實：頂部表面94、第一邊緣表面96及凸緣表面104係藉由載體薄片形成，且跡線在形成時被攜載於載體薄片之表面上。相似地，頂部端子38嵌入於介電塊之頂部表面94中。嵌入式跡線及端子可由固體金屬(如(例如)固體銅或銅合金)形成。典型地，固體金屬相比於包括金屬及黏合劑之複合物提供較高電導率。跡線36a之底部部分78駐留於凸緣表面104上，此係因為該等底部部分最初駐留於薄片之凸緣部分74上(圖3)。當然，跡線之底部部分78保持連接至封裝基板之導電元件，且特別是連接至跡線62，使得跡線36a且因此頂部端子38中之一些連接至底部端子64中之一些且連接至微電子元件48。
封裝進一步包括：第二邊緣表面108，其自頂部表面94向下延伸且在與第一水平方向H1 對置之第二水平方向H2 上傾斜離開微電子元件48；及第二凸緣表面110，其在第二水平方向上自第二邊緣表面108之底部邊界延伸。封裝進一步包括自頂部端子38中之一些沿著頂部表面94、第二邊緣表面108及第二凸緣表面110而延伸的跡線36b。此等特徵相同於上文所論述的第一邊緣表面96、第一凸緣表面104及跡線36a之特徵，惟方向被反轉除外。跡線36b經由封裝基板上之跡線62中之一些而將頂部端子38中之一些連接至底部端子64中之一些且連接至微電子元件48。
在此配置中，頂部端子38中之一些或全部係藉由封裝基板上之導電元件而連接至微電子元件或晶片48之接點54，且頂部端子38中之一些或全部亦連接至底部端子64中之一些或全部。頂部端子38係以對應於底部端子64之圖案的圖案而配置。因此，如圖9所示，封裝90中之兩者或兩者以上可以一堆疊而疊置，其中堆疊中之底部封裝90a之頂部端子連接至次較高封裝90b之底部端子64。堆疊之最下部或底部封裝之底部端子64可連接至導電元件(諸如，較大電路基板114上之接觸焊墊112)，使得整個堆疊安裝及連接至電路面板。
可將阻焊劑(未圖示)塗覆遍及延伸於包覆模具或介電塊上之跡線36。相似地，可在需要時將阻焊劑提供於封裝基板之導電特徵上。可以任何習知方式來塗覆及圖案化此阻焊劑。阻焊劑用來限制焊料沿著跡線之表面的展佈。
當然，上文參看圖1至圖10A所論述之配置可以許多方式而變化。舉例而言，將導電特徵(諸如，跡線62)描繪為位於封裝基板56之底部表面上。然而，跡線可安置於封裝基板之頂部表面上，或甚至安置於封裝基板內。此外，封裝基板可包括一個以上跡線層。
在一另外變體(圖10B)中，上文所論述之程序被修改之處在於：在引入介電組合物以形成介電塊之前，不將載體薄片上之跡線連接至封裝基板之導電特徵。眾多跡線36a沿著介電塊之第一邊緣表面96'而延伸。跡線36'經形成而使底部部分78'沿著介電塊之凸緣表面104'而延伸，但跡線36'在模製操作之前不連接至導電特徵(諸如，封裝基板56'上之跡線62')。在移除載體或薄片(未圖示)之前或之後，通過介電塊之凸緣部分107(亦即，安置於凸緣表面104'之下的部分)而形成通孔105。導體109安置於此等通孔內且將跡線之底部部分78'連接至介電基板56'之導電元件。在圖10B所描繪之特定實施例中，通孔係由基板之底部表面形成且因此延伸通過基板，以及通過介電塊或包覆模具之凸緣部分107，使得通孔自封裝基板之底部表面上的跡線62'到達介電塊上之跡線36'之底部部分78'。將跡線之底部部分78'定位成接近於封裝基板會極大地促進通孔105之形成。換言之，在封裝基板與凸緣表面104'之間的距離D1 顯著地小於在封裝基板與頂部表面之間的距離DT 。因此，必須藉由通孔穿透之距離比在介電塊具有延伸於整個封裝基板之上的平坦頂部表面之狀況下的距離小得多，使得整個介電塊具有等於DT 之厚度。此情形促進形成容納相對緊密隔開之跡線所必要的相對小直徑通孔。
在其他實施例中，通孔105無需穿透通過封裝基板。舉例而言，在導電元件包括在封裝基板56'之頂部表面上的跡線時，通孔可由凸緣表面形成且僅穿透通過介電塊或包覆模具之凸緣部分107。
根據本發明之另外實施例之程序(圖11及圖12)相似於上文所論述之程序，惟跡線236及頂部端子238被攜載於介電薄片230上除外。介電薄片係以相似於上文所論述之方式的方式而變形且定位於封裝基板256與微電子元件248之集合體之上。因此，載體之第一部分240及跡線236之對應第一部分延伸於微電子元件之上，而載體薄片之第二部分242及位於第二部分242上的跡線236之彼等部分自第一部分240朝向封裝基板256而延伸。再次，在薄片與封裝基板之間及圍繞微電子元件引入可流動組合物，且固化可流動組合物，以便形成覆蓋微電子元件且具有至少部分地藉由薄片230界定之形狀的介電塊或包覆模具286。此處，再次，塊或包覆模具包括凸緣表面204及下伏於該等凸緣表面之凸緣部分。跡線236之部分278上覆於凸緣部分，且因此經安置成鄰近於封裝基板且安置於相比於頂部端子238及該跡線之鄰近部分更接近於封裝基板之距離處。在此實施例中，在引入介電組合物之前，不將跡線之底部部分278連接至封裝基板之導電特徵。取而代之，通過塊之凸緣部分及通過薄片230之對應部分而形成通孔，且在此等通孔內形成通孔導體209以將跡線之底部部分278連接至封裝基板之導電元件(諸如，跡線262)。
亦在此實施例中，在薄片及封裝基板保持呈併入形成眾多個別封裝之元件之連續或半連續薄片或帶子的形式時，可執行處置薄片且模製介電塊之程序。可在形成通孔及通孔導體209之前或之後將封裝自彼此切開。
如圖12所描繪之已完成封裝將薄片230之部分併入為封裝結構之部件。理想地，薄片230黏附至介電塊286。出於此目的，薄片230可在表面231處併入黏附劑，表面231在模製程序期間面朝封裝基板。因此，介電薄片230形成緊密地上覆於介電塊286且在最終產品中黏附至介電塊286之層。在其他實施例中，可流動介電材料自身可充當將所形成之介電塊結合至薄片的黏附劑。僅僅舉例而言，薄片可包括普遍地用於可撓性印刷電路中之材料，如(例如)聚醯亞胺及BT樹脂。又，可在使薄片變形之前將阻焊劑(未圖示)塗覆遍及薄片上之跡線，其限制條件為阻焊劑可耐受在模製程序期間所使用之溫度及壓力。
根據本發明之另外實施例之程序(圖13)使用一對模具元件382及384以形成介電塊386。在此程序中，在模製時不存在載體及跡線。介電塊具有相似於上文所論述之組態的組態，且再次包括界定凸緣表面304之凸緣部分307，以及頂部表面394及一或多個邊緣表面396。此處，再次，邊緣表面自頂部表面394處之頂部邊界延伸至安置於封裝基板356之區域內的底部邊界398。如上文所論述，當自較大薄片或帶子切開封裝基板356時，可在模製步驟之後界定封裝基板之邊緣396。
在模製程序之後，將攜載跡線336及頂部端子338之薄片330施加於介電塊之頂部表面394之上且施加於邊緣表面396及凸緣表面304之上。此處，再次，跡線之底部部分經安置成鄰近於封裝基板356，使得可容易地通過介電塊或包覆模具之相對薄凸緣部分307而形成通孔。通孔導體309安置於通孔中且將薄片上之跡線336電連接至封裝基板之導電元件362。在圖14所描繪之特定實施例中，薄片330係藉由黏附劑之薄層301而結合至介電塊。又，薄片攜載阻焊劑層303。
根據另外實施例之程序使用相似於上文所論述之集合體的集合體446，惟微電子元件或晶片448相對於封裝基板456定位於「面向下」定向上除外。封裝基板併入導電元件，導電元件包括在封裝基板之上部表面上的跡線463、在封裝基板之下部表面上的額外跡線462、底部端子464，及將上部表面跡線463與下部表面跡線及底部端子連接之直通導體(through conductor)465。微電子元件或晶片448之接點454結合至上部表面導電元件463(如(例如)藉由焊接結合件)。介電塊或包覆模具486係使用相似於上文參看圖13所論述之模具元件的模具元件而形成，且具有相似組態。自向上面對之凸緣表面404至上部表面導電元件463通過介電塊之凸緣部分而形成通孔405。可在模製程序期間形成通孔405(如(例如)藉由嚙合該等上部表面導電元件的在模具上之凸塊或突起)。或者，可在模製之後藉由諸如雷射切除、蝕刻、噴砂處理或其類似者之程序來形成通孔405。在另外替代例中，可部分地藉由模具之特徵且部分地藉由後模製處理來形成通孔405。在形成介電塊或包覆模具486及通孔405之後，使用黏附劑層(未圖示)將攜載跡線436及頂部端子438之介電薄片430安裝於介電塊上。在此實施例中，薄片430攜載面朝介電塊的薄片之表面上的跡線436。因此，端子438通過薄片中之開口439而曝露於塊之頂部表面494處。可在將薄片430組裝至包覆模具之前或之後形成此等開口。跡線436之底部部分478係藉由安置於通孔405內之結合件409而結合至封裝基板456之上部表面導電元件463。僅僅舉例而言，可藉由焊接、共熔結合、熱超音波結合或其類似者來形成此等結合件。結合材料可被攜載於跡線436上或可沈積至通孔中。此處，再次，跡線底部部分478與封裝基板之近接促進結合程序及小結合件之使用，其又准許跡線底部部分之緊密間距。眾多跡線可被容納於該結構上。可將圖15及圖16所示之類型的封裝基板及微電子元件用於上文所論述之程序及結構中。又，可將介電薄片430(其中跡線係在面朝封裝基板之側面上)用於相似於圖11及圖12之程序的程序中，其中將薄片置放至模具中且藉由與薄片接觸來塑形介電塊。在此狀況下，理想地在模製程序之後形成開口439。
根據本發明之另外實施例之程序(圖17及圖18)在集合體546上形成介電塊，類似於上文參看圖15及圖16所論述之集合體，集合體546具有在面向下定向上之微電子元件，其中接點554面朝封裝基板556，使得該等接點接合至該封裝基板上之導電元件。此處，再次，集合體包括被攜載於封裝基板556之下部表面上的底部端子564。圖17所描繪之特定集合體包括安置於在微電子元件或晶片548與封裝基板上部表面之間的空間內的底部填料501。底部填料理想地環繞在微電子元件與封裝基板之導電元件之間的連接件503。
在該程序中使用具有第一表面507及第二表面509之保形介電層505。當將保形層施加至集合體546時，保形層下垂而與封裝基板556之上部表面558接觸、與微電子元件548之曝露表面接觸且與底部填料501接觸。因此，在將保形層施加至集合體時，保形層應具有足以按此方式保形之柔軟度及可變形性。僅僅舉例而言，保形層可為「B級(B-stage)」或經部分固化之環氧樹脂組合物，其可視情況含有微粒填充物材料。在施加之後，可硬化保形層(如(例如)藉由化學反應)。隨著保形層變形以覆蓋集合體546之曝露元件，保形層之第一部分界定遠離於封裝基板556且延伸於微電子元件548之上的頂部表面594(圖18)，而保形層之額外部分界定邊緣表面596，邊緣表面596在封裝基板之區域中朝向封裝基板而向下延伸於藉由微電子元件548覆蓋之區域外部。
在施加及固化保形層之後，將跡線536及頂部端子538形成於經固化層上。舉例而言，可電鍍、遮蔽及選擇性地蝕刻整個保形層以形成頂部端子及跡線。或者，可用遮罩材料來覆蓋保形層之表面，且接著將保形層之表面選擇性地曝露至雷射輻射以通過遮罩而切割溝槽。可將晶種層施加於遮罩之上且施加至溝槽中，隨之移除遮罩，以便在除了在溝槽處以外之任何地方起離晶種層。接著將表面曝露至電鍍浴，使得金屬僅沈積於存在晶種之溝槽處。可使用用於在介電本體上形成金屬特徵之任何其他技術。此處，再次，頂部端子曝露於頂部表面594上，且跡線536自頂部端子中之至少一些沿著頂部表面594而延伸且亦沿著邊緣表面596朝向封裝表面556而向下延伸。亦在此實施例中，跡線之底部部分578經安置成與封裝基板相隔距離D578 ，距離D578 小於在封裝基板與頂部表面594之間的距離D594 且因此小於在封裝基板與端子538之間的距離。此處，再次，高度差促進底部部分至封裝基板之導電元件的連接。在圖18之特定實施例中，保形層形成界定凸緣表面504之凸緣部分507，且跡線之底部部分578沿著該等凸緣表面而延伸。藉由通過凸緣部分而形成通孔且將通孔導體509沈積於此等通孔中而將底部部分連接至基板之導電元件。
在使用具有用於眾多封裝之跡線及端子之連續或半連續保形層的情況下，可使用經形成為具有共同封裝基板之許多集合體之大薄片的集合體來進行施加保形層之程序(類似於上文所論述之其他程序)。在施加保形層之後，將集合體自彼此切開。
應瞭解，圖式未按比例。舉例而言，出於說明清晰性起見而極大地誇示微電子元件548及保形層自身之垂直尺寸。實務上，自封裝基板至頂部表面及頂部端子之高度或距離D594 可為大約幾百微米或更小，普遍地為約400微米或更小，而跡線之底部部分578安置於在封裝基板上方之甚至更小高度D578 處。保形層形成封裝之介電塊。在此方面，術語「介電塊」不暗示任何特定最小厚度或形狀。
在上文參看圖17及圖18所論述之程序之變體中，將保形層施加至集合體546，其中跡線536及頂部接點538已經處於保形層上之適當位置。舉例而言，保形層自身可包括複數個子層，諸如，承載頂部接點及端子之可撓性頂部層，及諸如B級環氧樹脂之保形底部層。
可利用上文所論述之特徵之眾多另外變化及組合。僅僅舉例而言，介電塊可具有一個、兩個或兩個以上邊緣表面，其中跡線延伸於邊緣表面上。又，封裝可包括一個以上的微電子元件。僅僅舉例而言，圖19所描繪之封裝相似於上文參看圖1至圖10A所論述之封裝，但將兩個微電子元件748併入於介電塊786中。
根據本發明之另外實施例之封裝(圖20)併入大體上相似於上文參看(例如)圖9至圖10A及圖10B所論述之封裝之對應元件的微電子元件848及封裝基板856。亦在此實施例中，微電子元件848電連接至封裝基板856上之導電元件且係藉由第一介電塊886覆蓋。此處，再次，此介電塊界定頂部表面894，及自頂部表面894朝向封裝基板而延伸之第一邊緣表面896。介電塊亦包括在第一水平方向H1 (在圖20中向右)上向外突出之凸緣部分804。
然而，在圖20之實施例中，基板856延伸超出凸緣部分804。輔助介電塊847安置於封裝基板之此突起部分上，輔助介電塊847界定與第一介電塊886之頂部表面894共平面的頂部表面897。輔助介電塊亦界定自頂部表面897朝向封裝基板向下延伸之邊緣表面895。邊緣表面895在與第一水平方向對置之第二水平方向H2 上傾斜，使得第一介電塊886之第一邊緣表面896及輔助介電塊847之邊緣表面895在向下方向上朝向封裝基板856彼此會聚。此等邊緣表面合作地界定自頂部表面894及897向下延伸之渠溝。渠溝及邊緣表面為延伸至圖式之平面中及自圖式之平面中延伸出的狹長結構，如在圖20中所見。輔助介電塊847界定自邊緣表面895之底部邊界朝向微電子元件848向內突出的凸緣區帶803。凸緣區帶803與第一介電塊886之凸緣區帶804合併。應瞭解，儘管分離地描述此等介電塊及部分，但事實上，其為單式介電本體之部分。
如在上文所論述之實施例中，頂部端子838曝露於第一介電塊886之頂部表面894處。連接至頂部端子中之至少一些的跡線836沿著塊886之第一邊緣表面896而延伸，且具有連接至封裝基板之導電元件的底部部分。然而，在圖20之實施例中，輔助頂部端子837曝露於輔助介電塊847之頂部表面897處。跡線833自此等輔助頂部端子中之至少一些沿著輔助塊之頂部表面897及沿著輔助塊847之傾斜邊緣表面895而延伸。經安置成鄰近於封裝基板856的跡線833之底部部分亦連接至該封裝基板之導電元件。如在上文所論述之實施例中，封裝基板界定與第一介電塊886對準且與藉由該第一介電塊攜載之頂部端子838對準的底部端子陣列。在圖20之實施例中，封裝基板亦界定與被攜載於輔助塊847上之輔助頂部端子837對準的輔助底部端子857。
在此實施例中，第一介電塊886亦具有在第二水平方向H2 上傾斜之第二邊緣表面808，且跡線836中之一些自頂部端子838中之一些沿著第二邊緣表面808而延伸。介電本體包括第二輔助塊809，第二輔助塊809具有曝露於此塊之頂部表面處的輔助頂部端子811，且具有自該塊之頂部表面向下延伸且在第一水平方向H1 上傾斜的邊緣表面813，使得邊緣表面813與第一介電塊886之第二邊緣表面808會聚。此等邊緣表面合作地界定延伸至圖式之平面中及自圖式之平面中延伸出的另外狹長渠溝，如在圖20中所見。額外輔助跡線815沿著額外輔助塊809之邊緣表面而延伸。此等跡線連接至封裝基板856之導電元件。封裝基板界定與額外輔助頂部端子811對準之額外輔助底部端子817。輔助塊809界定凸緣區帶，該凸緣區帶與第一介電塊886之第二邊緣表面808之底部處的凸緣區帶合併。此處，再次，額外輔助塊809及第一介電塊886形成單式介電本體之部件。
輔助介電塊中每一者可攜載一列或一列以上頂部接點811、837。此等頂部接點及與此等頂部接點對準之輔助底部接點857、817提供在封裝堆疊中信號之額外連接性及額外投送。如圖20所示之封裝可堆疊於彼此頂部，其中輔助頂部接點與堆疊中之次較高封裝之輔助底部接點對準。第一介電塊之頂部接點838與堆疊中之次較高封裝之底部接點864對準。
如圖20所描繪之封裝可藉由基本上相同於上文所論述之方法的方法予以製造，且可併入上文所論述之特徵。僅僅舉例而言，在圖21所描繪之成品封裝中不存在用以形成封裝之薄片或載體。然而，具有輔助介電塊之封裝可併入諸如參看圖11、圖12及圖16所論述之介電薄片的特徵。在又一變體中，一或多個微電子元件可安置於輔助塊中之一或多者內。
根據本發明之另外實施例之封裝(圖21)相似於圖20之封裝之處在於：圖21之封裝包括具有第一邊緣表面696及第二邊緣表面608之第一或主要介電塊686。封裝進一步包括：第一輔助介電塊647，其具有與塊686之第一邊緣表面696會聚的傾斜邊緣表面695；及第二輔助介電塊，其具有與塊686之第二邊緣表面608會聚的傾斜邊緣表面613。此處，再次，出於增加連接性起見，將輔助頂部接點637及611提供於輔助介電塊上，且將輔助底部接點617及657提供於基裝基板之底部表面上。然而，圖21之封裝中的介電塊不包括凸緣表面。因此，邊緣表面696、608、695及613自始至終延伸至封裝基板656之上部表面658。跡線沿著邊緣表面而向下延伸，使得每一跡線之底部部分終止於邊緣表面之底部處，其中跡線接合封裝基板之上部表面上的導電元件663。
在又一變化中，用以固持跡線及頂部端子之載體可為除了薄片以外之元件。舉例而言，可將跡線及端子沈積至模具元件上，接著使用模具元件以形成介電塊之頂部表面及邊緣表面。當移除模具時，頂部端子及跡線以與上文參看圖1至圖10A所論述之方式大致相同的方式保持嵌入於介電塊中。
可將上文所論述之封裝用於互異電子系統之構造中。舉例而言，根據本發明之另外實施例之系統900(圖22)包括如上文結合堆疊904(併入如上文所描述之兩個封裝)以及結合其他電子組件908及910所描述之第一封裝902。在所描繪實例中，組件908為半導體晶片，而組件910為顯示螢幕，但可使用任何其他組件。當然，儘管出於說明清晰性起見而在圖22中僅描繪兩個額外組件，但系統可包括任何數目個此等組件。封裝902及904以及組件908及910安裝至共同外殼901(以摺線示意性地描繪)，且在必要時彼此電互連以形成所要電路。在所示之例示性系統中，該系統包括電路面板907(諸如，可撓性或剛性印刷電路板)，且該電路面板包括使組件彼此互連之眾多導體909，圖22中僅描繪導體909中之一者。板外連接器911將組件910連接至電路面板。然而，此情形僅僅係例示性的；可使用用於進行電連接之任何合適結構。將外殼901描繪為可用於(例如)蜂巢式電話或個人數位助理中之類型的攜帶型外殼，且螢幕910曝露於該外殼之表面處。再次，圖22所示之簡化系統僅僅係例示性的；可使用上文所論述之封裝來製造其他系統(包括被普遍地視為固定結構之系統，諸如，桌上型電腦、路由器及其類似者)。
由於可在不脫離本發明之情況下利用上文所論述之特徵之此等及其他變化與組合，故應藉由說明而非限制如藉由申請專利範圍所界定之本發明來採取較佳實施例之上述描述。
30．．．金屬薄片/載體薄片
32．．．第一表面
34．．．第二表面
36．．．導電跡線
36'．．．跡線
36a．．．跡線
36b．．．跡線
38．．．頂部端子
40．．．第一部分
42．．．第二部分
46．．．集合體/封裝基板
48．．．微電子元件/晶片
50．．．前表面
52．．．後表面
54．．．接點
56．．．介電結構/封裝基板
56'．．．封裝基板/介電基板
58．．．頂部表面/上部表面
60．．．底部表面/下部表面
62．．．跡線
62'．．．跡線
64．．．底部端子
66．．．導線結合件
68．．．孔隙
70．．．傾斜區帶
74．．．凸緣區帶/凸緣部分
76．．．傾斜部分
78．．．底部部分
78'．．．底部部分
80．．．焊接結合件
82．．．第一側面/模具元件
84．．．第二側面/模具元件
86．．．包覆模具
88．．．分離線
90．．．微電子封裝
90a．．．底部封裝
90b．．．次較高封裝
92．．．邊緣
94．．．頂部表面
96．．．第一邊緣表面
96'．．．第一邊緣表面
98．．．頂部邊界
100．．．底部邊界
102．．．虛線
104．．．第一凸緣表面
104'．．．凸緣表面
105．．．通孔
107．．．凸緣部分
108．．．第二邊緣表面
109．．．導體
110．．．第二凸緣表面
112．．．接觸焊墊
114．．．電路基板
204．．．凸緣表面
209．．．通孔導體
230．．．介電薄片
231．．．表面
236．．．跡線
238．．．頂部端子
240．．．第一部分
242．．．第二部分
248．．．微電子元件
256．．．封裝基板
262．．．跡線
286．．．介電塊/包覆模具
301．．．黏附劑之薄層
303．．．阻焊劑層
304．．．凸緣表面
307．．．凸緣部分
309．．．通孔導體
330．．．薄片
336．．．跡線
338．．．頂部端子
356．．．封裝基板
362．．．導電元件
382．．．模具元件
386．．．介電塊
394．．．頂部表面
396．．．邊緣表面
398．．．底部邊界
404．．．凸緣表面
405．．．通孔
409．．．結合件
430．．．介電薄片
436．．．跡線
438．．．頂部端子
439．．．開口
446．．．集合體
448．．．微電子元件/晶片
454．．．接點
456．．．封裝基板
462．．．額外跡線
463．．．上部表面跡線/上部表面導電元件
464．．．底部端子
465．．．直通導體
478．．．底部部分
486．．．介電塊/包覆模具
494．．．頂部表面
501．．．底部填料
503．．．連接件
504．．．凸緣表面
505．．．保形介電層
507．．．第一表面/凸緣部分
509．．．第二表面/通孔導體
536．．．跡線
538．．．頂部端子/頂部接點
546．．．集合體
548．．．微電子元件/晶片
554．．．接點
556．．．封裝基板/封裝表面
558．．．上部表面
564．．．底部端子
578．．．底部部分
594．．．頂部表面
596．．．邊緣表面
608．．．第二邊緣表面
611．．．輔助頂部接點
613．．．傾斜邊緣表面
617．．．輔助底部接點
637．．．輔助頂部接點
647．．．第一輔助介電塊
656．．．封裝基板
657．．．輔助底部接點
658．．．上部表面
663．．．導電元件
686．．．第一或主要介電塊
695．．．傾斜邊緣表面
696．．．第一邊緣表面
748．．．微電子元件
786．．．介電塊
803．．．凸緣區帶
804．．．凸緣部分/凸緣區帶
808．．．第二邊緣表面
809．．．第二輔助塊/額外輔助塊
811．．．輔助頂部端子/頂部接點
813．．．邊緣表面
815．．．額外輔助跡線
817．．．額外輔助底部端子/輔助底部接點
833．．．跡線
836．．．跡線
837．．．輔助頂部端子/頂部接點
838．．．頂部端子/頂部接點
847．．．輔助介電塊
848．．．微電子元件
856．．．封裝基板
857．．．輔助底部端子/輔助底部接點
864．．．底部接點
886．．．第一介電塊
894．．．頂部表面
895．．．邊緣表面
896．．．第一邊緣表面
897．．．頂部表面
900．．．系統
901．．．外殼
902．．．第一封裝
904．．．堆疊/封裝
907．．．電路面板
908．．．電子組件
909．．．導體
910．．．電子組件/螢幕
D1 ．．．距離
D578 ．．．距離/高度
D594 ．．．距離/高度
DT ．．．距離
H1 ．．．第一水平方向
H2 ．．．第二水平方向
圖1為根據本發明之一實施例的用於製造封裝之方法中之組件的圖解仰視平面圖。
圖2為圖1所描繪之組件的圖解正視圖。
圖3為描繪使用圖1及圖2之組件之製造步驟的圖解剖視圖。
圖4為相似於圖3的圖解剖視圖，但其描繪在製造程序中之較遲階段的組件及關聯元件。
圖5為相似於圖3及圖4的圖解剖視圖，其描繪在製造操作中之較遲階段的組件及關聯元件。
圖6為相似於圖3至圖5的視圖，但其描繪製造中之仍較遲階段。
圖7為描繪使用圖3至圖6之製造程序所製造之封裝的圖解俯視平面圖。
圖8為沿著圖7中之線8-8所截取之在放大比例尺上的片斷剖視圖。
圖9為圖7所描繪之封裝結合另一封裝的圖解剖視圖。
圖10A為展示圖9之封裝之部分之在放大比例尺上的片斷剖視圖。
圖10B為根據本發明之另外實施例的描繪封裝之部分的片斷剖視圖。
圖11為根據本發明之另外實施例的描繪製造程序之部分的片斷剖視圖。
圖12為描繪在圖11之程序中所製造之封裝之部分的片斷剖視圖。
圖13為根據本發明之又一實施例的描繪製造程序中之階段的片斷剖視圖。
圖14為描繪使用圖13之程序所製造之封裝之部分的片斷剖視圖。
圖15為根據本發明之又一實施例的描繪製造程序中之階段的片斷剖視圖。
圖16為描繪在圖15之程序中所製造之封裝之部分的片斷剖視圖。
圖17為根據本發明之又一實施例的描繪製造程序中之階段的圖解剖視圖。
圖18為描繪在圖17之程序中所製造之封裝的剖視圖。
圖19為根據本發明之又一實施例之封裝的圖解剖視圖。
圖20為根據本發明之另外實施例之封裝的圖解剖視圖。
圖21為根據本發明之又一實施例的描繪封裝的圖解剖視圖。
圖22為根據本發明之一實施例的描繪系統的圖解視圖。
38．．．頂部端子
48．．．微電子元件/晶片
54．．．接點
56．．．介電結構/封裝基板
58．．．頂部表面/上部表面
60．．．底部表面/下部表面
62．．．跡線
64．．．底部端子
78．．．底部部分
86．．．包覆模具
90a．．．底部封裝
90b．．．次較高封裝
92．．．邊緣
94．．．頂部表面
96．．．第一邊緣表面
98．．．頂部邊界
100．．．底部邊界
108．．．第二邊緣表面
110．．．第二凸緣表面
112．．．接觸焊墊
114．．．電路基板
H1 ．．．第一水平方向
H2 ．．．第二水平方向

Claims (42)

  1. 一種微電子封裝，其包含：(a)一第一微電子元件；(b)一封裝基板，其具有延伸於水平方向上之上部表面及下部表面，以及延伸於該上部表面與該下部表面之間的邊緣；(c)導電元件，其係在該封裝基板上，該等導電元件包括曝露於該封裝基板之該下部表面處的底部端子，該第一微電子元件安置於該封裝基板之該上部表面之上，該第一微電子元件電連接至該封裝基板上之該等導電元件中至少一些；(d)一第一介電塊，其覆蓋該第一微電子元件及該封裝基板之該上部表面之至少一部分，該第一介電塊界定背對該封裝基板的遠離於該封裝基板之一頂部表面，該頂部表面之至少一部分延伸於該微電子元件之上，該第一介電塊亦界定一第一邊緣表面，該第一邊緣表面自鄰近於該第一介電塊之該頂部表面的一頂部邊界向下延伸至鄰近於該封裝基板且在該封裝基板之該等邊緣內部的一底部邊界，該第一介電塊進一步界定一向上面對之第一凸緣表面，該第一凸緣表面鄰近於該封裝基板在一水平方向上延伸離開該第一邊緣表面之該底部邊界，該第一凸緣表面經安置成與該封裝基板相隔一垂直距離，該垂直距離小於在該封裝基板與該頂部表面之間的一垂直距離； (e)複數個頂部端子，其曝露於該第一介電塊之該頂部表面處；及(f)複數個第一跡線，其自該等頂部端子沿著該頂部表面而延伸且沿著該第一邊緣表面而延伸，該等第一跡線使底部部分沿著該第一凸緣表面而延伸，該等底部部分電連接至該封裝基板之該等導電元件。
  2. 如請求項1之封裝，其中該第一邊緣表面在一第一水平方向上傾斜離開該第一微電子元件，使得該底部邊界比該頂部邊界更遠離於該第一微電子元件。
  3. 如請求項2之封裝，其中該第一介電塊之該第一邊緣表面經塑形成使得沿著該第一邊緣表面而延伸成與該封裝基板相隔一恆定垂直距離之一直線在該第一水平方向上具有一恆定部位。
  4. 如請求項2之封裝，其中該第一介電塊之該第一邊緣表面係大體上平面的。
  5. 如請求項2之封裝，其中該第一介電塊界定自鄰近於該第一介電塊之該頂部表面的一頂部邊界向下延伸至鄰近於該封裝基板之一底部邊界的一第二邊緣表面，該第二邊緣表面在一第二水平方向上傾斜離開該第一微電子元件，使得該底部邊界比該頂部邊界更遠離於該第一微電子元件，該封裝進一步包含第二跡線，該等第二跡線沿著該第一介電塊之該頂部表面而延伸且沿著該第二邊緣表面向下延伸至鄰近於該封裝基板之底部部分。
  6. 如請求項5之封裝，其中該第二水平方向與該第一水平 方向對置。
  7. 如請求項1之封裝，其中該複數個第一跡線沿著該第一邊緣表面彼此實質上平行地延伸。
  8. 如請求項1之封裝，其中該等第一跡線嵌入於該第一介電塊之該第一邊緣表面及該頂部表面中。
  9. 如請求項1之封裝，其中該等頂部端子係與該等第一跡線成一體式且嵌入於該第一介電塊之該頂部表面中。
  10. 如請求項1之封裝，其中該等第一跡線延伸於該第一邊緣表面及該頂部表面之上。
  11. 如請求項10之封裝，其進一步包含在該等第一跡線與該第一邊緣表面及該頂部表面之間的一黏附劑層。
  12. 如請求項1之封裝，其進一步包含導電通孔連接器，該等導電通孔連接器延伸通過該第一介電塊之該第一凸緣表面且將該等第一跡線之該等底部部分與該封裝基板之該等導電元件進行電連接。
  13. 如請求項1之封裝，其中該第一介電塊為一包覆模具。
  14. 如請求項1之封裝，其中該第一介電塊為一保形層，該保形層具有延伸於該第一微電子元件之上的一部分，該部分界定該頂部表面且具有凸緣區帶，該等凸緣區帶安置於未藉由該第一微電子元件覆蓋的該上部表面之區帶上。
  15. 如請求項1之封裝，其進一步包含一第二微電子元件，該第二微電子元件安置於該第一介電塊內且電連接至該第一微電子元件、該等頂部端子及該等底部端子中至少 一者。
  16. 如請求項1之封裝，其中該等頂部端子中至少一些上覆於該第一微電子元件。
  17. 如請求項16之封裝，其中該等頂部端子係以一區域陣列而安置。
  18. 如請求項17之封裝，其中該等底部端子包括與該等頂部端子中至少一些對準之中心端子。
  19. 如請求項1之封裝，其進一步包含覆蓋該封裝基板之一部分的一輔助介電塊，該輔助介電塊界定遠離於該封裝基板之一輔助頂部表面，該封裝進一步包含曝露於該輔助頂部表面處之輔助頂部端子，該等輔助頂部端子中至少一些電連接至該封裝基板之該等導電元件。
  20. 如請求項19之封裝，其中該輔助介電塊界定自該輔助頂部表面朝向該封裝基板而延伸之一輔助邊緣表面，該輔助邊緣表面及該第一邊緣表面合作地界定一狹長渠溝，該封裝進一步包含沿著該輔助邊緣表面而延伸之輔助跡線，該等輔助頂部端子係經由該等輔助跡線而連接至該封裝基板之該等導電元件。
  21. 一種包括如請求項18之第一微電子封裝及第二微電子封裝的總成，該第二微電子封裝之該等中心端子係與該第一微電子封裝之該等頂部端子對準且結合至該第一微電子封裝之該等頂部端子。
  22. 一種包括如請求項1之一微電子封裝及一第二微電子元件的總成，該第二微電子元件電連接至該微電子封裝之 該等頂部端子。
  23. 一種微電子封裝，其包含：(a)一微電子元件；(b)一封裝基板，其具有延伸於水平方向上之上部表面及下部表面，該微電子元件安置於該封裝基板之該上部表面之上；(c)一包覆模具，其覆蓋該微電子元件及該微電子元件之該上部表面之至少一部分，該包覆模具界定背對該封裝基板的遠離於該封裝基板之一頂部表面，該包覆模具頂部表面之至少一部分延伸於該微電子元件之上，該包覆模具亦界定一第一邊緣表面，該第一邊緣表面自鄰近於該包覆模具之該頂部表面的一頂部邊界向下延伸至鄰近於該封裝基板且在該封裝基板之該等邊緣內部的一底部邊界，該包覆模具進一步界定一向上面對之第一凸緣表面，該第一凸緣表面鄰近於該封裝基板在一水平方向上延伸離開該第一邊緣表面之該底部邊界，該第一凸緣表面經安置成與該封裝基板相隔一垂直距離，該垂直距離小於在該封裝基板與該頂部表面之間的一垂直距離；及(d)頂部端子，其曝露於該包覆模具之該頂部表面處；及(e)複數個固體金屬跡線，其自該等頂部端子沿著該包覆模具之該頂部表面而延伸，該等頂部端子及該等跡線嵌入於該包覆模具中。
  24. 如請求項23之封裝，其中該封裝基板具有在其上之導電 元件，該等頂部端子中至少一些電連接至該等導電元件中至少一些。
  25. 如請求項24之封裝，其中該封裝基板之該等導電元件包括曝露於該封裝基板之該下部表面處的底部端子。
  26. 如請求項23之封裝，其中該等頂部端子中至少一些上覆於該微電子元件。
  27. 一種包含如請求項1及23中任一項之一微電子封裝及一或多個其他電子組件的系統，該一或多個其他電子組件電連接至該微電子封裝。
  28. 如請求項27之系統，其進一步包含一外殼，該微電子封裝及該等其他電子組件安裝至該外殼。
  29. 一種製造一微電子封裝之方法，其包含以下步驟：(a)將承載複數個跡線之一薄片定位於具有導電元件之一封裝基板與上覆於該封裝基板且電連接至該等導電元件之一微電子元件的一集合體之上，使得該等跡線中至少一些之部分延伸於該微電子元件之上；(b)在該薄片與該封裝基板之間及圍繞該微電子元件引入一可流動組合物，且固化該組合物以形成覆蓋該微電子元件且具有藉由該薄片至少部分地界定之一形狀之一包覆模具；及(c)移除該薄片，以便使該等跡線延伸於背對該封裝基板的該包覆模具之一或多個表面之上。
  30. 如請求項29之方法，其中定位該薄片之該步驟包括：定 位該薄片之一第一部分及在該薄片之該第一部分上的該等跡線之第一部分，該等跡線之該等第一部分延伸於該微電子元件之上；及定位該薄片之一第二部分，使得該薄片之該第二部分及在該薄片之該第二部分上的該等跡線之第二部分自該薄片之該第一部分朝向該封裝基板而延伸。
  31. 如請求項30之方法，其中該定位步驟包括使該薄片變形。
  32. 如請求項29之方法，其中執行該定位步驟，使得承載該等跡線的該薄片之一表面面朝該封裝基板，且執行該引入步驟，使得該可流動組合物部分地環繞該等跡線。
  33. 如請求項32之方法，其中該薄片係由一金屬材料形成，且移除該薄片之該步驟包括蝕刻該薄片之該金屬材料。
  34. 一種製造一微電子封裝之方法，其包含以下步驟：(a)將承載複數個跡線之一薄片定位於具有導電元件之一封裝基板與上覆於該封裝基板且電連接至該等導電元件之一微電子元件的一集合體之上，執行該定位步驟，使得該薄片之一第一部分及在該薄片之該第一部分上的該等跡線之第一部分延伸於該微電子元件之上，且該薄片之一第二部分及在該薄片之該第二部分上的該等跡線之第二部分自該第一部分朝向該封裝基板而延伸；(b)在該薄片與該封裝基板之間及圍繞該微電子元件引入一可流動組合物；(c)固化該組合物以形成覆蓋該微電子元件且具有藉由 (d)將該等跡線之該等第二部分與該封裝基板之該等導電元件進行電連接。
  35. 如請求項34之方法，其中在引入該可流動組合物之該步驟之前執行將該等跡線之該等第二部分與該等導電元件進行電連接之該步驟。
  36. 如請求項34之方法，其中執行定位該薄片且引入及固化該可流動組合物之該等步驟，使得該包覆模具包括界定延伸於該微電子元件之上的一頂部表面的一主要部分、界限該主要部分且朝向該微電子元件而向下延伸之一第一邊緣表面，及自該第一邊緣表面向外延伸的薄於該主要部分之一凸緣部分，且使得該等跡線之該等第二部分包括延伸於該凸緣部分之上的底部部分，電連接該等第二部分之該步驟包括通過該包覆模具之該凸緣部分而形成連接件。
  37. 如請求項36之方法，其進一步包含如下步驟：在該包覆模具之該凸緣部分中形成延伸於該等跡線之該等底部部分與該封裝基板之間的通孔，通過該凸緣部分而形成連接件之該步驟包括在該等通孔中形成通孔導體。
  38. 如請求項37之方法，其中在引入及固化該組合物之該等步驟之後執行在該包覆模具之該凸緣部分中形成通孔之該步驟。
  39. 一種製造一微電子封裝之方法，其包含以下步驟：(a)將一保形介電層沈積至具有導電元件之一封裝基板與上覆於該封裝基板之一上部表面且電連接至該等導電 元件之一微電子元件的一集合體上，該等導電元件包括曝露於該封裝基板之一下部表面處的底部端子，執行該沈積步驟，使得該保形介電層之一第一部分界定遠離於該封裝基板且延伸於該微電子元件之上的一頂部表面，且一或多個額外部分界定一或多個邊緣表面，該一或多個邊緣表面朝向該封裝基板而向下延伸於藉由該微電子元件覆蓋之一區域外部；及(b)在該保形介電層上提供跡線及頂部端子，使得該等跡線沿著該頂部表面而延伸且沿著至少一邊緣表面朝向該封裝基板而延伸，且該等跡線之底部部分經定位成鄰近於該封裝基板；及(c)將該等跡線之該等底部部分連接至該封裝基板上之該等導電元件中至少一些，其中執行沈積一保形介電層之該步驟，使得該保形介電層形成至少一向上面對之凸緣表面，該至少一向上面對之凸緣表面自至少一邊緣表面之一底部邊界延伸，使得每一凸緣表面經安置成與該封裝基板相隔一垂直距離，該垂直距離小於在該封裝基板與該頂部表面之間的一垂直距離。
  40. 如請求項39之方法，其中執行提供跡線之該步驟，使得該等跡線之底部部分延伸於該至少一凸緣表面之上，且連接該等跡線之該等底部部分之該步驟包括形成連接件，使得該等連接件延伸通過該至少一凸緣表面。
  41. 如請求項40之方法，其中提供跡線及端子之該步驟包括 在將該保形層沈積至該集合體上之前於該層上提供該等跡線及該等端子。
  42. 如請求項41之方法，其中提供跡線及端子之該步驟包括在將該保形層沈積至該集合體上之後將該等跡線沈積至該層上。
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