TW330309B - Novel transistor with ultra shallow tip and method of fabrication - Google Patents

Novel transistor with ultra shallow tip and method of fabrication

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Publication number
TW330309B
TW330309B TW084113335A TW84113335A TW330309B TW 330309 B TW330309 B TW 330309B TW 084113335 A TW084113335 A TW 084113335A TW 84113335 A TW84113335 A TW 84113335A TW 330309 B TW330309 B TW 330309B
Authority
TW
Taiwan
Prior art keywords
forming
fabrication
wall spacers
ultra shallow
pair
Prior art date
Application number
TW084113335A
Other languages
English (en)
Inventor
S Chau Robert
Chern Chan-Hong
Jan Chia-Hong
R Weldon Kevin
A Packan Paul
D Yau Leopoldo
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of TW330309B publication Critical patent/TW330309B/zh

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    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
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    • H01L21/2257Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW084113335A 1994-12-23 1995-12-14 Novel transistor with ultra shallow tip and method of fabrication TW330309B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/363,749 US5710450A (en) 1994-12-23 1994-12-23 Transistor with ultra shallow tip and method of fabrication

Publications (1)

Publication Number Publication Date
TW330309B true TW330309B (en) 1998-04-21

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Application Number Title Priority Date Filing Date
TW084113335A TW330309B (en) 1994-12-23 1995-12-14 Novel transistor with ultra shallow tip and method of fabrication

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Country Link
US (3) US5710450A (zh)
EP (2) EP1253632A3 (zh)
JP (2) JPH10511506A (zh)
CN (1) CN1095196C (zh)
AU (1) AU4528396A (zh)
TW (1) TW330309B (zh)
WO (1) WO1996020499A1 (zh)

Families Citing this family (273)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3256084B2 (ja) 1994-05-26 2002-02-12 株式会社半導体エネルギー研究所 半導体集積回路およびその作製方法
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